Integrated circuit unit including column stack pins

Abstract

An integrated circuit (IC) cell includes: a first logic gate including a first polysilicon structure and a first pin; a second logic gate including a second polysilicon structure and a second pin, where the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a cell row direction; and the source electrode region is shared by the first logic gate and the second logic gate and is positioned between the first polycrystalline silicon structure and the second polycrystalline silicon structure, and the first pin and the second pin are positioned on the first metal trace right above the shared source electrode region.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the benefit of priority to U.S. Non - Provisional Application No. 17 / 993,594, filed on November 23, 2022, which is pending and assigned to the assignee of the present application, and is hereby incorporated by reference in its entirety as if fully set forth herein and for all applicable purposes. Technical Field

[0003] Aspects of the present disclosure generally relate to integrated circuits (ICs), and particularly to IC cells including columns or vertically - stacked pins. Background Art

[0004] Integrated circuits (ICs), such as system - on - a - chip (SOC), typically include combinational logic cells arranged in rows and columns. When designing such ICs, it is necessary to use the area or footprint of the IC in an efficient manner; for example, it is necessary to make the IC smaller and / or increase the number of IC cells for additional functions. However, designing such ICs to improve area utilization sometimes poses challenges and requires new IC cell design and layout methods. Summary of the Invention

[0005] The following presents a simplified summary of one or more specific implementations in order to provide a basic understanding of such specific implementations. This summary is not an exhaustive overview of all contemplated specific implementations, and is not intended to identify key or important elements of all specific implementations, nor to delineate the scope of any or all specific implementations. Its sole purpose is to present some concepts of one or more specific implementations in a simplified form as a prelude to the more detailed description that follows.

[0006] One aspect of the present disclosure relates to an integrated circuit (IC) cell. The IC cell includes: a first logic gate including a first polysilicon structure and a first pin; a second logic gate including a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in the cell row direction; and a source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are located on a first metal trace directly above the shared source region.

[0007] Another aspect of the present disclosure relates to a method. The method includes generating a first input logic signal; generating a second input logic signal; applying the first logic signal and the second logic signal to a first pin and a second pin of an integrated circuit (IC) unit, where the IC unit includes: a first logic gate including a first polysilicon structure and a first pin; a second logic gate including a second polysilicon structure and a second pin, where the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in the unit row direction; and a source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, where the first pin and the second pin are located on a first metal trace directly above the shared source region; receiving a first output logic signal from the IC unit, where the first output logic signal is based on the first input logic signal; and receiving a second output logic signal from the IC unit, where the second output logic signal is based on the second input logic signal.

[0008] Another aspect of the present disclosure relates to a wireless communication device. The wireless communication device includes: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) coupled to the transceiver, where the IC includes a set of one or more signal processing cores, the set of one or more signal processing cores including an IC unit, the IC unit including: a first logic gate including a first polysilicon structure and a first pin; a second logic gate including a second polysilicon structure and a second pin, where the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in the unit row direction; and a source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, where the first pin and the second pin are located on a first metal trace directly above the shared source region.

[0009] To achieve the foregoing and related purposes, one or more specific implementations include the features described in detail hereinafter and particularly pointed out in the claims. The following description and the appended drawings set forth in detail certain illustrative aspects of one or more specific implementations. However, these aspects are merely indicative of the various ways in which the principles of the various specific implementations may be employed, and the specification of the specific implementations is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A Illustrates a layout view of an example integrated circuit (IC) inverter unit according to an aspect of the present disclosure.

[0011] Figure 1B Illustrates a layout view of an example pair of adjacent integrated circuit (IC) inverter units according to another aspect of the present disclosure.

[0012] Figure 1C Illustrates a layout view of an exemplary multi-gate integrated circuit (IC) inverter cell according to another aspect of the present disclosure.

[0013] Figure 2A Illustrates a layout view of an exemplary row of integrated circuit (IC) cells according to another aspect of the present disclosure.

[0014] Figure 2B Illustrates a layout view of another exemplary row of integrated circuit (IC) cells according to another aspect of the present disclosure.

[0015] Figure 3A Illustrates a layout view of an exemplary multi-gate integrated circuit (IC) NAND gate cell according to another aspect of the present disclosure.

[0016] Figure 3B Illustrates a layout view of another exemplary multi-gate integrated circuit (IC) NAND gate cell according to another aspect of the present disclosure.

[0017] Figure 4 Illustrates a layout view of another exemplary multi-gate integrated circuit (IC) NAND gate cell according to another aspect of the present disclosure.

[0018] Figure 5 Illustrates a layout view of another exemplary multi-gate integrated circuit (IC) NAND gate cell according to another aspect of the present disclosure.

[0019] Figure 6 Illustrates a layout view of another exemplary multi-gate integrated circuit (IC) inverter cell according to another aspect of the present disclosure.

[0020] Figure 7 Illustrates a flowchart of an exemplary method of processing signals according to another aspect of the present disclosure.

[0021] Figure 8 Illustrates a block diagram of an exemplary wireless communication device according to another aspect of the present disclosure. Detailed Description

[0022] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. For a thorough understanding of the various concepts, the detailed description includes specific details. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0023] Figure 1AIllustrates a layout view of an exemplary integrated circuit (IC) inverter unit 100 in accordance with one aspect of the present disclosure. In this example, the inverter unit 100 is a unit cell; that is, it includes a single input pin "a" and a single output pin "z". The inverter unit 100 is located between a pair of horizontal power metal rails VDD 102 and VSS 104. As used herein, "horizontal" means in the unit row direction, and "vertical" means in the unit column direction.

[0024] The inverter unit 100 has a width of two (2) contact polycrystalline silicon pitches (CPP). That is, the inverter unit 100 includes upper left and lower left termination polycrystalline silicon structures 106a and 106b that extend in the column or vertical direction and that can be coupled to the power rails VDD 102 and VSS 104, respectively, to provide electrical isolation of the unit from its left side. Similarly, the inverter unit 100 includes upper right and lower right termination polycrystalline silicon structures 110a and 110b that extend in the column or vertical direction and that can also be coupled to the power rails VDD 102 and VSS 104, respectively, to provide electrical isolation of the unit from its right side. Additionally, the inverter unit 100 includes an intermediate polycrystalline silicon structure 108 that extends in the column or vertical direction and that serves as the gate or input of the inverter unit 100 (which may be referred to herein as gate polycrystalline silicon). In the row or horizontal direction, the distance between adjacent polycrystalline silicon structures is one (1) CPP. Thus, as discussed, the inverter unit 100 has a width of 2CPP:1CPP between the polycrystalline silicon structures 106 and 108 and a width of 1CPP between the polycrystalline silicon structures 108 and 110.

[0025] The inverter unit 100 also includes an n+ diffusion region 112 (sometimes referred to as an oxide diffusion (OD) region) on which a p-channel metal oxide semiconductor field effect transistor (PMOS FET) is formed. The n+ diffusion region 112 extends in the row or horizontal direction. In this example, the region of the n+ diffusion region 112 to the right of the gate polycrystalline silicon 108 is the source of the PMOS FET, and the region of the n+ diffusion region 112 to the left of the gate polycrystalline silicon 108 is the drain of the PMOS FET. Similarly, the inverter unit 100 also includes a p+ diffusion region 114 on which an n-channel metal oxide semiconductor field effect transistor (NMOS FET) is formed. The p+ diffusion region 114 extends in the row or horizontal direction and is spaced apart from the n+ diffusion region 112 in the vertical or column direction. The region of the p+ diffusion region 114 to the right of the gate polycrystalline silicon 108 is the source of the NMOS FET, and the region of the p+ diffusion region 114 to the left of the gate polycrystalline silicon 108 is the drain of the NMOS FET. Since the inverter unit 100 includes both a PMOS and an NMOS FET, the inverter unit 100 can be referred to as a complementary metal oxide semiconductor (CMOS) inverter unit.

[0026] As schematically illustrated, the source of the PMOS FET is electrically coupled to the VDD power rail 102. Similarly, the source of the NMOS FET is electrically coupled to the VSS power rail 104. A via contact representing the input "a" (represented herein as a square with two diagonal cross-lines) is shown to be located above the gate polysilicon 108 and coupled to the gate polysilicon. Also, another via contact representing the output "z" is shown to be located above the electrically coupled drains of the PMOS and NMOS FETs (but for simplicity, the actual metal layer that electrically couples the drains of the PMOS FET and the NMOS FET is not shown). For illustrative purposes, the inverter unit 100 includes a set of M0 metal layer traces 116 that are elongated in a row or horizontal direction and equally spaced apart from each other in a column or vertical direction. The height of the inverter unit 100 may indicate the number of stacked M0 metal layer traces 116 (e.g., five (5)). One or more of the set of M0 metal layer traces 116 may provide intra-cell interconnects for the inverter unit 100.

[0027] Figure 1B A layout view of a row of integrated circuit (IC) units 130 according to another aspect of the present disclosure is illustrated. For descriptive purposes, the row of IC units 130 includes two adjacent units 100 and 120. However, it should be understood that a row of IC units may include multiple adjacent or neighboring units. Thus, in this example, the row of IC units 130 includes the inverter unit 100 as previously discussed and another inverter unit 120 adjacent to the inverter unit 100.

[0028] As depicted, the two inverter units 100 and 120 share: the VDD and VSS power rails 102 and 104 (which may be metal layers located above and below the row of units 130 and extending continuously across the row of units); the n+ diffusion regions 112 (also extending continuously across the row of units 130); the p+ diffusion regions 114 (also extending continuously across the row of units 130). The two inverter units 100 and 120 also share upper and lower termination polysilicon structures 110a / 110b to electrically isolate the units from each other.

[0029] The inverter unit 120 further includes a gate polysilicon 122 and additional upper and lower termination polysilicon structures 124a and 124b. The termination polysilicon structures 124a and 124b may be respectively coupled to the power rails VDD 102 and VSS 104 to electrically isolate the inverter unit 120 from its right side. The inverter unit 120 further includes a PMOS FET, which includes a source formed above the n+ diffusion region 112 to the left of the gate polysilicon 122 and a drain formed above the n+ diffusion region 112 to the right of the gate polysilicon 122. Similarly, the inverter unit 120 further includes an NMOS FET, which includes a source formed above the p+ diffusion region 114 to the left of the gate polysilicon 122 and a drain formed above the p+ diffusion region 114 to the right of the gate polysilicon 122.

[0030] As schematically illustrated, the source of the PMOS FET of the inverter unit 120 is also electrically coupled to the VDD power rail 102. Similarly, the source of the NMOS FET of the inverter unit 120 is also electrically coupled to the VSS power rail 104. The via contact representing the input “a2” is shown to be located above the gate polysilicon 122 and coupled to the gate polysilicon (note that the via contact of the gate polysilicon of the inverter unit 100 is relabeled as “a1” in Figure 1B ). Moreover, another via contact representing the output “z2” is shown to be located above the electrically coupled drains of the PMOS and NMOS FETs (but the actual metal layer electrically coupling the drains of the PMOS FET and the NMOS FET is not shown for simplicity) (it should also be noted that the via contact of the drain of the inverter unit 100 is relabeled as “z1” in Figure 1B ). The inverter units 100 and 120 have the same height (e.g., a two (2)-fin height unit); and thus, for the intra-cell interconnects of the units 100 and 120, there are respectively the same number of horizontally aligned M0 metal layer traces 116 and 126 (e.g., five (5)).

[0031] Note that the cumulative width of two adjacent inverter units 100 and 120 is four (4) CPPs. That is, the first CPP between the termination polysilicon structures 106a / 106b and the gate polysilicon 108 of the inverter unit 100; the second CPP between the gate polysilicon 108 of the inverter unit 100 and the termination polysilicon structures 110a / 110b; the third CPP between the termination polysilicon structures 110a / 110b and the gate polysilicon 122 of the inverter unit 120; and the fourth CPP between the gate polysilicon 122 of the inverter unit 120 and the termination polysilicon structures 124a / 124b. As discussed below, a multi-gate IC unit providing the same function as two adjacent IC inverter units but having a reduced width of three (3) CPPs is also described herein.

[0032] Figure 1C Illustrates a layout view of an exemplary multi-gate integrated circuit (IC) inverter unit 160 according to another aspect of the present disclosure. The term multi-gate means that the unit has more than one (1) gate (e.g., two inverters). As described above, the multi-gate inverter unit 160 provides the same functionality as the two adjacent inverter units 100 and 120 previously discussed. For descriptive purposes, the same reference numerals are used for similar elements in the two inverter units 100 and 120 in the multi-gate inverter unit 160.

[0033] Compared to the two adjacent inverter units 100 and 120, the multi-gate inverter unit 160 combines two separate source regions in the two adjacent inverter units 100 and 120 into a common source region. For example, two PMOS FETs share a source above the n+ diffusion region 112, on the right and left sides of the gate polysilicons 108 and 122, respectively. The PMOS FETs include drains above the n+ diffusion region 112, on the left and right sides of the gate polysilicons 108 and 122, respectively. Similarly, two NMOS FETs share a source above the p+ diffusion region 114, on the right and left sides of the gate polysilicons 108 and 122, respectively. The NMOS FETs include drains above the p+ diffusion region 114, on the left and right sides of the gate polysilicons 108 and 122, respectively. Schematically illustrated, the common source of the PMOS FETs is coupled (electrically connected) to the VDD power rail 102, and the common source of the NMOS FETs is coupled (electrically connected) to the VSS power rail 104.

[0034] Because the PMOS FETs and NMOS FETs share the source terminals, the width of the multi-gate inverter unit 160 is three (3) CPP, whereas, in contrast, the width of the two adjacent inverter units 100 and 120 is four (4) CPP. This is because the two adjacent inverter units 100 and 120 have their own source regions. Thus, the multi-gate inverter unit 160 can be more efficient in terms of IC footprint compared to the two adjacent inverter units 100 and 120.

[0035] Figure 2A Illustrates a layout view of an exemplary row of integrated circuit (IC) units 200 according to another aspect of the present disclosure. A place and route (PnR) IC layout tool routes to the pins of the IC unit via a set of M1 metal traces. The pins of the IC unit are the inputs and outputs of the IC unit. For example, a single inverter unit 100 has a single input pin "a" and a single output pin "z". Similarly, the two adjacent inverter units 100 and 120 or the multi-gate inverter unit 160 include two input pins "a1" and "a2" and two output pins "z1" and "z2".

[0036] Similar to the polysilicon structures with CPP, the M1 metal traces also have an M1 pitch. For example, this row of IC units 200 includes four (4) polysilicon structures 205, 210, 215, and 220 that are equally spaced from each other by one (1) CPP. Similarly, this row of IC units 200 includes four (4) M1 traces 225, 230, 235, and 240 that are equally spaced from each other by one (1) M1 pitch. In certain technology nodes, there may be a specific CPP / M1 pitch ratio. For example, the CPP / M1 pitch ratio of this row of IC units 200 is 2 / 3. That is, for a width of 2*CPP, there are three M1 traces. Thus, in this example, this row of IC units 200 includes four (4) M1 traces 225, 230, 235, and 240 within four (4) polysilicon structures 205, 210, 215, and 220.

[0037] Figure 2B Illustrated is a layout view of a row of integrated circuit (IC) units 250 according to another example of another aspect of the present disclosure. Other technology nodes may have different CPP / M1 pitch ratios. For example, this row of IC units 250 includes four (4) polysilicon structures 255, 260, 265, and 270 that are equally spaced from each other by one (1) CPP. Similarly, this row of IC units 250 includes three (3) M1 traces 275, 280, and 285 that are equally spaced from each other by one (1) M1 pitch. Thus, the CPP / M1 pitch ratio of this row of IC units 250 is one (1); that is, there is a one-to-one correspondence between the polysilicon structures and the M1 traces. As further discussed herein, the lower CPP / M1 of this row of IC units 250 may pose problems / troubles for the implementation of multi-gate IC units.

[0038] Figure 3A Illustrated is a layout view of an example multi-gate integrated circuit (IC) NAND gate unit 300 according to another aspect of the present disclosure. As discussed in more detail herein, the multi-gate NAND gate unit 300 can be implemented in a technology node with a CPP / M1 pitch ratio of 2 / 3. The multi-gate NAND gate unit 300 includes a VDD power rail 302 that extends in the unit row or horizontal direction and a VSS power rail 304 that also extends in the unit row or horizontal direction, both spanning the width of the unit 300. The VDD and VSS power rails 302 and 304 are spaced apart in the unit column or vertical direction based on the height of the multi-gate NAND gate unit 300.

[0039] The multi-gate NAND gate cell 300 includes a width of five (5) CPPs and includes cell-terminating polysilicon structures 312a / 312b, gate polysilicon 314, gate polysilicon 316, gate polysilicon 332, gate polysilicon 334, and terminating polysilicon structures 336a / 336b, where each adjacent polysilicon structure is spaced apart by one (1) CPP. All polysilicon structures 312, 314, 316, 332, 334, and 336 extend in the cell column or vertical direction and span the height of the cell 300. Two gate polysilicons 314 and 316 belong to the first NAND gate 310 of the multi-gate NAND gate cell 300. The other two gate polysilicons 332 and 334 belong to the second NAND gate 330 of the multi-gate NAND gate cell 300. The upper and lower terminating polysilicon structures 312a and 312b, which can be coupled to the VDD and VSS power rails 302 and 304 respectively, provide electrical isolation for the multi-gate NAND gate cell 300 from the left side. Similarly, the upper and lower terminating polysilicon structures 336a / 336b, which can also be coupled to the VDD and VSS power rails 302 and 304 respectively, provide electrical isolation for the multi-gate NAND gate cell 300 from the right side.

[0040] The multi-gate NAND gate cell 300 includes an n+ diffusion region 306, and PMOS FETs are formed, extended, and stretched across the cell 300 in the cell row or horizontal direction above the n+ diffusion region. Similarly, the multi-gate NAND gate cell 300 includes a p+ diffusion region 308, and NMOS FETs are formed, extended, and stretched across the cell 300 in the cell row or horizontal direction above the p+ diffusion region. The n+ diffusion region 306 and the p+ diffusion region 308 are located between the VDD and VSS power rails 302 and 304 and are spaced apart from each other based on the height of the cell 300.

[0041] Since the CPP / M1 pitch ratio of the multi-gate NAND gate cell 300 is 2 / 3, there are seven (7) M1 metal traces 320, 322, 324, 326, 340, 342, and 344 that extend in the cell column or vertical direction and are spaced apart from each other by one (1) M1 pitch. As previously discussed, each M1 metal trace includes a pin (input or output) of the multi-gate NAND gate cell 300.

[0042] For example, M1 metal trace 320 includes a pin "z1" for the output of the first NAND gate 310; M1 metal trace 322 includes a pin "a1" for the first input of the first NAND gate 310; M1 metal trace 324 includes a pin "b1" for the second input of the first NAND gate 310; M1 metal trace 340 includes a pin "b2" for the second input of the second NAND gate 330; M1 metal trace 342 includes a pin "a2" for the first input of the second NAND gate 330; and M1 metal trace 344 includes a pin "z2" for the output of the second NAND gate 330. Note that since there are seven (7) M1 traces in the multi-gate NAND gate cell 300 and there are six (6) input / output pins, an additional M1 trace 326 may be reserved for the PnR tool for routing through the cell 300 and / or other purposes.

[0043] The dual-input NAND gate includes two parallel PMOS FETs coupled between the VDD power rail 302 and the output of the NAND gate, and two series NMOS FETs coupled between the output and the VSS power rail 304. Regarding the first NAND gate 310, the first PMOS FET includes a source formed above the n+ diffusion region 306 to the left of the gate polysilicon 314, the second PMOS FET includes a source formed above the n+ diffusion region 306 to the right of the gate polysilicon 316, and the first and second PMOS FETs share a drain between the gate polysilicons 314 and 316 above the n+ diffusion region 306. The first NMOS FET includes a drain formed above the p+ diffusion region 308 to the left of the gate polysilicon 314 and a source formed above the p+ diffusion region 308 to the right of the gate polysilicon 314. The second NMOS FET includes a drain (shared with the source of the first NMOS FET) formed above the p+ diffusion region 308 to the left of the gate polysilicon 316 and a source formed above the p+ diffusion region 308 to the right of the gate polysilicon 316.

[0044] The first NAND gate 310 includes a set of M0 metal traces 318 (intra-cell interconnects) that extend in the cell row or horizontal direction and are equally spaced from each other in the cell column or vertical direction, and electrically couple the M1 metal trace 322 including the input pin "a1" to the gate polysilicon 314 (represented as a via contact above the gate polysilicon 314), electrically couple the M1 metal trace 324 including the input pin "b1" to the gate polysilicon 316 (represented as a via contact above the gate polysilicon 316), and electrically couple the M1 metal trace 320 including the output pin "z1" to the drains of the first and second PMOS FETs and the first NMOS FET of the first NAND gate 310.

[0045] Regarding the second NAND gate 330, the first PMOS FET includes a source formed above the n+ diffusion region 306 to the right of the gate polysilicon 334, the second PMOS FET includes a source formed above the n+ diffusion region 306 to the left of the gate polysilicon 332, and the first and second PMOS FETs share a drain between the gate polysilicons 332 and 334 above the n+ diffusion region 306. The first NMOS FET includes a drain formed above the p+ diffusion region 308 to the right of the gate polysilicon 334 and a source formed above the p+ diffusion region 308 to the left of the gate polysilicon 334. The second NMOS FET includes a drain (shared with the source of the first NMOS FET) formed above the p+ diffusion region 308 to the right of the gate polysilicon 332 and a source formed above the p+ diffusion region 308 to the left of the gate polysilicon 332.

[0046] The second NAND gate 330 includes a set of M0 metal traces 338 (intra-cell interconnects) that extend in the cell row or horizontal direction and are equally spaced from each other in the cell column or vertical direction, electrically coupling the M1 metal trace 342 including the input pin "a2" to the gate polysilicon 334 (represented as a via contact above the gate polysilicon 334), electrically coupling the M1 metal trace 340 including the input pin "b2" to the gate polysilicon 332 (represented as a via contact above the gate polysilicon 332), and electrically coupling the M1 metal trace 344 including the output pin "z2" to the common drain of the first and second PMOS FETs and the first NMOS FET of the second NAND gate 330.

[0047] As illustrated, at this technology node with a CPP / M1 ratio of 2 / 3, a multi-gate NAND gate cell 300 can be implemented because there are an equal number or more M1 traces for the pins of the cell. For example, the multi-gate NAND gate cell 300 includes seven (7) M1 traces, which is more than the number of pins of the cell (six (6)). As further discussed herein, at other technology nodes with a CPP / M1 ratio greater than 2 / 3 (such as one (1)), the number of available M1 metal traces can be less than the number of pins of the cell. In this case, a multi-gate cell in the configuration of the cell 300 may not be achievable because there are not enough M1 metal traces to accommodate the pins of the cell.

[0048] Figure 3BIllustrated is a layout view of an exemplary multi-gate integrated circuit (IC) NAND gate cell 350 in accordance with another aspect of the present disclosure. As discussed in more detail herein, the multi-gate NAND gate cell 350 may be implemented in a technology node with a CPP / M1 pitch ratio of one (1). The multi-gate NAND gate cell 350 includes a VDD power rail 352 extending in the cell row or horizontal direction and a VSS power rail 354 also extending in the cell row or horizontal direction, both spanning the width of the cell 350. The VDD and VSS power rails 352 and 354 are spaced apart in the cell column or vertical direction based on the height of the multi-gate NAND gate cell 350.

[0049] The multi-gate NAND gate cell 350 includes a width of five (5) CPPs and includes cell termination polysilicon structures 362, gate polysilicon 364, gate polysilicon 366, gate polysilicon 382, gate polysilicon 384, and termination polysilicon structures 386, where each adjacent polysilicon structure is spaced apart by one (1) CPP. All of the polysilicon structures 362, 364, 366, 382, 384, and 386 extend in the cell column or vertical direction and span the height of the cell. Two of the gate polysilicons 364 and 366 belong to the first NAND gate 360 of the multi-gate NAND gate cell 350. The other two gate polysilicons 382 and 384 belong to the second NAND gate 380 of the multi-gate NAND gate cell 350. The termination polysilicon structure 362, which may be floating, provides electrical isolation for the multi-gate NAND gate cell 350 from the left side. Similarly, the termination polysilicon structure 386, which may also be floating, provides electrical isolation for the multi-gate NAND gate cell 350 from the right side.

[0050] The multi-gate NAND gate cell 350 includes an n+ diffusion region 356 over which PMOS FETs are formed, extended, and stretched across the cell 350 in the cell row or horizontal direction. Similarly, the multi-gate NAND gate cell 350 includes a p+ diffusion region 358 over which NMOS FETs are formed, extended, and stretched across the cell 350 in the cell row or horizontal direction. The n+ diffusion region 356 and the p+ diffusion region 358 are located between the VDD and VSS power rails 352 and 354 and are spaced apart from each other based on the height of the cell 350.

[0051] Since the CPP / M1 pitch ratio of the multi-gate NAND gate cell 350 is one (1), there are five (5) M1 metal traces 370, 372, 374, 390, and 392 that extend in the cell column or vertical direction and are spaced apart from each adjacent trace by one (1) M1 pitch. As previously discussed, each M1 metal trace includes a pin (input or output) of the multi-gate NAND gate cell 350. However, the multi-gate NAND gate cell 350 is problematic because there are only five (5) M1 metal traces, while the multi-gate NAND gate cell 350 requires six (6) pins. For illustrative purposes, the M1 metal trace 374 depicts a pin conflict by being labeled "b1 / b2". Thus, the multi-gate NAND gate cell 350 does not have enough M1 metal traces to accommodate the required pins.

[0052] For example, the M1 metal trace 370 includes the pin "z1" for the output of the first NAND gate 360; the M1 metal trace 372 includes the pin "a1" for the first input of the first NAND gate 360; the M1 metal trace 390 includes the pin "a2" for the first input of the second NAND gate 380; and the M1 metal trace 392 includes the pin "z2" for the output of the second NAND gate 330. However, there are still two additional pins for the input "b1" of the first NAND gate 360 and the input "b2" of the second NAND gate 380, but there is only one remaining M1 metal trace 374. Thus, another multi-gate cell design and layout method is needed to implement a multi-gate NAND gate cell with a CPP / M1 pitch ratio of one (1).

[0053] Figure 4 A layout view of another exemplary multi-gate integrated circuit (IC) NAND gate cell 400 according to another aspect of the present disclosure is illustrated. As discussed in more detail herein, the multi-gate NAND gate cell 400 can be implemented in a technology node with a CPP / M1 pitch ratio of one (1). The multi-gate NAND gate cell 400 includes a VDD power rail 402 that extends in the cell row or horizontal direction and a VSS power rail 404 that also extends in the cell row or horizontal direction, both spanning the width of the cell 400. The VDD and VSS power rails 402 and 404 are spaced apart in the cell column or vertical direction based on the height of the multi-gate NAND gate cell 400.

[0054] The multi-gate NAND gate cell 400 includes a width of five (5) CPPs and includes a cell-terminating polysilicon structure 412, gate polysilicon 414, gate polysilicon 416, gate polysilicon 432, gate polysilicon 434, and a terminating polysilicon structure 436, where each adjacent polysilicon structure is spaced apart by one (1) CPP. All the polysilicon structures 412, 414, 416, 432, 434, and 436 extend in the cell column or vertical direction and span the height of the cell. Two gate polysilicons 414 and 416 belong to the first NAND gate 410 of the multi-gate NAND gate cell 400. The other two gate polysilicons 432 and 434 belong to the second NAND gate 430 of the multi-gate NAND gate cell 400. The terminating polysilicon structure 412, which can be floating, provides electrical isolation for the multi-gate NAND gate cell 400 from the left side. Similarly, the terminating polysilicon structure 436, which can also be floating, provides electrical isolation for the multi-gate NAND gate cell 400 from the right side.

[0055] The multi-gate NAND gate cell 400 includes an n+ diffusion region 406 above which PMOS FETs are formed, extended, and stretched across the cell 400 in the cell row or horizontal direction. Similarly, the multi-gate NAND gate cell 400 includes a p+ diffusion region 408 above which NMOS FETs are formed, extended, and stretched across the cell 400 in the cell row or horizontal direction. The n+ diffusion region 406 and the p+ diffusion region 408 are located between the VDD and VSS power rails 402 and 404 and are spaced apart from each other based on the height of the cell 400.

[0056] Since the CPP / M1 pitch ratio of the multi-gate NAND gate cell 400 is one (1), there are five (5) M1 metal traces 420, 422, dual-pin column stacks or vertical stack M1 metal traces 424-1 and 424-2, 440, and 442 that are spaced apart from each adjacent trace by one (1) M1 pitch. As previously discussed, each M1 metal trace includes a pin (input or output) of the multi-gate NAND gate cell 400. However, compared to the multi-gate NAND gate cell 350, in addition to the other M1 metal traces 420, 422, 440, and 442, the dual-pin column stack or vertical stack metal traces 424-1 and 424-2 also accommodate six (6) pins of the multi-gate NAND gate cell 400 together.

[0057] For example, M1 metal trace 420 includes a pin "z1" for the output of the first NAND gate 410; M1 metal trace 422 includes a pin "a1" for the first input of the first NAND gate 410; the first column of stacked or vertically stacked M1 traces 424-1 includes a pin "b1" for the second input of the first NAND gate 410; the second column of stacked or vertically stacked M1 traces 424-2 includes a pin "b2" for the second input of the second NAND gate 430; M1 metal trace 440 includes a pin "a2" for the first input of the second NAND gate 430; and M1 metal trace 442 includes a pin "z2" for the output of the second NAND gate 430.

[0058] As previously discussed, a dual-input NAND gate includes two parallel PMOS FETs coupled between the VDD power rail 402 and the output of the NAND gate, and two series NMOS FETs coupled in series between the output and the VSS power rail 404. With respect to the first NAND gate 410, the first PMOS FET includes a source formed above the n+ diffusion region 406 to the left of the gate polysilicon 414, the second PMOS FET includes a source formed above the n+ diffusion region 406 to the right of the gate polysilicon 416, and the first and second PMOS FETs share a drain between the gate polysilicons 414 and 416 above the n+ diffusion region 406. The first NAND gate 410 includes a set of M0 metal traces 450, 452, and 454 / 456 (intra-cell interconnects) that extend in the cell row or horizontal direction and are equally spaced from each other in the cell column or vertical direction (although one trace between traces 450 and 452 is not shown or may not be used). M0 trace 450 electrically couples the common drain of the PMOS FETs to the M1 metal trace 420 including the output pin "z1"; M0 trace 452 electrically couples the gate polysilicon 414 (represented as a via contact above the gate polysilicon 414) to the M1 metal trace 422 including the input pin "a1"; M0 trace 454 electrically couples the drain of the first NMOS FET to the M1 trace 420; and M0 trace 456 electrically couples the gate polysilicon 416 (represented as a via contact above the gate polysilicon 416) to the first column of stacked or vertically stacked M1 metal traces 424-1 including the input pin "b1".

[0059] Regarding the second NAND gate 430, the first PMOS FET includes a source formed above the n+ diffusion region 406 to the right of the gate polysilicon 434, the second PMOS FET includes a source formed above the n+ diffusion region 406 to the left of the gate polysilicon 432, and the first and second PMOS FETs share a drain between the gate polysilicons 432 and 434 above the n+ diffusion region 406. The second NAND gate 430 includes a set of M0 metal traces 460, 462, 464, and 466 (intra-cell interconnects) that extend in the cell row or horizontal direction and are equally spaced from each other in the cell column or vertical direction. The M0 trace 460 electrically couples the gate polysilicon 432 (represented as a via contact above the gate polysilicon 432) to the second column stack or vertical stack of M1 metal traces 424-2 including the input pin "b2"; the M0 trace 462 electrically couples the gate polysilicon 434 (represented as a via contact above the gate polysilicon 434) to the M1 metal trace 440 including the input pin "a2"; the M0 trace 464 electrically couples the drain of the first NMOS FET to the M1 trace 442; and the M0 trace 466 electrically couples the common drain of the PMOS FETs to the M1 trace 442 including the output pin "z2".

[0060] Thus, the column stack or vertical stack of M1 metal traces 424-1 and 424-2 (located between the gate polysilicons 416 and 432) provide additional pins to meet the pin count requirements of the multi-gate cell 400. Additionally, the column stack or vertical stack of M1 metal traces 424-1 and 424-2 including the pins "b1" and "b2" are respectively located above the common source regions shared by the two NAND gates 410 and 430 (e.g., generally logic gates). Further, the input pins "b1" and "b2" of the column stack or vertical stack of M1 metal traces 424-1 and 424-2 are respectively located above the p+ and n+ diffusion regions 408 and 406 (note that the other input pins "a1" and "a2" are located in the cell region between the diffusion regions 406 and 408). Moreover, the M0 metal traces 456 and 460 for electrically coupling the input pins "b1" and "b2" to the corresponding gate polysilicons 416 and 432 can be respectively closest to the corresponding VSS and VDD power rails 404 and 402. Although the NAND gates 410 and 430 are used herein to illustrate the column stack or vertical stack of multi-pin M1 metal trace layout concept, it should be understood that the multi-gate cell 400 can be implemented using any two (identical or different) logic gates sharing a common source region coupled to the VDD and VSS power rails.

[0061] Figure 5Illustrated is a layout view of another exemplary multi-gate integrated circuit (IC) dual-input NAND gate cell 500 according to another aspect of the present disclosure. The multi-gate IC NAND gate cell 500 is a variant of the multi-gate IC NAND gate cell 400 and includes multiple identical / similar elements as indicated by the same reference numerals, but the most significant bit in the multi-gate IC NAND gate cell 500 is "5" instead of "4" in the multi-gate IC NAND gate cell 400.

[0062] The difference between the multi-gate IC NAND gate cells 400 and 500 is that the height of the multi-gate IC NAND gate cell 500 is greater than the height of the multi-gate IC NAND gate cell 400. For example, the multi-gate NAND gate cell 400 can be a single fin height cell, while the multi-gate NAND gate cell 500 can be a double fin height cell. In this example, the greater height of the multi-gate NAND gate cell 500 accommodates five (5) M0 metal traces compared to four (4) M0 metal traces in the multi-gate NAND gate cell 400. However, the attributes discussed above for the multi-gate NAND gate 500 apply to the multi-gate NAND gate 400.

[0063] That is, the multi-gate IC NAND gate 500 includes column-stacked or vertically-stacked dual-pin M1 metal traces 524-1 and 524-2 (located between gate polysilicons 516 and 532), which provide additional pins to meet the required pins of the multi-gate cell 500. Additionally, the column-stacked or vertically-stacked M1 metal traces 524-1 and 524-2 including pins "b1" and "b2" are respectively located above a common source region shared by two NAND gates 510 and 530 (e.g., generally logic gates). Further, the input pins "b1" and "b2" of the column-stacked or vertically-stacked M1 metal traces 524-1 and 524-2 are respectively located above p+ and n+ diffusion regions 508 and 506 (while the other input pins "a1" and "a2" are located in the cell region between diffusion regions 406 and 408). Moreover, the M0 metal traces 556 and 560 for electrically coupling the input pins "b1" and "b2" to the corresponding gate polysilicons 516 and 532 can be respectively closest to the corresponding VSS and VDD power rails 504 and 502. Although NAND gates 510 and 530 are used herein to illustrate the column-stacked or vertically-stacked multi-pin M1 metal trace layout concept, it should be understood that any two (identical or different) logic gates sharing a common source region coupled to VDD and VSS power rails can be used to implement the multi-gate cell 500.

[0064] Figure 6Illustrates a layout view of another exemplary multi-gate integrated circuit (IC) inverter unit 600 in accordance with another aspect of the present disclosure. As discussed in more detail herein, the multi-gate inverter unit 600 may be implemented in a technology node with a CPP / M1 pitch ratio of one (1). The multi-gate inverter unit 600 includes a VDD power rail 602 that extends in a unit row or horizontal direction and a VSS power rail 604 that extends in a unit row or horizontal direction, both spanning the width of the unit 600. The VDD and VSS power rails 602 and 604 are spaced apart in a unit column or vertical direction based on the height of the multi-gate inverter unit 600.

[0065] The multi-gate inverter unit 600 includes a width of three (3) CPPs and includes unit-terminated polysilicon structures 612, gate polysilicon 614, gate polysilicon 632, and terminated polysilicon structures 634, where each adjacent polysilicon structure is spaced apart by one (1) CPP. All polysilicon structures 612, 614, 632, and 634 extend in a unit column or vertical direction and span the height of the unit 600. The gate polysilicon 614 belongs to the first inverter 610 of the multi-gate inverter unit 600. Another gate polysilicon 632 belongs to the second inverter unit 630 of the multi-gate inverter unit 600. The terminating polysilicon structure 612, which can be floating, provides electrical isolation for the multi-gate inverter unit 600 from the left side. Similarly, the terminating polysilicon structure 634, which can also be floating, provides electrical isolation for the multi-gate inverter unit 600 from the right side.

[0066] The multi-gate inverter unit 600 includes an n+ diffusion region 606 above which PMOS FETs are formed, extended, and stretched across the unit 600 in a unit row or horizontal direction. Similarly, the multi-gate inverter unit 600 includes a p+ diffusion region 608 above which NMOS FETs are formed, extended, and stretched across the unit 600 in a unit row or horizontal direction. The n+ diffusion region 606 and the p+ diffusion region 608 are located between the VDD and VSS power rails 602 and 604 and are spaced apart from each other based on the height of the unit 600.

[0067] Since the CPP / M1 pitch ratio of the multi-gate inverter unit 600 is one (1), there are three (3) M1 metal traces spaced apart from each adjacent trace by one (1) M1 pitch: M1 trace 620, column stack or vertical stack dual-pin M1 metal traces 622-1 and 622-2, and M1 trace 640. As previously discussed, each M1 metal trace includes a pin (input or output) of the multi-gate inverter unit 600. In addition to the other M1 metal traces 620 and 640, the column stack or vertical stack dual-pin M1 metal traces 622-1 and 622-2 also together accommodate four (4) pins of the multi-gate inverter unit 600.

[0068] For example, the M1 metal trace 620 includes a pin "z1" for the output of the first inverter 610; the first column stack or vertical stack of M1 traces 622-1 includes a pin "a1" for the input of the first inverter 610; the second column stack or vertical stack of M1 traces 622-2 includes a pin "a2" for the input of the second inverter 630; and the M1 metal trace 640 includes a pin "z2" for the output of the second inverter 630.

[0069] Regarding the first inverter 610, the PMOS FET includes a source above the n+ diffusion region 606 on the right side of the gate polysilicon 614 and a drain above the n+ diffusion region 606 on the left side of the gate polysilicon 614. The NMOS FET of the first inverter 610 includes a source above the p+ diffusion region 608 on the right side of the gate polysilicon 614 and a drain above the p+ diffusion region 608 on the left side of the gate polysilicon 614. Similarly, regarding the second inverter 630, the PMOS FET includes a source above the n+ diffusion region 606 on the left side of the gate polysilicon 632 and a drain above the n+ diffusion region 606 on the right side of the gate polysilicon 632. The NMOS FET of the second inverter 630 includes a source above the p+ diffusion region 608 on the left side of the gate polysilicon 632 and a drain above the p+ diffusion region 608 on the right side of the gate polysilicon 632.

[0070] Thus, the column stack or vertical stack of dual-pin M1 metal traces 622-1 and 622-2 (located between the gate polysilicons 614 and 632) provides additional pins to meet the pin count requirements of the multi-gate inverter cell 600. Additionally, the column stack or vertical stack of dual-pin M1 metal traces 622-1 and 622-2 including pins "a1" and "a2" are respectively located above a common source region shared by two inverters 610 and 630 (e.g., typically logic gates). Further, the input pins "a1" and "a2" of the column stack or vertical stack of M1 metal traces 622-1 and 622-2 are respectively located above the p+ and n+ diffusion regions 608 and 606. Moreover, the M0 metal traces 624 and 626 that electrically couple the input pins "a1" and "a2" to the corresponding gate polysilicons 614 and 632 can be respectively closest to the corresponding VSS and VDD power rails 604 and 602. Although inverters 610 and 630 are used herein to illustrate the column stack or vertical stack of multi-pin M1 metal trace layout concept, it should be understood that the multi-gate cell 600 can be implemented using any two (identical or different) logic gates that share a common source region coupled to the VDD and VSS power rails.

[0071] Figure 7A flowchart illustrating an example method 700 of processing signals according to another aspect of the present disclosure is shown. Method 700 includes generating a first input logic signal (block 710). The first input logic signal may be generated by an IC cell of an integrated circuit (IC). Method 700 also includes generating a second input logic signal (block 720). Similarly, the second input logic signal may be generated by another IC cell of the IC.

[0072] Additionally, method 700 includes applying the first logic signal and the second logic signal to a column stack or vertically stack the first and second pins of a multi-gate IC cell (block 730). As previously discussed, the column stack or vertically stack the first and second pins of the multi-gate IC cell may be located in a VDD and VSS coupled common source region shared by the logic gates of the multi-gate IC cell. Thus, applying the first logic signal and the second logic signal to the multi-gate IC cell may include routing the signals to pins "b1" and "b2" of the multi-gate NAND gate cell 400 or 500 or pins "a1" and "a2" of the multi-gate inverter cell 600, respectively.

[0073] Method 700 includes receiving a first output logic signal from the multi-gate cell, where the first output logic signal is based on the first input logic signal (block 740). For example, an IC cell of the IC may receive the first output logic signal generated at pin "z1" of the multi-gate NAND gate cell 400 or 500 or the multi-gate inverter cell 600. Additionally, method 700 includes receiving a second output logic signal from the multi-gate cell, where the second output logic signal is based on the second input logic signal (block 750). For example, an IC cell of the IC may receive the second output logic signal generated at pin "z2" of the multi-gate NAND gate cell 400 or 500 or the multi-gate inverter cell 600.

[0074] Figure 8 A block diagram illustrating an example wireless communication device 800 according to another aspect of the present disclosure is shown. The wireless communication device 800 may be a smart phone, a desktop computer, a laptop computer, a tablet device, an Internet of Things (IoT), a wearable wireless device (e.g., a wireless watch), and other types of wireless devices.

[0075] In particular, wireless communication device 800 includes an integrated circuit (IC) 810 that can be implemented as a system-on-chip (SOC) 810. SOC 810 includes one or more signal processing cores 820, which can be implemented using a two-dimensional array of IC cells 830. One or more of the IC cells 830 can be implemented as multi-gate IC cells having columns or vertically stacked pins in a VDD / VSS coupled common source region, as illustrated in the multi-gate IC cells 400, 500, and 600 discussed previously. The one or more signal processing cores 820 can be configured to generate transmitted baseband (BB) signals and process received baseband (BB) signals.

[0076] Wireless communication device 800 may further include a transceiver 850 and at least one antenna 860 (e.g., an antenna array). Transceiver 850 is coupled to one or more signal processing cores 820 to receive transmitted BB signals therefrom and provide received BB signals thereto. Transceiver 850 is configured to convert the transmitted BB signal into a transmitted radio frequency (RF) signal and convert the received RF signal into a received BB signal. Transceiver 850 is coupled to at least one antenna 860 to provide the transmitted RF signal thereto for electromagnetic radiation into the wireless medium for wireless transmission, and to receive the received RF signal electromagnetically picked up by at least one antenna 860 from the wireless medium.

[0077] An overview of aspects of the present disclosure is provided below:

[0078] Aspect 1: An integrated circuit (IC) cell, the integrated circuit (IC) cell comprising: a first logic gate, the first logic gate including a first polysilicon structure and a first pin; a second logic gate, the second logic gate including a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a cell row direction; and a source region, the source region being common to the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are located on a first metal trace directly above the common source region.

[0079] Aspect 2: The IC cell according to aspect 1, wherein the first metal trace is located on an M1 metal layer.

[0080] Aspect 3: The IC cell according to aspect 1 or 2, wherein the first pin and the second pin each include an input pin.

[0081] Aspect 4: The IC unit according to any one of Aspects 1 to 3, wherein the IC unit further comprises: a first power rail; a first diffusion region electrically connected to the first power rail at the common source region; a second power rail; and a second diffusion region electrically connected to the second power rail at the common source region.

[0082] Aspect 5: The IC unit according to Aspect 4, wherein the first pin is located directly above the first diffusion region, and the second pin is located directly above the second diffusion region.

[0083] Aspect 6: The IC unit according to Aspect 5, wherein the IC unit further comprises a first intra-cell interconnector and a second intra-cell interconnector that electrically couple the first pin and the second pin to the first polysilicon structure and the second polysilicon structure, respectively.

[0084] Aspect 7: The IC unit according to Aspect 6, wherein the first intra-cell interconnector and the second intra-cell interconnector are located directly above the first diffusion region and the second diffusion region, respectively.

[0085] Aspect 8: The IC unit according to Aspect 6 or 7, wherein the first intra-cell interconnector and the second intra-cell interconnector are located on the M0 metal layer.

[0086] Aspect 9: The IC unit according to any one of Aspects 6 to 8, wherein the IC unit further comprises a set of intra-cell interconnectors including the first intra-cell interconnector and the second intra-cell interconnector, wherein each intra-cell interconnector extends in the cell row direction and is spaced apart from each other in the cell column direction, and wherein the first intra-cell interconnector and the second intra-cell interconnector in the set of intra-cell interconnectors are located closest to the first power rail and the second power rail, respectively.

[0087] Aspect 10: The IC unit according to any one of Aspects 1 to 9, wherein the first logic gate comprises: a first p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET), wherein the first polysilicon structure serves as the first gate of the first PMOS FET, and wherein the first PMOS FET comprises a first source located above an n+ diffusion region within the common source region; and a first n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET), wherein the first polysilicon structure serves as the first gate of the first NMOS FET, and wherein the first NMOS FET comprises a first source located above a p+ diffusion region within the common source region.

[0088] Aspect 11: The IC unit according to aspect 10, wherein the second logic gate includes: a second PMOS FET, wherein the second gate polysilicon gate structure serves as the second gate of the second PMOS FET, and wherein the second PMOS FET shares the first source with the first PMOS FET; and a second NMOS FET, wherein the second gate polysilicon gate structure serves as the second gate of the second NMOS FET, and wherein the second NMOS FET shares the first source with the first NMOS FET.

[0089] Aspect 12: The IC unit according to aspect 11, the IC unit further includes: a third polysilicon structure, the third polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in the unit row direction; and a fourth polysilicon structure, the fourth polysilicon structure is spaced apart from and adjacent to the second polysilicon structure in the unit row direction.

[0090] Aspect 13: The IC unit according to aspect 12, wherein: the first PMOS FET includes a first drain above the n+ diffusion region between the first polysilicon structure and the third polysilicon structure; the first NMOS FET includes a first drain above the p+ diffusion region between the first polysilicon structure and the third polysilicon structure; the second PMOS FET includes a second drain above the n+ diffusion region between the second polysilicon structure and the fourth polysilicon structure; and the second NMOS FET includes a second drain above the p+ diffusion region between the second polysilicon structure and the fourth polysilicon structure.

[0091] Aspect 14: The IC unit according to aspect 13, wherein: the first logic gate includes a third pin on a second metal trace between the first gate polysilicon structure and the first polysilicon structure; and the second logic gate includes a fourth pin on a third metal trace between the second gate polysilicon structure and the second polysilicon structure.

[0092] Aspect 15: The IC unit according to claim 14, wherein each pair of adjacent first polysilicon structure, second polysilicon structure, third polysilicon structure and fourth polysilicon structure are separated by a first pitch, wherein each pair of adjacent first metal trace, second metal trace and third metal trace are separated by a second pitch, and wherein the ratio of the first pitch to the second pitch is one (1).

[0093] Aspect 16: The IC unit according to aspect 14, wherein the third pin and the fourth pin respectively include output pins.

[0094] Aspect 17: The IC unit according to aspect 16, wherein the first polysilicon gate structure and the second polysilicon gate structure include unit termination polysilicon gate structures.

[0095] Aspect 18: The IC unit according to aspect 14, wherein: the third pin is electrically coupled to the respective first drains of the first PMOSFET and the first NMOS FET; and the fourth pin is electrically coupled to the respective second drains of the second PMOSFET and the second NMOS FET.

[0096] Aspect 19: The IC unit according to aspect 14, wherein the third pin and the fourth pin are located between the n+ diffusion region and the p+ diffusion region.

[0097] Aspect 20: The IC unit according to aspect 20, wherein the third pin and the fourth pin each include input pins.

[0098] Aspect 21: The IC unit according to aspect 14, the IC unit further comprising: a first intra-unit interconnector that electrically couples the third pin to the third polysilicon structure; and a second intra-unit interconnector that electrically couples the fourth pin to the fourth polysilicon structure.

[0099] Aspect 22: The IC unit according to aspect 21, wherein the first intra-unit interconnector and the second intra-unit interconnector are located on the M0 metal layer.

[0100] Aspect 23: The IC unit according to aspect 20, wherein the first logic gate includes: a third PMOS FET, wherein the third polysilicon structure serves as the third gate of the third PMOS FET, and wherein the third PMOS FET includes a third drain coupled to the first drain of the first PMOS FET; and a third NMOS FET, wherein the third polysilicon structure serves as the third gate of the third NMOS FET, and wherein the third NMOS FET includes a third source coupled to the first drain of the first NMOS FET.

[0101] Aspect 24: The IC unit according to claim 23, wherein the second logic gate includes: a fourth PMOSFET, wherein the fourth polysilicon structure serves as the fourth gate of the fourth PMOSFET, and wherein the fourth PMOSFET includes a fourth drain coupled to the second drain of the second PMOSFET; and a fourth NMOSFET, wherein the fourth polysilicon structure serves as the fourth gate of the fourth NMOSFET, and wherein the fourth NMOSFET includes a fourth source coupled to the second drain of the second NMOSFET.

[0102] Aspect 25: The IC unit according to aspect 14, the IC unit further includes: a fifth polysilicon structure, the fifth polysilicon structure being spaced apart from and adjacent to the third polysilicon structure in the unit row direction; and a sixth polysilicon structure, the sixth polysilicon structure being spaced apart from and adjacent to the fourth polysilicon structure in the unit row direction.

[0103] Aspect 26: The IC unit according to aspect 25, wherein: the first logic gate includes a fifth pin on a fourth metal trace located between the third polysilicon structure and the fifth polysilicon structure; and the second logic gate includes a sixth pin on a fifth metal trace located between the fourth polysilicon structure and the sixth polysilicon structure.

[0104] Aspect 27: The IC unit according to aspect 26, wherein the fifth pin and the sixth pin each include an output pin.

[0105] Aspect 28: The IC unit according to any one of aspects 25 to 27, wherein the fifth polysilicon structure and the sixth polysilicon structure are respectively unit termination polysilicon structures.

[0106] Aspect 29: A method, the method comprising: generating a first input logic signal; generating a second input logic signal; applying the first logic signal and the second logic signal to a first pin and a second pin of an integrated circuit (IC) unit, wherein the IC unit comprises: a first logic gate comprising a first polysilicon structure and the first pin; a second logic gate comprising a second polysilicon structure and the second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a unit row direction; and a source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are located on a first metal trace directly above the shared source region; receiving a first output logic signal from the IC unit, wherein the first output logic signal is based on the first input logic signal; and receiving a second output logic signal from the IC unit, wherein the second output logic signal is based on the second input logic signal.

[0107] Aspect 30: A wireless communication device, the wireless communication device comprising: at least one antenna; a transceiver coupled to the at least one antenna; and an integrated circuit (IC) coupled to the transceiver, wherein the IC comprises a set of one or more signal processing cores, the set of one or more signal processing cores comprising an IC unit, the IC unit comprising: a first logic gate comprising a first polysilicon structure and a first pin; a second logic gate comprising a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a unit row direction; and a source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are located on a first metal trace directly above the shared source region.

[0108] The foregoing description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An integrated circuit (IC) unit, the integrated circuit (IC) unit comprising: A first logic gate, the first logic gate including a first polysilicon structure and a first pin; A second logic gate, the second logic gate including a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart and adjacent to the first polysilicon structure in the unit row direction; And A source region, the source region being shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are located on a first metal trace directly above the shared source region.

2. The IC unit according to claim 1, wherein the first metal trace is located on the M1 metal layer.

3. The IC unit according to claim 1, wherein the first pin and the second pin each include an input pin.

4. The IC unit according to claim 1, the IC unit further comprising: A first power rail; A first diffusion region, the first diffusion region being electrically connected to the first power rail at the shared source region; A second power rail; And A second diffusion region, the second diffusion region being electrically connected to the second power rail at the shared source region.

5. The IC unit according to claim 4, wherein the first pin is located directly above the first diffusion region, and the second pin is located directly above the second diffusion region.

6. The IC unit according to claim 5, the IC unit further comprising a first intra-unit interconnect and a second intra-unit interconnect that electrically couple the first pin and the second pin to the first polysilicon structure and the second polysilicon structure, respectively.

7. The IC unit according to claim 6, wherein the first intra-unit interconnect and the second intra-unit interconnect are located directly above the first diffusion region and the second diffusion region, respectively.

8. The IC unit according to claim 6, wherein the first intra-unit interconnect and the second intra-unit interconnect are located on the M0 metal layer.

9. The IC unit according to claim 6, the IC unit further comprising a set of intra-unit interconnects, the set of intra-unit interconnects including the first intra-unit interconnect and the second intra-unit interconnect, wherein each intra-unit interconnect extends in the unit row direction and is spaced apart from each other in the unit column direction, and wherein the first intra-unit interconnect and the second intra-unit interconnect in the set of intra-unit interconnects are located closest to the first power rail and the second power rail, respectively.

10. The IC unit according to claim 1, wherein the first logic gate includes: A first p-channel metal oxide semiconductor field effect transistor (PMOS FET), wherein the first polysilicon structure serves as the first gate of the first PMOS FET, and wherein the first PMOS FET includes a first source located above an n+ diffusion region within the shared source region; And A first n-channel metal-oxide-semiconductor field-effect transistor (NMOS FET), wherein the first polysilicon structure serves as the first gate of the first NMOS FET, and wherein the first NMOS FET includes a first source located above a p+ diffusion region within the common source region.

11. The IC unit according to claim 10, wherein the second logic gate comprises: A second PMOS FET, wherein the second polysilicon structure serves as the second gate of the second PMOS FET, and wherein the second PMOS FET shares the first source with the first PMOS FET; and A second NMOS FET, wherein the second polysilicon structure serves as the second gate of the second NMOS FET, and wherein the second NMOS FET shares the first source with the first NMOS FET.

12. The IC unit according to claim 11, the IC unit further comprising: A third polysilicon structure, the third polysilicon structure being spaced apart from and adjacent to the first polysilicon structure in the unit row direction; and A fourth polysilicon structure, the fourth polysilicon structure being spaced apart from and adjacent to the second polysilicon structure in the unit row direction.

13. The IC unit according to claim 12, wherein: The first PMOS FET includes a first drain located above the n+ diffusion region between the first polysilicon structure and the third polysilicon structure; The first NMOS FET includes a first drain located above the p+ diffusion region between the first polysilicon structure and the third polysilicon structure; The second PMOS FET includes a second drain located above the n+ diffusion region between the second polysilicon structure and the fourth polysilicon structure; and The second NMOS FET includes a second drain located above the p+ diffusion region between the second polysilicon structure and the fourth polysilicon structure.

14. The IC unit according to claim 13, wherein: The first logic gate includes a third pin on a second metal trace between the first polysilicon structure and the third polysilicon structure; and The second logic gate includes a fourth pin on a third metal trace between the second polysilicon structure and the fourth polysilicon structure.

15. The IC unit according to claim 14, wherein each pair of adjacent first polysilicon structure, second polysilicon structure, third polysilicon structure, and fourth polysilicon structure are separated by a first pitch, wherein each pair of adjacent first metal trace, second metal trace, and third metal trace are separated by a second pitch, and wherein the ratio of the first pitch to the second pitch is one (1).

16. The IC unit according to claim 14, wherein the third pin and the fourth pin respectively include output pins.

17. The IC unit according to claim 16, wherein the first polysilicon gate structure and the second polysilicon gate structure include unit termination polysilicon gate structures.

18. The IC unit according to claim 14, wherein: the third pin is electrically coupled to the respective first drains of the first PMOS FET and the first NMOS FET; and the fourth pin is electrically coupled to the respective second drains of the second PMOS FET and the second NMOS FET.

19. The IC unit according to claim 14, wherein the third pin and the fourth pin are located between the n+ diffusion region and the p+ diffusion region.

20. The IC unit according to claim 14, wherein the third pin and the fourth pin respectively include input pins.

21. The IC unit according to claim 20, the IC unit further comprising: a first intra-unit interconnect that electrically couples the third pin to the third polysilicon structure; and a second intra-unit interconnect that electrically couples the fourth pin to the fourth polysilicon structure.

22. The IC unit according to claim 21, wherein the first intra-unit interconnect and the second intra-unit interconnect are located on the M0 metal layer.

23. The IC unit according to claim 20, wherein the first logic gate comprises: a third PMOS FET, wherein the third polysilicon structure serves as the third gate of the third PMOS FET, and wherein the third PMOS FET includes a third drain coupled to the first drain of the first PMOS FET; and a third NMOS FET, wherein the third polysilicon structure serves as the third gate of the third NMOS FET, and wherein the third NMOS FET includes a third source coupled to the first drain of the first NMOS FET.

24. The IC unit according to claim 23, wherein the second logic gate comprises: a fourth PMOS FET, wherein the fourth polysilicon structure serves as the fourth gate of the fourth PMOS FET, and wherein the fourth PMOS FET includes a fourth drain coupled to the second drain of the second PMOS FET; and a fourth NMOS FET, wherein the fourth polysilicon structure serves as the fourth gate of the fourth NMOS FET, and wherein the fourth NMOS FET includes a fourth source coupled to the second drain of the second NMOS FET.

25. The IC unit according to claim 14, the IC unit further comprising: a fifth polysilicon structure that is spaced apart from and adjacent to the third polysilicon structure in the unit row direction; and a sixth polysilicon structure that is spaced apart from and adjacent to the fourth polysilicon structure in the unit row direction.

26. The IC unit according to claim 25, wherein: The first logic gate includes a fifth pin on a fourth metal trace between the third polysilicon structure and the fifth polysilicon structure; and The second logic gate includes a sixth pin on a fifth metal trace between the fourth polysilicon structure and the sixth polysilicon structure.

27. The IC unit according to claim 26, wherein the fifth pin and the sixth pin each include an output pin.

28. The IC unit according to claim 25, wherein the fifth polysilicon structure and the sixth polysilicon structure are respectively unit termination polysilicon structures.

29. A method, the method comprising: Generating a first input logic signal; Generating a second input logic signal; Applying the first logic signal and the second logic signal to a first pin and a second pin of an integrated circuit (IC) unit, wherein the IC unit includes: A first logic gate including a first polysilicon structure and the first pin; A second logic gate including a second polysilicon structure and the second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a unit row direction; and A source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are on a first metal trace directly above the shared source region; Receiving a first output logic signal from the IC unit, wherein the first output logic signal is based on the first input logic signal; and Receiving a second output logic signal from the IC unit, wherein the second output logic signal is based on the second input logic signal.

30. A wireless communication device, the wireless communication device comprising: At least one antenna; A transceiver coupled to the at least one antenna; And An integrated circuit (IC) coupled to the transceiver, wherein the IC includes a set of one or more signal processing cores, the set of one or more signal processing cores including an IC unit, the IC unit including: A first logic gate including a first polysilicon structure and a first pin; A second logic gate including a second polysilicon structure and a second pin, wherein the second polysilicon structure is spaced apart from and adjacent to the first polysilicon structure in a unit row direction; and A source region shared by the first logic gate and the second logic gate, located between the first polysilicon structure and the second polysilicon structure, wherein the first pin and the second pin are on a first metal trace directly above the shared source region.

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