Hybrid quenching circuit and working method for realizing gated quenching and fast active quenching

Abstract

The present invention discloses a hybrid quenching circuit and operating method for implementing gated quenching and rapid active quenching, relating to the field of weak light detection technology. The circuit comprises a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network. The first high-speed comparator has a non-inverting input connected to the anode of an active photodiode (APD), an inverting input connected to an adjustable discrimination level and the anode of the APD, and an inverting output connected to its latch-enable inverting input. The non-inverting output is connected to the input of the quenching transistor, and the output of the quenching transistor is connected to the anode of the APD. The output of the high-speed operational amplifier is connected to the output of the quenching transistor. The inverting output and latch-enable inverting input of the first high-speed comparator are connected to the inverting input of the second high-speed comparator. The non-inverting input of the second high-speed comparator is connected to the adjustable discrimination level. The present invention is compatible with both gated and free-running operating modes, achieving minimal circuit complexity and dual-mode detection performance.

Description

Technical Field

[0001] The present invention relates to the technical field of weak light detection, in particular to a hybrid quenching circuit and a working method for realizing gated quenching and rapid active quenching. Background Art

[0002] Single-photon detectors (SPDs) are key components in fields such as quantum information, lidar, and biomedicine. They possess extremely high sensitivity and can capture and convert energy at the level of a single photon. Common SPDs include photomultiplier tubes (PMTs), superconducting nanowire photodiodes (SNSPDs), and semiconductor avalanche photodiode detectors (APDs). APDs are highly practical due to their low cooling requirements, fast response speed, compact size, and easy optical fiber coupling.

[0003] The principle of single-photon detection in an avalanche photodiode (APD) is as follows: The APD is reverse-biased at a voltage above its breakdown voltage. This operating voltage region is called the "Geiger region," meaning the APD operates in single-photon detection mode, also known as Geiger mode. Operating in Geiger mode, the APD achieves sufficiently high gain. When a single incident photon is detected, an avalanche current is generated within the APD and continues spontaneously. Prolonged avalanche activity can affect the device's lifespan and stability. Therefore, upon detection of the avalanche current, the bias voltage must be immediately reduced to below the breakdown voltage, either actively or passively, to quench the current. This peripheral circuitry is called a quenching circuit. Common quenching circuits are categorized as active and passive. Passive quenching utilizes a large resistor connected in series with the APD to quench the avalanche current, creating a voltage drop across the resistor. Active quenching utilizes a bias control circuit to actively reduce the voltage difference across the APD.

[0004] Single-photon detectors typically operate in two modes: free-running mode, in which the APD operates with a bias voltage above its breakdown voltage, allowing it to detect photons at all times except during dead time. Gate-controlled mode, in which an external gating signal is used to keep the APD bias voltage above its breakdown voltage only when the gate is open, halting detection when the gate is closed. Both free-running and gated modes require a quenching circuit for proper operation. However, when the gate width is sufficiently narrow, the gate signal itself can achieve avalanche quenching, resulting in this type of circuit being called a gated quenching circuit.

[0005] Different practical applications require significantly different detector operating modes. For systems with predictable photon arrival times, such as quantum communication systems, single-photon detectors typically operate in gated mode to achieve a high detection signal-to-noise ratio. For systems with random photon arrival times, such as lidar systems, single-photon detectors are typically required to operate in free-running or wide-gate mode, but these often result in severe post-pulse effects. Therefore, hybrid quenching circuits with both gated quenching and fast active quenching capabilities are of great practical significance for single-photon detectors, as they can be used in applications that combine free-running and gated requirements, such as free-space optical communications. Summary of the Invention

[0006] In order to overcome the above problems existing in the prior art, the present invention proposes a hybrid quenching circuit and a working method for realizing gated quenching and fast active quenching.

[0007] The technical solution adopted by the present invention to solve its technical problems is: a hybrid quenching circuit that realizes gated quenching and fast active quenching, including an APD, a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network, wherein the APD anode is connected to an adjustable bias voltage source, the non-inverting input of the first high-speed comparator is connected to the APD anode via an AC coupling capacitor, the inverting input of the first high-speed comparator is connected to an adjustable discrimination level, the inverting output of the first high-speed comparator is connected to the latch enable inverting input of the first high-speed comparator; the non-inverting output of the first high-speed comparator is connected to the input of the quenching transistor, the output of the quenching transistor is connected to the cathode of the APD; the APD cathode is connected to the inverting input of the first high-speed comparator via a balanced noise cancellation network, and the output circuit of the high-speed operational amplifier is connected to the output of the quenching transistor;

[0008] The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator are connected to the inverting input terminal of the second high-speed comparator; the non-inverting input terminal of the second high-speed comparator is connected to the adjustable discrimination level.

[0009] In the above-mentioned hybrid quenching circuit that implements gated quenching and fast active quenching, a T-type network is provided between the non-inverting output terminal of the first high-speed comparator and the input terminal of the quenching transistor. The T-type network includes a second resistor, a third resistor and a third capacitor. The third capacitor is used to accelerate the conduction of the quenching transistor.

[0010] In the above-mentioned hybrid quenching circuit for realizing gated quenching and fast active quenching, the balanced noise cancellation network includes a first resistor, a first capacitor, and a second capacitor.

[0011] In the hybrid quenching circuit for realizing gated quenching and fast active quenching, an AC coupling capacitor is provided between the APD anode and the non-inverting input terminal of the first high-speed comparator.

[0012] In the hybrid quenching circuit that realizes gated quenching and fast active quenching, the high-speed operational amplifier is controlled by an FPGA, and the FPGA has a built-in serializer / deserializer to generate a gating signal, which is amplified and output by the in-phase amplifier circuit composed of the high-speed operational amplifier U3.

[0013] The invention relates to a working method of a hybrid quenching circuit for realizing gated quenching and rapid active quenching. Based on the above hybrid quenching circuit for realizing gated quenching and rapid active quenching, in free-running or wide-gated mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, the first high-speed comparator is in a normal comparison state, and the quenching transistor is in an off state; when the APD detects a photon, the generated avalanche pulse is higher than the discrimination level of the inverting input terminal of the first high-speed comparator, the avalanche is identified, and the output level of the first high-speed comparator is inverted; the non-inverting output terminal of the first high-speed comparator is inverted, driving the quenching transistor. The output is reversed, the APD cathode voltage decreases, and the avalanche is quenched. At the same time, the inverting output of the first high-speed comparator latches the quenching state through the inverting input of the latch enable. After the avalanche is quenched, the high-speed operational amplifier controlled by the FPGA cuts off the bias of the quenching transistor to achieve the lowest power consumption. At the same time, the reset lock signal is pulled low, and the latch state of the first high-speed comparator is released through the latch enable non-inverting input, restoring its comparison function. After the set dead time, or when the gate open signal arrives, the FPGA controls the high-speed operational amplifier to restore the quenching transistor bias, at which point the APD resumes operation.

[0014] In the narrow gating mode, the reset lock signal remains normally low, so that the first high-speed comparator cannot enter the latched state; at the same time, the reset lock signal is pulled low through the T-type network so that the base potential of the quenching transistor is always low, and the quenching transistor cannot be turned on. After the first high-speed comparator identifies the avalanche, it no longer has a quenching effect. The quenching and recovery of the APD are only completed by the narrow gating signal itself; at the same time, the inverting output end of the first high-speed comparator is normally output to the inverting input end of the second high-speed comparator, and is buffered by the second high-speed comparator and input into the FPGA, so that the avalanches can be counted normally.

[0015] The present invention has the beneficial effect of flexibly utilizing the latch enable function of the comparator. By controlling the logic for resetting the latch signal through an FPGA and incorporating a T-network into the feedback loop between the comparator's non-inverting output and the latch enable non-inverting input, the hybrid quenching circuit is compatible with both gated and free-running modes of operation while simultaneously avoiding the effects of quenching and recovery of the quenching transistor on high-speed operation with narrow gated signals. Compared to existing technologies, this circuit achieves minimal circuit complexity and excellent dual-mode detection performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a circuit structure block diagram of the hybrid quenching circuit of the present invention. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] like Figure 1 As shown, this embodiment discloses a hybrid quenching circuit for a compatible gated and free-running dual-mode single-photon detector, which can realize gated quenching and fast active quenching, and specifically includes an APD D1, a first high-speed comparator U1, a second high-speed comparator U2, a quenching transistor Q1, a high-speed operational amplifier U3 and a C-RC balanced noise cancellation network, wherein the C-RC balanced noise cancellation network includes a first resistor R1, a first capacitor C1 and a second capacitor C2.

[0019] APD D1 anode is connected to the resistor R d Connected to the adjustable bias voltage source; APD D1 anode is connected to the APD D1 anode through the AC coupling capacitor C C Connected to the non-inverting input terminal of the first high-speed comparator U1; the inverting input terminal of the first high-speed comparator U1 is connected to the inverting input terminal of the first high-speed comparator U1 through the resistor R N Connected to the adjustable discrimination level; the inverting output terminal of the first high-speed comparator U1 is connected to the latch enable inverting input terminal of the first high-speed comparator U1;

[0020] The non-inverting output terminal of the first high-speed comparator U1 is connected to the input terminal of the quenching transistor Q1 through a T-type network, which includes a second resistor R2, a third resistor R3, and a third capacitor C3; the output terminal of the quenching transistor Q1 is connected to the cathode of the APD; the cathode of the APD is connected to the inverting input terminal of the first high-speed comparator U1 through a balanced noise cancellation network;

[0021] The FPGA's built-in serializer / deserializer (SerDes) generates a gating signal, which is amplified and output by the in-phase amplifier circuit formed by the high-speed operational amplifier U3. The output circuit of the high-speed operational amplifier U3 is connected to the output end of the quenching transistor Q1.

[0022] The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator U1 are connected to the inverting input terminal of the second high-speed comparator U2; the non-inverting input terminal of the second high-speed comparator U2 is connected to the adjustable discrimination level; the second high-speed comparator U2 is used to achieve conversion from single-ended to differential level signals with higher sensitivity.

[0023] Based on the above hybrid quenching circuit, this embodiment further discloses an operating method for the hybrid quenching circuit, specifically including: when the single-photon detector operates in free-running or wide-gating mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, and the first high-speed comparator U1 is in a normal comparison state. At this time, the quenching transistor Q1 is in an off state.

[0024] When a photon is detected, the avalanche pulse generated by APD D1 exceeds the discrimination level of the inverting input of the first high-speed comparator U1. Avalanche is detected, and the output level of the first high-speed comparator U1 reverses. The non-inverting output of the first high-speed comparator U1 also reverses, driving the output of the quenching transistor Q1 to reverse. The third capacitor C3 accelerates the conduction of the quenching transistor, reducing the APD cathode voltage and quenching the avalanche. After the avalanche is quenched, the quenching state holds for a period of time. The inverting output of the first high-speed comparator U1 latches the quenching state through the inverting input of the latch enable. After the avalanche is quenched, the high-speed operational amplifier U3, controlled by the FPGA, de-biases the quenching transistor Q1 to minimize power consumption. Simultaneously, the reset lock signal is pulled low, releasing the latch state of the first high-speed comparator U1 through the non-inverting input of the latch enable, restoring its comparator function. After the set dead time expires, or when the gate "on" signal arrives, the FPGA controls the high-speed operational amplifier U3 to restore the bias of the quenching transistor Q1, at which point the APD resumes operation.

[0025] In narrow gating mode, the reset lock signal remains permanently low, preventing the first high-speed comparator U1 from entering the latched state. Simultaneously, the reset lock signal is pulled low through the T-type network, keeping the base potential of the quenching transistor Q1 permanently low. This prevents the quenching transistor Q1 from conducting. After the first high-speed comparator U1 detects an avalanche, it no longer quenches the APD. The narrow gating signal itself completes the quenching and recovery of the APD. Meanwhile, the inverting output of the first high-speed comparator U1 is normally fed to the inverting input of the second high-speed comparator U2. This signal is then buffered by the second high-speed comparator U2 and fed into the FPGA, enabling avalanche counting.

[0026] The above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the present invention. Those skilled in the art may make various modifications or equivalent substitutions to the present invention within the spirit and scope of protection of the present invention, and such modifications or equivalent substitutions shall also be deemed to fall within the scope of protection of the present invention.

Claims

1. A hybrid quenching circuit that realizes gated quenching and fast active quenching, characterized in that: The device comprises an APD, a first high-speed comparator, a second high-speed comparator, a quenching transistor, a high-speed operational amplifier, and a balanced noise cancellation network, wherein the APD anode is connected to an adjustable bias voltage source, the non-inverting input of the first high-speed comparator is connected to the APD anode, the inverting input of the first high-speed comparator is connected to an adjustable discrimination level, the inverting output of the first high-speed comparator is connected to the latch enable inverting input of the first high-speed comparator; the non-inverting output of the first high-speed comparator is connected to the input of the quenching transistor, the output of the quenching transistor is connected to the cathode of the APD; the APD cathode is connected to the inverting input of the first high-speed comparator via a balanced noise cancellation network, and the output circuit of the high-speed operational amplifier is connected to the output of the quenching transistor; The inverting output terminal and the latch enable inverting input terminal of the first high-speed comparator are connected to the inverting input terminal of the second high-speed comparator; the non-inverting input terminal of the second high-speed comparator is connected to the adjustable discrimination level.

2. The hybrid quenching circuit for realizing gated quenching and fast active quenching according to claim 1, characterized in that: A T-type network is provided between the in-phase output terminal of the first high-speed comparator and the input terminal of the quenching transistor. The T-type network includes a second resistor, a third resistor and a third capacitor. The third capacitor is used to accelerate the conduction of the quenching transistor.

3. The hybrid quenching circuit for realizing gated quenching and fast active quenching according to claim 1, characterized in that: The balanced noise cancellation network includes a first resistor, a first capacitor, and a second capacitor.

4. The hybrid quenching circuit for realizing gated quenching and fast active quenching according to claim 1, characterized in that: An AC coupling capacitor is provided between the APD anode and the non-inverting input terminal of the first high-speed comparator.

5. The hybrid quenching circuit for realizing gated quenching and fast active quenching according to claim 1, characterized in that: The high-speed operational amplifier is controlled by an FPGA, and a built-in serializer / deserializer in the FPGA generates a gating signal, which is amplified by a common-mode amplifier circuit formed by a high-speed operational amplifier U3 and then output.

6. A method for implementing a hybrid quenching circuit for gated quenching and rapid active quenching, characterized in that: Based on the hybrid quenching circuit for realizing gated quenching and fast active quenching as described in any one of claims 1 to 5, in free-running or wide-gated mode, when there is no avalanche signal, the reset lock signal is in a high-impedance state, the first high-speed comparator is in a normal comparison state, and the quenching transistor is in an off state; when the APD detects a photon, the generated avalanche pulse is higher than the identification level of the inverting input terminal of the first high-speed comparator, the avalanche is identified, and the output level of the first high-speed comparator is inverted; the non-inverting output terminal of the first high-speed comparator is inverted, driving the quenching transistor output to invert, and the APD The cathode voltage decreases, and the avalanche is quenched. Simultaneously, the inverting output of the first high-speed comparator latches the quenching state through the inverting input of the latch enable. After the avalanche is quenched, the high-speed operational amplifier controlled by the FPGA cuts off the bias of the quenching transistor to achieve the lowest power consumption. Simultaneously, the reset lock signal is pulled low, and the latched state of the first high-speed comparator is released through the non-inverting input of the latch enable, restoring its comparison function. After the set dead time, or when the gate-on signal arrives, the FPGA controls the high-speed operational amplifier to restore the bias of the quenching transistor, at which point the APD resumes operation. In the narrow gating mode, the reset lock signal remains normally low, so that the first high-speed comparator cannot enter the latched state; at the same time, the reset lock signal is pulled low through the T-type network so that the base potential of the quenching transistor is always low, and the quenching transistor cannot be turned on. After the first high-speed comparator identifies the avalanche, it no longer has a quenching effect. The quenching and recovery of the APD are only completed by the narrow gating signal itself; at the same time, the inverting output end of the first high-speed comparator is normally output to the inverting input end of the second high-speed comparator, and is buffered by the second high-speed comparator and input into the FPGA, so that the avalanches can be counted normally.

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