Array substrate and liquid crystal display device
By adopting RGB+ miniaturized white subpixel design in projector products, adjusting the overlap area and capacitance structure of the gate and source of the transistor, the poor crosstalk problem of projector products under high temperature conditions is solved, and the balance of high transmittance and high brightness is achieved, and the production yield is improved.
Patent Information
- Application Number
- CN202410006587.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-02
- Publication Date
- 2025-07-08
AI Technical Summary
Existing projector products are difficult to meet the requirements of high transmittance and high brightness at high temperatures, resulting in poor crosstalk and low productivity in pixel design.
The design of RGB+ miniaturized white subpixels is adopted, and the overlap area and capacitance structure of the gate and source of the transistor are adjusted to equalize the voltage variation of each subpixel and reduce crosstalk failure.
It improves the color, brightness and transmittance of the display product, equalizes the voltage changes of the sub-pixels, and improves the yield of production.
Smart Images
Figure CN120276184A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the technical field of display, and particularly relates to an array substrate and a liquid crystal display device. Background Art
[0002] With the rapid development of display technology, diverse display products have emerged in the public eye, and users' requirements for display products are also getting higher and higher. For example, display products such as projectors are widely welcomed by users due to their high transmittance and high brightness. Therefore, improving transmittance and creating high-definition products close to 1080P has gradually become the mainstream research direction in the projector industry.
[0003] However, due to the high-temperature characteristics of the projector optical engine, certain bottlenecks have emerged in product design, especially in pixel design. To meet the requirements of high transmittance and high brightness, new problems often arise. Summary of the Invention
[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art, and provides an array substrate and a liquid crystal display device.
[0005] In a first aspect, the technical solution adopted to solve the technical problems of the present disclosure is an array substrate, which includes a substrate, and a plurality of gate lines and a plurality of data lines disposed on the substrate. The gate lines and the data lines intersect to define a plurality of pixel units; the gate lines extend in a first direction, the data lines extend in a second direction, and the first direction and the second direction intersect.
[0006] Each pixel unit includes at least one color sub-pixel and a white sub-pixel; the orthographic projection area of the white sub-pixel on the substrate is smaller than the orthographic projection area of the color sub-pixel on the substrate.
[0007] The white sub-pixel includes a first transistor, and the orthographic projection portions of the gate and the source of the first transistor on the substrate overlap to form a first capacitor; the color sub-pixel includes a second transistor, and the orthographic projection portions of the gate and the source of the second transistor on the substrate overlap to form a second capacitor; the first capacitor is smaller than the second capacitor.
[0008] In some embodiments, the overlapping area of the orthographic projection of the gate and the source of the first transistor on the substrate is a first overlapping area.
[0009] The overlapping area of the orthographic projection of the gate and the source of the second transistor on the substrate is a second overlapping area.
[0010] The first overlapping area is smaller than the second overlapping area.
[0011] In some embodiments, the ratio of the second overlapping area to the first overlapping area is between 1.4 and 1.6.
[0012] In some embodiments, the patterns of the projections of the gates in the first transistor and the gates in the second transistor on the substrate are the same;
[0013] The area of the projection of the source in the first transistor on the substrate is smaller than the area of the projection of the source in the second transistor on the substrate.
[0014] In some embodiments, the source in the first transistor is located on the side of the active layer of the second transistor away from the substrate;
[0015] The source in the second transistor includes a first conductive part and a second conductive part. The first conductive part is disposed on the side of the active layer of the second transistor away from the substrate. The second conductive part is connected to the first conductive part, and the surface of the second conductive part close to the substrate is coplanar with the surface of the active layer of the second transistor close to the substrate.
[0016] In some embodiments, the white sub-pixel further includes a first pixel electrode electrically connected to the first transistor and a first common electrode. The first pixel electrode and the first common electrode partially overlap in the projection on the substrate to form a third capacitor;
[0017] The color sub-pixel further includes a second pixel electrode electrically connected to the second transistor and a second common electrode. The second pixel electrode and the second common electrode partially overlap in the projection on the substrate to form a fourth capacitor;
[0018] The third capacitor is smaller than the fourth capacitor.
[0019] In some embodiments, the first common electrode includes a plurality of first common electrode strips; the second common electrode includes a plurality of second common electrode strips;
[0020] The number of the first common electrode strips included in the first common electrode is less than the number of the second common electrode strips included in the second common electrode.
[0021] In some embodiments, the overlapping area between the first common electrode strip and the first pixel electrode is a third overlapping area; the overlapping area between the second common electrode strip and the second pixel electrode is a fourth overlapping area;
[0022] The third overlapping area is larger than the fourth overlapping area.
[0023] In some embodiments, the width of the first common electrode strip in the first direction is greater than the width of the second common electrode strip in the first direction.
[0024] In some embodiments, the ratio of the third overlapping area to the fourth overlapping area is between 0.6 and 0.69.
[0025] In some embodiments, the array substrate includes a pixel electrode layer, a common electrode layer, and a channel insulating layer disposed between the pixel electrode layer and the common electrode layer;
[0026] The first pixel electrode and the second pixel electrode are located in the pixel electrode layer; the first common electrode and the second common electrode are located in the common electrode layer.
[0027] In some embodiments, the thickness of the channel insulating layer is between.
[0028] In some embodiments, the pixel unit includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel;
[0029] For one pixel unit, the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged side by side in the first direction.
[0030] In a second aspect, an embodiment of the present disclosure further provides a liquid crystal display device, including the array substrate according to any one of the first aspect. Description of the Drawings
[0031] Figure 1a It is a schematic diagram of the change of the sub-pixel voltage in the driving circuit of the sub-pixel;
[0032] Figure 1b It is a circuit diagram of the equivalent driving circuit of the sub-pixel;
[0033] Figure 2 It is a schematic diagram of the array substrate provided by the embodiment of the present disclosure;
[0034] Figure 3a It is a layout of the gate and source of the first transistor provided by the embodiment of the present disclosure;
[0035] Figure 3b It is a layout of the gate and source of the second transistor provided by the embodiment of the present disclosure;
[0036] Figure 4a It is a cross-sectional view of the white sub-pixel provided by the embodiment of the present disclosure;
[0037] Figure 4b It is a cross-sectional view of the color sub-pixel provided by the embodiment of the present disclosure;
[0038] Figure 5 Layout of the color sub-pixel and the white sub-pixel provided by the embodiments of the present disclosure;
[0039] Figure 6a is Figure 5 Plan view of the first common electrode corresponding to the white sub-pixel in
[0040] Figure 6b is Figure 5 Plan view of the second common electrode corresponding to the color sub-pixel in
[0041] Figure 7 is Figure 5 Cross-sectional view in the AA' direction in
[0042] Figure 8 Schematic diagram of an exemplary one-to-one sub-pixel pattern conversion;
[0043] Figure 9 Schematic diagram of another exemplary two-to-one sub-pixel pattern conversion;
[0044] Figure 10 Schematic diagram of another exemplary four-to-three sub-pixel pattern conversion. Detailed implementation manners
[0045] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. Components of the embodiments of the present disclosure usually described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed present disclosure, but merely represents selected embodiments of the present disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.
[0046] Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the field to which this disclosure pertains. The terms "first", "second" and similar terms used in this disclosure do not denote any order, quantity or importance, but are merely used to distinguish different components. Similarly, terms such as "a", "an" or "the" do not denote a limitation of quantity, but rather indicate the presence of at least one. Terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "upper", "lower", "left" and "right" are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0047] As used in this disclosure, "a plurality of" or "several" means two or more. "And / or" describes the association relationship of associated objects and indicates that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally represents an "or" relationship between the associated objects before and after.
[0048] In this disclosure, unless otherwise specified, the term "formed on the same layer" means that two layers, components, members, elements or parts can be formed by the same lithography process, and generally, these two layers, components, members, elements or parts are formed of the same material. Additionally, it should be noted that in this disclosure, two structures being "formed on the same layer" means that they are formed of the same material layer, so they are in the same layer in the stacking relationship, but it does not mean that their distances from the substrate are equal, nor does it mean that the other layer structures between them and the substrate are exactly the same.
[0049] In the embodiments of this disclosure, the transistor may be a thin-film transistor or a field-effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetric, there is no distinction between its source and drain. This disclosure takes the thin-film transistor as an example for illustration. The thin-film transistor may be an N-type thin-film transistor or a P-type thin-film transistor; among them, the N-type thin-film transistor refers to the N-type ion doping in the active layer of the thin-film transistor; the P-type thin-film transistor refers to the P-type ion doping in the active layer of the thin-film transistor. The working level signal of the N-type thin-film transistor is a high-level signal; the working level signal of the P-type thin-film transistor is a low-level signal.
[0050] It should be noted that the size of the capacitor involved in the present disclosure refers to the capacitance value. The first capacitor is smaller than the second capacitor, which can be understood as the capacitance value of the first capacitor is smaller than that of the second capacitor.
[0051] In the related art, by reducing the coverage area of the gate of the transistor TFT in the sub-pixel on the active layer channel, the transmittance of the sub-pixel is improved. However, this design will cause a significant increase in the TFT characteristic parameter Ioff (representing the magnitude of the leakage current of the TFT, the lower it is, the better the off-state characteristics of the TFT) under high-brightness light sources, resulting in problems such as crosstalk. Moreover, in the conventional pixel design of liquid crystal display products, it is also necessary to comprehensively consider the overlapping capacitances of each film layer, such as C st (representing the overlapping capacitance between the pixel electrode and the common electrode), C gs (representing the overlapping capacitance between the gate and the source of the TFT), etc. Among them, the size of the overlapping capacitance is closely related to the pixel feed voltage △Vp (which can be understood as a parameter related to the crosstalk problem). The voltage output by the driving chip IC to each sub-pixel is the same, but if the △Vp corresponding to each sub-pixel is inconsistent, it will cause a certain degree of crosstalk problems; once crosstalk problems occur, it will further cause the production products to be scrapped, greatly affecting the production yield.
[0052] It should be noted that Figure 1a is a schematic diagram of the change in the sub-pixel voltage in the driving circuit of the sub-pixel, Figure 1b is the circuit diagram of the equivalent driving circuit of the sub-pixel. When the gate line Gate or the data line Data is turned on or off, the sub-pixel voltage on the sub-pixel changes due to the capacitance coupling effect. The thick solid line 01 represents the gate line voltage (Vgate), and the thin solid line 02 represents the sub-pixel voltage (Vpixel). When the gate of the transistor TFT is loaded with the gate line voltage (Vgate) and turned on, the pixel unit is charged row by row, and the sub-pixel voltage (Vpixel) increases accordingly. However, due to capacitance coupling, the sub-pixel voltage (Vpixel) will be pulled down by △Vp, making the sub-pixel unable to be fully charged, thus affecting various performances of the panel. As Figure 1b shown, each coupling voltage has a great influence on the sub-pixel voltage (Vpixel). Among them, C st represents the overlapping capacitance between the pixel electrode and the common electrode, C gs represents the overlapping capacitance between the gate and the source of the TFT, and C lc represents the coupling capacitance affected by the liquid crystal between the pixel electrode and the common electrode in the sub-pixel, which needs to be obtained through simulation tests.
[0053] In view of this, embodiments of the present disclosure provide an array substrate, which adopts the technical solution of red, green, and blue sub-pixels RGB + miniaturized white sub-pixel W to improve the color, brightness, and transmittance of display products; further, by improving the pixel design, the △Vp of each sub-pixel is substantially balanced, and to a certain extent, the △Vp is reduced, and the crosstalk defect of the product is eliminated as much as possible, and the product yield is improved.
[0054] The array substrate in the embodiments of the present disclosure will be described below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.
[0055] Figure 2 It is a schematic diagram of the array substrate provided by the embodiments of the present disclosure. As Figure 2 shown, the array substrate includes a substrate 1 and a plurality of gate lines Gate and a plurality of data lines Data disposed on the substrate 1, wherein the gate lines Gate and the data lines Data intersect to define a plurality of pixel units 2.
[0056] The gate lines Gate extend along a first direction X, and the data lines Data extend along a second direction Y, and the first direction X and the second direction Y intersect.
[0057] Exemplarily, the first direction X and the second direction Y are perpendicular.
[0058] Exemplarily, the array substrate includes a plurality of pixel units 2 arranged in an array, specifically arranged in a rectangular array, that is, including multiple rows of pixel units 2 and multiple columns of pixel units 2, wherein the first direction X is the row direction and the second direction Y is the column direction.
[0059] For any pixel unit 2, it includes at least one color sub-pixel 21 and a white sub-pixel W. Wherein, the orthographic projection area of the white sub-pixel W on the substrate 1 is smaller than the orthographic projection area of the color sub-pixel 21 on the substrate 1.
[0060] Exemplarily, the color sub-pixel 21 can be any one of a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. For example, the pixel unit 2 includes any one or a combination of multiple of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B, and the white sub-pixel W.
[0061] Exemplarily, as Figure 2 shown, the pixel unit 2 includes a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W. At this time, the orthographic projection areas of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B on the substrate 1 are all larger than the orthographic projection area of the white sub-pixel W on the substrate 1.
[0062] Exemplarily, the first dimension of the white sub-pixel W in the first direction X is smaller than the second dimension of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the first direction X. The third dimension of the white sub-pixel W in the second direction Y is equal to or smaller than the fourth dimension of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the second direction Y. The first dimension represents the length of the sub-pixel of the white sub-pixel W in the first direction X, and the second dimension represents the length of the sub-pixel of the color sub-pixel 21 in the first direction X. The third dimension represents the width of the sub-pixel of the white sub-pixel W in the second direction Y, and the fourth dimension represents the width of the sub-pixel of the color sub-pixel 21 in the second direction Y.
[0063] That is to say, the pixel unit 2 of the present disclosure adopts the sub-pixel distribution of RGB + miniaturized W, which can improve the color, brightness, and transmittance of the display product. Among them, compared with the scheme of equal-sized sub-pixels in the original RGBW, the design of the miniaturized white sub-pixel W improves the transmittance by more than 7%, meeting the user's demand for high transmittance.
[0064] For the sub-pixel distribution of RGB + miniaturized W, since the size of the white sub-pixel W is smaller than that of the color sub-pixel 21, it indirectly leads to the inconsistency between the storage capacitance of the white sub-pixel W and the storage capacitance of the color sub-pixel 21, resulting in the inconsistency of the crosstalk-related parameter △Vp. According to the following expression one, it can be known that the △Vp of the small-sized white sub-pixel W is greater than that of the color sub-pixel 21. Due to the inconsistency of △Vp between the white sub-pixel W and the color sub-pixel 21, it affects the brightness consistency of each sub-pixel, resulting in non-uniform light efficiency of the display panel, and further causing defects such as flicker in the display panel screen.
[0065] Among them, the storage capacitance at least includes the overlapping capacitance Cst between the pixel electrode and the common electrode. The relevant expression of △Vp is shown in the following expression one:
[0066]
[0067] Among them, △Vp represents the pixel feed voltage corresponding to a single sub-pixel; C gs represents the overlapping capacitance between the gate and the source of the transistor in the sub-pixel; Vgh represents the highest applied voltage of the transistor gate in the sub-pixel; Vgl represents the lowest applied voltage of the transistor gate in the sub-pixel; C st represents the overlapping capacitance between the pixel electrode and the common electrode in the sub-pixel; C lc represents the coupling capacitance affected by the liquid crystal between the pixel electrode and the common electrode in the sub-pixel, which needs to be obtained through simulation tests.
[0068] According to the above expression one, it can be known that △Vp is related to the overlapping capacitances C gs and C stAre closely related. Therefore, by adjusting the overlapping capacitance C of the sub-pixels gs , C st , the consistency of △Vp between the white sub-pixel W and the color sub-pixel 21 can be achieved.
[0069] Specifically, the white sub-pixel W includes a first transistor TFT1. The overlapping part of the gate and the source of the first transistor TFT1 in the positive projection on the substrate 1 forms a first capacitance; the color sub-pixel 21 includes a second transistor TFT2. The overlapping part of the gate and the source of the second transistor TFT2 in the positive projection on the substrate 1 forms a second capacitance. The first capacitance is smaller than the second capacitance. For example, the overlapping capacitance formed by the gate and the source of the first transistor TFT1 in the original white sub-pixel W is the first capacitance The overlapping capacitance formed by the gate and the source of the second transistor TFT2 in the original color sub-pixel 21 is also the first capacitance This disclosure keeps the first capacitance of the original white sub-pixel W unchanged, and increases the overlapping capacitance between the gate and the source in the second transistor TFT2 of the color sub-pixel 21 to be the second capacitance The second capacitance is greater than the first capacitance of the original color sub-pixel 21 Based on this improvement scheme, according to Expression 1, it is deduced that the △Vp of the color sub-pixel 21 is finally increased. Due to the above conclusion "in the conventional design, the △Vp of the small-sized white sub-pixel W is greater than the △Vp of the color sub-pixel 21", this disclosure narrows the difference between the △Vp of the white sub-pixel W and the △Vp of the color sub-pixel 21 by increasing the △Vp of the color sub-pixel 21, so as to balance the △Vp of each sub-pixel on the premise of ensuring the color, brightness and transmittance of the display product, eliminate the crosstalk defect of the product as much as possible, and improve the product yield.
[0070] It should be noted that there are various ways to increase the overlapping capacitance between the gate and the source in the second transistor TFT2 of the color sub-pixel 21. One way is to increase the overlapping area between the gate and the source in the second transistor TFT2; another way is to shorten the vertical distance between the gate and the source in the second transistor TFT2; still another way is to adjust the material of the dielectric layer between the layer where the gate is located and the layer where the source is located.
[0071] To understand the relationship between △Vp and the overlapping area more clearly, the following is a simple formula derivation on the premise that the △Vp of the white sub-pixel W and the color sub-pixel 21 is consistent.
[0072]
[0073] C = C i × S 重叠面积………………………Formula II
[0074]
[0075] Wherein, C i represents the unit capacitance; d represents the distance between the two electrodes forming the capacitor; C represents any overlapping capacitor, that is, Formula II is the calculation formula for any overlapping capacitor; S 重叠面积 represents the overlapping area between the two electrodes forming the capacitor. Substituting Formula II into Formula III, the following Formula IV is obtained.
[0076]
[0077] Wherein, S′ gs is the first overlapping area between the gate and the source of the first transistor TFT1 corresponding to the white sub-pixel W; S gs represents the second overlapping area between the gate and the source of the second transistor TFT2 corresponding to the color sub-pixel 21; S′ st represents the overlapping area between the first common electrode 51 and the first pixel electrode 41 in the first transistor TFT1 corresponding to the white sub-pixel W; S st represents the overlapping area between the second common electrode 52 and the second pixel electrode 42 in the second transistor TFT2 corresponding to the color sub-pixel 21. a, b, c, c′ are constants respectively.
[0078] In some embodiments, Figure 3a is the layout of the gate and the source of the first transistor provided by the embodiment of the present disclosure, Figure 3b is the layout of the gate and the source of the second transistor provided by the embodiment of the present disclosure.
[0079] As Figure 3a shown, the overlapping area of the orthographic projection of the gate G1 (a part of the gate line Gate) and the source S1 in the first transistor TFT1 on the substrate 1 is the first overlapping area; as Figure 3b shown, the overlapping area of the orthographic projection of the gate G2 and the source S2 in the second transistor TFT2 on the substrate 1 is the second overlapping area; the first overlapping area is smaller than the second overlapping area.
[0080] That is, in this embodiment, by increasing the overlapping area between the gate G2 and the source S2 in the second transistor TFT2, the capacitance between the gate G2 and the source S2 in the second transistor TFT2 is increased to be the second capacitance Thereby increasing the △Vp of the color sub-pixel 21 彩 , and shortening the △Vp of the white sub-pixel W as much as possible 白 The difference from the △Vp of the color sub-pixel 21 彩 is increased, and the △Vp of the white sub-pixel W is improved白 the △Vp of the color sub-pixel 21 彩 consistency
[0081] As Figure 3a shown, the source S1 of the first transistor TFT1 includes a first main part S11 and a first connection part S12 connected to the first pixel electrode 41; mainly, the partial orthographic projection of the first main part S11 on the substrate 1 overlaps with the orthographic projection of the gate G1 of the first transistor TFT1 on the substrate 1. The first connection part S12 has no overlap with the orthographic projection of the gate G1 of the first transistor TFT1 on the substrate 1. Similarly, as Figure 3b shown, the source S2 of the second transistor TFT2 includes a second main part S21 and a second connection part S22 connected to the second pixel electrode 42; mainly, the partial orthographic projection of the second main part S21 on the substrate 1 overlaps with the orthographic projection of the gate G2 of the second transistor TFT2 on the substrate 1. The second connection part S22 has no overlap with the orthographic projection of the gate of the second transistor TFT2 on the substrate 1.
[0082] Optionally, the ratio of the second overlapping area to the first overlapping area is between 1.4 and 1.6.
[0083] For example, the ratio of the second overlapping area to the first overlapping area is 1.4. For example, the ratio of the second overlapping area to the first overlapping area is 1.5. For example, the ratio of the second overlapping area to the first overlapping area is 1.6.
[0084] It should be noted that there are multiple ways to increase the overlapping area between the gate G2 and the source S2 in the second transistor TFT2. One way can be to ensure that the patterns of the gate G1 of the first transistor TFT1 and the gate G2 of the second transistor TFT2 on the substrate 1 are the same, and increase the coverage area of the source S2 of the second transistor TFT2 to be larger than the coverage area of the source S1 of the first transistor TFT1. Another way can be to ensure that the patterns of the source S1 of the first transistor TFT1 and the source S2 of the second transistor TFT2 on the substrate 1 are the same, and increase the coverage area of the gate G2 of the second transistor TFT2 to be larger than the coverage area of the gate G1 of the first transistor TFT1.
[0085] In some embodiments, as Figure 3a and Figure 3b shown, the patterns of the orthographic projections of the gate G1 in the first transistor TFT1 and the gate G2 in the second transistor TFT2 on the substrate 1 are the same; the area of the orthographic projection of the source S1 in the first transistor TFT1 on the substrate 1 is smaller than the area of the orthographic projection of the source S2 in the second transistor TFT2 on the substrate 1.
[0086] The orthographic projection of the gate G1 of the first transistor TFT1 on the substrate 1 completely covers the orthographic projection of the active layer A1 of the first transistor TFT1 on the substrate 1. The orthographic projection of the gate G2 of the second transistor TFT2 on the substrate 1 completely covers the orthographic projection of the active layer A2 of the second transistor TFT2 on the substrate 1. The source is electrically connected to the source contact region of the active layer. Therefore, the orthographic projection of the source on the substrate 1 falls within the orthographic projection of the gate on the substrate 1. The present disclosure increases the coverage area of the source S2 of the second transistor TFT2, that is, increases the overlapping area of the orthographic projections of the source S2 and the gate G2 of the second transistor TFT2 on the substrate 1, thereby increasing the capacitance between the gate G2 and the source S2 in the second transistor TFT2 as the second capacitance, and further increasing △Vp 彩 , as close as possible to △Vp 白 .
[0087] In some embodiments, Figure 4a is a cross-sectional view of a white sub-pixel provided by an embodiment of the present disclosure, Figure 4b is a cross-sectional view of a color sub-pixel provided by an embodiment of the present disclosure.
[0088] As Figure 4a shown, the first transistor TFT1 includes a gate G1 (i.e., a part of the gate line Gate) provided on the substrate 1, a gate insulating layer 31 provided on the side of the gate G1 away from the substrate 1, an active layer A1 provided on the side of the gate insulating layer 31 away from the gate G1, a source S1 provided on the side of the active layer A1 away from the gate insulating layer 31, and a drain (i.e., a part of Data).
[0089] As Figure 4b shown, the second transistor TFT2 includes a gate G2 (i.e., a part of the gate line Gate) provided on the substrate 1, a gate insulating layer 31 provided on the side of the gate G2 away from the substrate 1, an active layer A2 provided on the side of the gate insulating layer 31 away from the gate G2, a source S2 provided on the side of the active layer A2 away from the gate insulating layer 31, and a drain (i.e., a part of Data).
[0090] As Figure 4a and Figure 4b shown, for the color sub-pixels 21 and the white sub-pixel W arranged in the same row, the gate line Gate in that row is multiplexed as the gate G1 of the first transistor TFT1 and the gate G2 of the second transistor TFT2.
[0091] As Figure 4a and Figure 4bAs shown, the active layer A1 of the first transistor TFT1 and the active layer A2 of the second transistor TFT2 are arranged on the same layer. Exemplarily, the shape of the active layer can be set according to the size requirements of the actual sub-pixels. For example, a U-shaped active layer can be selected for large sizes, a trapezoidal active layer can be selected for small sizes, etc. Or a rectangular active layer can also be selected. In the embodiments of the present disclosure, a rectangular active layer is used for illustration, but this does not limit the shape of the actual active layer.
[0092] As Figure 4a and Figure 4b shown, the source S1 and drain (data line Data) of the first transistor TFT1, and the source S2 and drain (data line Data) of the second transistor TFT2 are arranged on the same layer.
[0093] As Figure 4a shown, both the source S1 and drain (data line Data) in the first transistor TFT1 are located on the side of the active layer A1 of the first transistor TFT1 away from the substrate 1.
[0094] As Figure 4b shown, the drain (data line Data) in the second transistor TFT2 is located on the side of the active layer A2 of the second transistor TFT2 away from the substrate 1. The source S2 of the second transistor TFT2 includes a first conductive portion S22a and a second conductive portion S22b. The first conductive portion S22a is arranged on the side of the active layer A2 of the second transistor TFT2 away from the substrate 1. The second conductive portion S22b is connected to the first conductive portion S22a, and the surface of the second conductive portion S22b close to the substrate 1 is coplanar with the surface of the active layer A2 of the second transistor TFT2 close to the substrate 1.
[0095] As Figure 3b and Figure 4b shown, the first conductive portion S22a and the second conductive portion S22b are an integrally formed structure.
[0096] The source S2 of the second transistor TFT2 has an increased second conductive portion S22b compared with the source S1 of the first transistor TFT1, thereby increasing the overlapping area of the projection of the source S2 of the second transistor TFT2 and the gate G2 on the substrate 1, and further increasing the capacitance between the gate G2 and the source S2 in the second transistor TFT2 to be the second capacitance.
[0097] The above-mentioned various embodiments and their combinations increase the C gs corresponding to the color sub-pixel 21, improve the △Vp 彩 of the color sub-pixel 21, balance the △Vp 彩 of the color sub-pixel 21 白 and the △Vp of the white sub-pixel W, and eliminate the crosstalk defect of the product as much as possible, and improve the product yield.
[0098] As Figure 4a and Figure 4b shown, for the film layer preparation process of each sub-pixel of the present disclosure, it specifically includes: adopting a 6-mask Mask process to provide a substrate; then, forming a gate metal layer on the substrate by the first Mask process; the gate lines corresponding to each row of pixel units are all located in the gate metal layer; then, by a deposition process, a gate insulating layer material is deposited on the entire surface of the side of the gate metal layer facing away from the substrate, and a gate insulating layer 31 is formed; then, by the second Mask process, an active layer of the transistor in each sub-pixel is formed on the side of the gate insulating layer 31 facing away from the gate metal layer; then, by the third Mask process, a pixel electrode layer 32 is formed on the side of the active layer 1 facing away from the gate insulating layer 31; the first pixel electrode 41 and the second pixel electrode 42 are both located in the pixel electrode layer 32; then, by the fourth Mask process, a source electrode and a drain electrode of the transistor in each sub-pixel are formed on the side of the active layer 1 facing away from the gate insulating layer 31; then, by the fifth Mask process, a channel insulating layer PVX is formed on the sides of each transistor source electrode, drain electrode, and the pixel electrode layer 32 facing away from the gate insulating layer 31; then, by the sixth Mask process, a common electrode layer 33 is formed on the side of the channel insulating layer PVX facing away from the substrate 1. The first common electrode 51 and the second common electrode 52 are both located in the common electrode layer 33.
[0099] Further, according to Expression One, it can be known that △Vp is also closely related to the overlapping capacitance C st After determining C' of the white sub-pixel W gs and C of the color sub-pixel 21 gs In the following, some embodiments reduce △Vp of the white sub-pixel W by increasing C' of the white sub-pixel W st , thereby narrowing the difference between △Vp of the white sub-pixel W 白 and △Vp of the color sub-pixel 21 白 as much as possible, so that △Vp 彩 is as consistent as possible with △Vp 白 . 彩
[0100] Figure 5 FIGURES 30-32 are layout diagrams of the color sub-pixel and the white sub-pixel provided by the embodiments of the present disclosure; Figure 6a FIG. Figure 5 33 is a plan view of the first common electrode corresponding to the white sub-pixel in FIG. Figure 6b FIG. Figure 5 34 is a plan view of the second common electrode corresponding to the color sub-pixel in FIG. Figure 7 FIG. Figure 5 35 is a cross-sectional view in the AA' direction in FIG.
[0101] In some embodiments, asFigure 5 , Figure 6a and Figure 7 As shown in Figure 5 , Figure 6a , and Figure 7 , the white sub-pixel W further includes a first pixel electrode 41 electrically connected to the first transistor TFT1, and a first common electrode 51. A part of the orthographic projection of the first pixel electrode 41 and the first common electrode 51 on the substrate 1 overlaps to form a third capacitor.
[0102] As Figure 5 , Figure 6b and Figure 7 As shown in Figure 5 , Figure 6b , and Figure 7 , the color sub-pixel 21 further includes a second pixel electrode 42 electrically connected to the second transistor TFT2, and a second common electrode 52; a part of the orthographic projection of the second pixel electrode 42 and the second common electrode 52 on the substrate 1 overlaps to form a fourth capacitor.
[0103] Since the present disclosure needs to ensure high brightness and high transmittance of the product, the size of the white sub-pixel W is limited, resulting in the third capacitor being smaller than the fourth capacitor.
[0104] In some embodiments, as Figure 6a and Figure 6b shown, the first common electrode 51 includes a plurality of first common electrode strips 511; the second common electrode 52 includes a plurality of second common electrode strips 521. By setting the number of the first common electrode strips 511 included in the first common electrode 51 to be less than the number of the second common electrode strips 521 included in the second common electrode 52, the white sub-pixel W is miniaturized, and thus high brightness and high transmittance of the product are ensured.
[0105] In some embodiments, as Figure 6a and Figure 6b shown, the plurality of first common electrode strips 511 are integrally formed to form the first common electrode 51; the plurality of second common electrode strips 521 are integrally formed to form the second common electrode 52.
[0106] In some embodiments, as Figure 5 shown, the first common electrode 51 and the second common electrode 52 are of an integrally formed structure.
[0107] In some embodiments, as Figure 6a , Figure 6b and Figure 7 shown, the overlapping area between the first common electrode strip 511 and the first pixel electrode 41 is the third overlapping area; the overlapping area between the second common electrode strip 521 and the second pixel electrode 42 is the fourth overlapping area; the third overlapping area is larger than the fourth overlapping area.
[0108] Based on ensuring the high brightness and high transmittance of the product, the embodiments of the present disclosure increase the overlapping area between the first common electrode strip 511 and the first pixel electrode 41, thereby increasing the overlapping capacitance between a single first common electrode strip 511 and the first pixel electrode 41, and further increasing the overlapping capacitance between the first common electrode 51 and the first pixel electrode 41 to be the third capacitance. According to Expression 1, the △Vp of the white sub-pixel W is reduced. 白 , thereby narrowing the △Vp of the white sub-pixel W. 白 and the △Vp of the color sub-pixel 21. 彩 The difference between them is reduced, and the consistency between the two is improved.
[0109] Optionally, the ratio of the third overlapping area to the fourth overlapping area is between 0.6 and 0.69.
[0110] For example, the ratio of the third overlapping area to the fourth overlapping area is 0.6, 0.61, 0.62, 0.63, 0.64, 0.65, 0.66, 0.67, 0.68 or 0.69.
[0111] In some embodiments, as Figure 7 shown, the width of the first common electrode strip 511 in the first direction X is greater than the width of the second common electrode strip 521 in the first direction X.
[0112] Exemplarily, the width of the first common electrode strip 511 in the first direction X is between 2.1 μm and 2.3 μm; the width of the second common electrode strip 521 in the first direction X is between 2.0 μm and 2.1 μm. For example, the width of the first common electrode strip 511 in the first direction X is 2.2 μm or 2.3 μm. The width of the second common electrode strip 521 in the first direction X is 2.0 μm or 2.1 μm.
[0113] Exemplarily, as Figure 7 shown, the spacing between adjacent first common electrode strips 511 in the first direction X is the same.
[0114] Exemplarily, as Figure 7 shown, the spacing between adjacent second common electrode strips 521 in the first direction X is the same.
[0115] Exemplarily, as Figure 7 shown, the shortest spacing between adjacent first common electrode strips 511 is the first spacing L1; the shortest spacing between adjacent second common electrode strips 521 is the second spacing L2; the first spacing L1 is less than the second spacing L2. For example, the first spacing L1 is 3.6 μm. The second spacing L2 is 3.7 μm.
[0116] Exemplarily, as Figure 7As shown, the minimum distance between the data line Data and the first pixel electrode 41 in the first direction X is the same as the minimum distance between the data line Data and the second pixel electrode 42 in the first direction X.
[0117] Based on ensuring the high brightness and high transmittance of the product, in the embodiments of the present disclosure, by increasing the width of the first common electrode strip 511, the overlapping capacitance between a single first common electrode strip 511 and the first pixel electrode 41 is improved, and further the overlapping capacitance between the first common electrode 51 and the first pixel electrode 41 is the third capacitance. According to Expression 1, the △Vp of the white sub-pixel W is reduced, thereby narrowing the difference between the △Vp of the white sub-pixel W and the △Vp of the color sub-pixel 21, and improving the consistency of the △Vp of the two.
[0118] In some embodiments, as Figure 7 shown, the array substrate includes a pixel electrode layer 32, a common electrode layer 33, and a channel insulating layer PVX disposed between the pixel electrode layer 32 and the common electrode layer 33. The first pixel electrode 41 and the second pixel electrode 42 are both located in the pixel electrode layer 32; the first common electrode 51 and the second common electrode 52 are both located in the common electrode layer 33.
[0119] In the embodiments of the present disclosure, by reducing the thickness of the channel insulating layer PVX, the △Vp of the white sub-pixel W and the color sub-pixel 21 is reduced.
[0120] Optionally, the thickness of the channel insulating layer PVX is between For the case where the ratio of the second overlapping area to the first overlapping area is between 1.4 and 1.6; and the ratio of the third overlapping area to the fourth overlapping area is between 0.6 and 0.69, setting the thickness of the channel insulating layer PVX between can better uniform the △Vp between the white sub-pixel W and the color sub-pixel 21, and achieve the consistency of the △Vp of each sub-pixel.
[0121] For example, the thickness of the channel insulating layer PVX is or
[0122] According to Formula 1, when the thickness of the channel insulating layer PVX is reduced, the unit capacitance increases, so that the third capacitance C′ of the white sub-pixel W st and the fourth capacitance C of the color sub-pixel 21 st both increase, making △Vp 白 and △Vp 彩 synchronously decrease. The decrease of △Vp further eliminates the defects caused by crosstalk and reduces the flicker phenomenon of the display screen.
[0123] Exemplarily, the material of the channel insulating layer PVX can be selected as silicon nitride (SiNx).
[0124] In some embodiments, such as Figure 2 shown, the pixel unit 2 includes a red sub-pixel R, a green sub-pixel G, a blue sub-pixel B, and a white sub-pixel W; for one pixel unit 2, the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W are arranged side by side along the first direction X.
[0125] This embodiment is directed to the sub-pixel distribution of RGB + miniaturized W, and the specific distribution pattern is as follows.
[0126] Figure 8 It is a schematic diagram of an exemplary one-to-one sub-pixel pattern conversion. As Figure 8 shown, where Figure 8 Figure (a) in shows a pixel unit 2 in the related art, and the pixel unit 2 in the related art only includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; Figure 8 Figure (b) in shows the distribution of converting the size of one pixel unit 2 in Figure (a) into a sub-pixel of RGB + miniaturized W. Specifically, the sizes of the two pixel units 2 are the same, mainly including that the physical resolution of a single pixel unit 2 (i.e., a×d) remains unchanged, and the number of pixel units 2 remains unchanged. Figure (b) adds a miniaturized white sub-pixel W compared to Figure (a). Among them, the sizes of the red sub-pixel R, the green sub-pixel G, the blue sub-pixel B, and the white sub-pixel W in the second direction Y (i.e., size d) are the same, and the size of the white sub-pixel W in the first direction is smaller than the size of any one of the red sub-pixel R, the green sub-pixel G, and the blue sub-pixel B in the first direction.
[0127] Figure 9 It is another schematic diagram of an exemplary two-to-one sub-pixel pattern conversion. As Figure 9 shown, where Figure 9 Figure (c) in shows two pixel units 2 in the related art, and the pixel unit 2 in the related art only includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; Figure 9Figure (d) in [description] shows the distribution of sub-pixels obtained by converting the sizes of two pixel units 2 in Figure (c) into one RGB+miniaturized W sub-pixel. As shown in Figures (c) and (d), two pixel units 2 (RGB) are converted into one pixel unit 2 (RGB+miniaturized W). At this time, the physical resolution of two pixel units 2 in the related art is equal to the physical resolution of one pixel unit 2 in this embodiment. The size of a single sub-pixel in the converted pixel unit 2 is slightly increased compared to that of a single sub-pixel in the pixel unit 2 before conversion. However, the sizes (i.e., size d) of the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W in the converted pixel unit 2 in the second direction Y are the same, and the size of the white sub-pixel W in the first direction is smaller than that of any one of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B in the first direction.
[0128] Figure 10 Another exemplary schematic diagram of a 4:3 sub-pixel pattern conversion provided by an embodiment of the present disclosure is shown in Figure 10 as follows, where Figure 10 Figure (e) in [description] shows four pixel units 2 in the related art, and the pixel unit 2 in the related art only includes a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B; Figure 10 Figure (f) in [description] shows the distribution of sub-pixels obtained by converting the sizes of four pixel units 2 in Figure (e) into three RGB+miniaturized W sub-pixels. As shown in Figures (e) and (f), four pixel units 2 (RGB) are converted into three pixel units 2 (RGB+miniaturized W). At this time, the physical resolution of four pixel units 2 in the related art is equal to the physical resolution of three pixel units 2 in this embodiment. The size of a single sub-pixel in the converted pixel unit 2 is slightly increased compared to that of a single sub-pixel in the pixel unit 2 before conversion. However, the sizes (i.e., size d) of the red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W in the converted pixel unit 2 in the second direction Y are the same, and the size of the white sub-pixel W in the first direction is smaller than that of any one of the red sub-pixel R, green sub-pixel G, and blue sub-pixel B in the first direction.
[0129] As above Figures 8 - 10 , an appropriate sub-pixel pitch ratio of RGB and W can be selected through optical simulation to further improve the display brightness.
[0130] In addition, an embodiment of the present disclosure also provides a liquid crystal display device, which includes the array substrate described in any one of the above embodiments.
[0131] Exemplarily, the liquid crystal display device may be a projector. By adopting the technical solution of RGB + miniaturized W, the color and transmittance of the display product can be improved, so as to develop excellent high-transmittance projector products such as extremely fine amorphous silicon (a-Si). Further, by improving the pixel design, the △Vp of each sub-pixel is substantially balanced, and the △Vp is reduced to a certain extent, and the crosstalk defect of the product is eliminated as much as possible, and the product yield is improved.
[0132] Exemplarily, the liquid crystal display device further includes a color filter substrate, and the color filter substrate is disposed opposite to the array substrate. A liquid crystal layer is filled between the color filter substrate and the array substrate.
[0133] Another exemplarily, the display device may also be any product with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a vehicle-mounted device, etc.
[0134] Other essential components of the display device should be understood by those of ordinary skill in the art and will not be described herein, nor should they be considered as a limitation to the present disclosure.
[0135] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.
Claims
1. An array substrate, which includes a substrate, and a plurality of gate lines and a plurality of data lines disposed on the substrate, wherein the gate lines and the data lines intersect to define a plurality of pixel units; the gate lines extend in a first direction, the data lines extend in a second direction, and the first direction intersects the second direction; The pixel unit includes at least one color sub-pixel and a white sub-pixel; the orthographic projection area of the white sub-pixel on the substrate is smaller than the orthographic projection area of the color sub-pixel on the substrate; The white sub-pixel includes a first transistor, and a positive projection part of the gate and the source in the first transistor overlaps on the substrate to form a first capacitor; the color sub-pixel includes a second transistor, and a positive projection part of the gate and the source in the second transistor overlaps on the substrate to form a second capacitor; the first capacitor is smaller than the second capacitor.
2. The array substrate according to claim 1, wherein, The overlapping area of the positive projection of the gate and the source in the first transistor on the substrate is a first overlapping area; The overlapping area of the positive projection of the gate and the source in the second transistor on the substrate is a second overlapping area; The first overlapping area is smaller than the second overlapping area.
3. The array substrate according to claim 2, wherein, The ratio of the second overlapping area to the first overlapping area is between 1.4 and 1.
6.
4. The array substrate according to claim 2, wherein, The patterns of the positive projections of the gate in the first transistor and the gate in the second transistor on the substrate are the same; The area of the positive projection of the source in the first transistor on the substrate is smaller than the area of the positive projection of the source in the second transistor on the substrate.
5. The array substrate according to claim 4, wherein, The source in the first transistor is located on a side of the active layer of the second transistor away from the substrate; The source in the second transistor includes a first conductive part and a second conductive part, the first conductive part is disposed on a side of the active layer of the second transistor away from the substrate, the second conductive part is connected to the first conductive part, and the surface of the second conductive part close to the substrate is coplanar with the surface of the active layer of the second transistor close to the substrate.
6. The array substrate according to claim 1, wherein, The white sub-pixel further includes a first pixel electrode electrically connected to the first transistor, and a first common electrode, and a positive projection part of the first pixel electrode and the first common electrode overlaps on the substrate to form a third capacitor; The color sub-pixel further includes a second pixel electrode electrically connected to the second transistor, and a second common electrode, and a positive projection part of the second pixel electrode and the second common electrode overlaps on the substrate to form a fourth capacitor; The third capacitor is smaller than the fourth capacitor.
7. The array substrate according to claim 6, wherein, The first common electrode includes a plurality of first common electrode strips; the second common electrode includes a plurality of second common electrode strips; The number of the first common electrode strips included in the first common electrode is less than the number of the second common electrode strips included in the second common electrode.
8. The array substrate according to claim 7, wherein, The overlapping area between the first common electrode strip and the first pixel electrode is a third overlapping area; the overlapping area between the second common electrode strip and the second pixel electrode is a fourth overlapping area; The third overlapping area is larger than the fourth overlapping area.
9. The array substrate according to claim 8, wherein, The width of the first common electrode strip in the first direction is larger than the width of the second common electrode strip in the first direction.
10. The array substrate according to claim 8 or 9, wherein, The ratio of the third overlapping area to the fourth overlapping area is between 0.6 and 0.
69.
11. The array substrate according to claim 6, wherein, The array substrate includes a pixel electrode layer, a common electrode layer, and a channel insulating layer disposed between the pixel electrode layer and the common electrode layer; The first pixel electrode and the second pixel electrode are located in the pixel electrode layer; the first common electrode and the second common electrode are located in the common electrode layer.
12. The array substrate according to claim 11, wherein, The thickness of the channel insulating layer is between and.
13. The array substrate according to claim 1, wherein, The pixel unit includes a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel; For one pixel unit, the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel are arranged side by side in the first direction.
14. A liquid crystal display device, which includes the array substrate according to any one of claims 1 to 13.