Mask and overlay error measurement method
By designing and testing and aligning the graphic structure on the mask, high-precision overturning error measurement is achieved, the problem of insufficient overturning accuracy in the lithography process is solved, and the research and development and production quality of semiconductor equipment is improved.
Patent Information
- Application Number
- CN202510465296.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-14
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, it is difficult to detect the intercalation accuracy in the lithography process to achieve high accuracy, which affects the research and development and production quality of semiconductor equipment.
Design a mask plate that includes test graphic structure and alignment graphic structure. By setting alignment marks and centerlines on the mask plate, combined with the rotation center, accurate overturn error measurement is achieved.
It improves the detection accuracy of the interlacing error, can calculate the rotation error and step splicing accuracy more accurately, and improves the quality control of the lithography process.
Smart Images
Figure CN120276207A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of detection technology, and particularly to a reticle and a method for measuring overlay error. Background Art
[0002] In the lithography process flow, first, a layer of photoresist is coated on the surface of a wafer (also known as a silicon wafer). Subsequently, using the light source provided by an exposure equipment, light is allowed to pass through a reticle engraved with a circuit pattern, that is, a photomask (abbreviated as mask) commonly referred to, and irradiate the wafer. Through the light-sensitive reaction of the photoresist material, the circuit pattern on the reticle is accurately transferred into the photoresist layer, thereby forming the required photoresist pattern.
[0003] Before the lithography process, all patterns designed with circuit graphics are made on the reticle. Circuit graphics design usually involves multi-layer stacking technology. In this process, it is necessary to accurately control the offset in the X and Y directions between each layer, that is, the overlay accuracy. The detection of overlay accuracy plays a crucial role in the research and development of semiconductor equipment, as well as the daily maintenance and equipment acceptance of semiconductor factories. Summary of the Invention
[0004] Embodiments of this application provide a reticle and a method for measuring overlay error, which are used to improve the detection accuracy of overlay error.
[0005] In some embodiments, a reticle is provided, which includes a test pattern structure disposed in the middle area of the reticle and an alignment pattern structure disposed on the outer periphery of the test pattern structure. The test pattern structure is used to form an overlay mark on the wafer, and the alignment pattern structure is used to perform reticle alignment. Among them, the center of the reticle is defined as the rotation center. The alignment pattern structure includes two first alignment marks, and the two first alignment marks are respectively located on opposite sides of the test pattern structure. The straight line where the two first alignment marks are located is parallel to and does not coincide with a first center line, and the first center line is a reference line passing through the rotation center in the plane of the reticle.
[0006] In some embodiments, the alignment pattern structure further includes two second alignment marks, and the two second alignment marks are respectively located on opposite sides of the test pattern structure. The straight line where the two second alignment marks are located is parallel to and does not coincide with a second center line, and the second center line is a reference line passing through the rotation center in the plane of the reticle and perpendicular to the first center line. Among them,
[0007] The distance from the end of the second alignment mark close to the second center line to the second center line is greater than the distance from the end of the first alignment mark far from the first center line to the first center line;
[0008] Or, the distance from the end of the first alignment mark close to the first center line to the first center line is greater than the distance from the end of the second alignment mark far from the second center line to the second center line.
[0009] In some embodiments, the first alignment mark includes a plurality of strip-shaped patterns parallel to the first center line;
[0010] And / or, the second alignment mark includes a plurality of strip-shaped patterns parallel to the second center line.
[0011] In some embodiments, the distance from each first alignment mark to the rotation center is greater than 5 mm;
[0012] And / or, the distance from each second alignment mark to the rotation center is greater than 5 mm.
[0013] In some embodiments, the first alignment mark and the second alignment mark have the same graphic structure and a length of d, the distance from the center of the first alignment mark to the first center line is d, and the distance from the second alignment mark to the second center line is 3d;
[0014] Or, the distance from the center of the first alignment mark to the first center line is 3d, and the distance from the second alignment mark to the second center line is d.
[0015] In some embodiments, the mask includes a scribe lane region provided on the outer periphery of the middle region, the middle region is a rectangular region, one of the first center line and the second center line extends along the width direction of the middle region, and the other extends along the length direction of the middle region, the scribe lane region is an annular rectangular region, and the alignment graphic structure is located in the scribe lane region.
[0016] In some embodiments, the test graphic structure includes a first lithography pattern group, a first reference pattern group, a second lithography pattern group, and a second reference pattern group sequentially arranged along the circumferential direction of the rotation center. When the mask is in the initial position, the regions corresponding to the first lithography pattern group, the first reference pattern group, the second lithography pattern group, and the second reference pattern group on the wafer are defined as the first quadrant region, the second quadrant region, the third quadrant region, and the fourth quadrant region respectively. Among them,
[0017] The first reference pattern group and the second reference pattern group are centrosymmetric structures;
[0018] When the first set of etched pattern groups and the second set of etched pattern groups are rotated around the rotation center to the second quadrant area or the fourth quadrant area respectively, the marks mapped by the first set of etched pattern groups and the second set of etched pattern groups on the wafer are in a mutually offset layout and neither of them coincides with the marks mapped by the first reference pattern group and the second reference pattern group on the wafer.
[0019] In some embodiments, a method for measuring overlay error is provided, including the following steps:
[0020] Provide a mask as described in any of the foregoing embodiments;
[0021] After placing the mask at the initial position, obtain the reference layer marks;
[0022] After placing the mask at the first position, obtain the first overlay layer marks, where the first position is obtained by rotating the initial position forward by 90°;
[0023] After placing the mask at the second position, obtain the second overlay layer marks, where the second position is obtained by rotating the position backward by 90°;
[0024] Measure the reference layer marks, the first overlay layer marks, and the second overlay layer marks to obtain the overlay error.
[0025] In some embodiments, the step of obtaining the reference layer marks after placing the mask at the initial position includes:
[0026] Place the wafer coated with photoresist on the wafer stage;
[0027] Place the mask at the initial position of the mask stage;
[0028] Perform mask alignment, then expose and develop;
[0029] And / or, the step of obtaining the first overlay layer marks after placing the mask at the first position includes:
[0030] Remove the mask from the mask stage and then place the mask at the first position;
[0031] Remove the wafer with the reference mark layer from the wafer stage and then load the wafer in place;
[0032] Perform mask alignment and wafer alignment, then expose and develop;
[0033] And / or, the step of obtaining the second overlay layer marks after placing the mask at the second position includes:
[0034] Remove the mask from the mask stage and then place the mask at the second position;
[0035] After removing the wafer with the fiducial layer mark and the first set of layer marks from the wafer stage, load the wafer in-situ;
[0036] After performing mask alignment and wafer alignment, expose and develop.
[0037] In some embodiments, measuring the fiducial layer mark, the first set of layer marks, and the second set of layer marks to obtain the overlay error includes:
[0038] Obtain a first alignment feature and a second alignment feature, where the first alignment feature is the information feature formed by the alignment pattern structure in the first set of layer marks, and the second alignment feature is the information feature formed by the alignment pattern structure in the second set of layer marks;
[0039] Calculate the rotation error based on the first alignment feature and the second alignment feature.
[0040] In the reticle provided by the embodiments of the present application, the alignment pattern structure can not only be used to perform mask alignment, but also be used to measure other errors concerned in the exposure process, such as rotation error, step and repeat accuracy, and scaling error. By cleverly designing the alignment pattern structure around the test pattern structure, the rotation radius of the alignment pattern structure is greater than that of the test pattern structure. Therefore, during the rotation of the reticle around the rotation center, the displacement of the alignment pattern structure is more significant, making the rotation error of the alignment pattern structure easier to observe and correct, and further making the rotation error calculated through the overlay alignment marks corresponding to the alignment pattern structure more accurate. Description of the Drawings
[0041] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0042] Figure 1 is a schematic structural diagram of a reticle in some embodiments of the present application;
[0043] Figure 2 is Figure 1 a schematic diagram of the overlay marks formed by the reticle on the wafer in the embodiment;
[0044] Figure 3 is a schematic structural diagram of a reticle in another embodiment of the present application;
[0045] Figure 4 is Figure 3 a schematic diagram of the overlay marks formed by the reticle on the wafer in the embodiment;
[0046] Figure 5 is a schematic structural diagram of a photomask in another embodiment of the present application;
[0047] Figure 6 is Figure 5 a schematic diagram of an alignment mark formed by the photomask on the wafer in the embodiment;
[0048] Figure 7 is a schematic flowchart of a method for measuring alignment error in some embodiments of the present application;
[0049] Figure 8 is Figure 7 a refined flowchart of step S200 in the embodiment;
[0050] Figure 9 is Figure 7 a refined flowchart of step S300 in the embodiment;
[0051] Figure 10 is Figure 7 a refined flowchart of step S400 in the embodiment. Detailed implementation manners
[0052] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be specifically noted that the following embodiments are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only partial embodiments of the present application rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present application.
[0053] The terms "first", "second", and "third" in the embodiments of the present application are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically and clearly defined. All directional indications (such as up, down, left, right, front, back...) in the embodiments of the present application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. The terms "include" and "have" and any variations thereof in the embodiments of the present application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or components inherent to these processes, methods, products, or devices.
[0054] As used herein, the mention of "embodiment" means that the specific features, structures or characteristics described in connection with the embodiments may be included in at least one embodiment of the present application. The phrase appears at various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein may be combined with other embodiments.
[0055] Please refer to Figure 1 and Figure 2 , Figure 1 which is a schematic structural diagram of a mask in some embodiments of the present application, Figure 2 is Figure 1 a schematic diagram of the alignment marks formed by the mask on the wafer in the embodiment.
[0056] An embodiment of the present application provides a mask 100, which includes a test pattern structure 10 provided in the middle area 101 of the mask 100 and an alignment pattern structure 20 provided on the outer periphery of the test pattern structure 10. The test pattern structure 10 is used to form alignment marks on the wafer 200, and the alignment pattern structure 20 is used to perform the alignment of the mask 100.
[0057] It can be understood that a reference fiducial mark is fixed on the mask stage of the lithography machine as an absolute coordinate system for position calibration. The alignment pattern structure 20 on the mask 100 can correspond to the reference fiducial mark on the mask stage to perform mask alignment. Among them, the center of the mask 100 is defined as the rotation center 103. The alignment pattern structure 20 includes two first alignment marks 21, and the two first alignment marks 21 are respectively located on the opposite sides of the test pattern structure 10. The straight line where the two first alignment marks 21 are located is parallel to and does not coincide with the first center line, and the first center line is a reference line passing through the rotation center 103 in the plane of the mask 100.
[0058] Please refer to Figure 2 , Figure 2 where the purple marks represent the reference layer marks 205, the green marks represent the first alignment layer marks 206, and the blue marks represent the second alignment layer marks 207. In the present application, the mask 100 can be rotated relative to the wafer 200 around the rotation center 103 to form different alignment marks on the wafer 200, and these marks are subsequently used to measure the alignment error of the lithography machine. In this embodiment, the positive direction is the counterclockwise direction ( Figure 2in the R direction), and the reverse direction is the clockwise direction. The specific operations are as follows: First, place the mask 100 at the initial position of the mask stage to obtain the reference layer mark 205 on the wafer 200; subsequently, move the mask 100 to the first position to obtain the first set of layer marks 206 on the wafer 200, and this first position is obtained by rotating the mask 100 90 degrees forward from the initial position; then, adjust the position of the mask 100 again and place it at the second position to obtain the second set of layer marks 207 on the wafer 200, and this second position is obtained by rotating the mask 100 90 degrees in the reverse direction from the initial position.
[0059] Taking the position corresponding to the rotation center 103 on the wafer 200 as the origin, establish a rectangular coordinate system. In this coordinate system, the first center line can be set to be parallel to the X direction. In this way, any alignment mark corresponding to a first alignment mark 21 in the first set of layer marks 206 and the alignment mark corresponding to another first alignment mark 21 in the second set of layer marks 207 will be symmetrically arranged with the Y axis as the axis of symmetry.
[0060] Based on the method for forming overlay marks on the wafer 200 in the present application, the alignment pattern structure 20 on the mask 100 in the present application can not only cooperate with the reference marks on the mask stage to perform mask alignment, but also calculate other errors concerned in the exposure process such as rotation error, step stitching accuracy, and scaling error through the symmetric marks corresponding to the first set of layer marks 206 and the second set of layer marks 207. Since the alignment pattern structure 20 is cleverly designed on the periphery of the test pattern structure 10, the rotation radius of the alignment pattern structure 20 is larger than that of the test pattern structure 10. Therefore, during the rotation of the mask 100 around the rotation center 103, the displacement of the alignment pattern structure 20 is more significant, making the rotation error of the alignment pattern structure 20 easier to observe and correct, and further making the rotation error calculated through the overlay alignment marks corresponding to the alignment pattern structure 20 more accurate.
[0061] In some embodiments, the alignment pattern structure 20 further includes two second alignment marks 22, and the two second alignment marks 22 are respectively located on opposite sides of the test pattern structure 10. The straight line where the two second alignment marks 22 are located is parallel to and does not coincide with the second center line, and the second center line is a reference straight line passing through the rotation center 103 and perpendicular to the first center line in the plane of the mask 100. Specifically, the second center line can be set to be parallel to the Y direction. Any alignment mark corresponding to a second alignment mark 22 in the first set of layer marks 206 and the alignment mark corresponding to another second alignment mark 22 in the second set of layer marks 207 will be symmetrically arranged with the X axis as the axis of symmetry.
[0062] By further providing a second alignment mark 22, the second alignment mark 22 can cooperate with the first alignment mark 21 to perform mask alignment, improving the mask alignment accuracy. Meanwhile, among the first set of layer marks 206 and the second set of layer marks 207, the alignment marks corresponding to the first alignment mark 21 are symmetrically arranged with respect to the Y axis, and the alignment marks corresponding to the second alignment mark 22 are symmetrically arranged with respect to the X axis. The extending directions of the first alignment mark 21 and the second alignment mark 22 are different, enabling the measurement of alignment marks at multiple different positions and measurement directions, more comprehensively calculating the rotation error, and thus improving the measurement accuracy of the overlay error.
[0063] The distance from the end of the second alignment mark 22 close to the second center line to the second center line is greater than the distance from the end of the first alignment mark 21 far from the first center line to the first center line; or, the distance from the end of the first alignment mark 21 close to the first center line to the first center line is greater than the distance from the end of the second alignment mark 22 far from the second center line to the second center line. In this embodiment, by restricting the positions of the first alignment mark 21 and the second alignment mark 22, it is ensured that among the formed reference layer marks 205, the first set of layer marks 206, and the second set of layer marks 207, the alignment marks corresponding to the first alignment mark 21 and the second alignment mark 22 on the wafer 200 do not interfere with each other, thereby ensuring the error measurement accuracy.
[0064] In some embodiments, the first alignment mark 21 includes a plurality of strip-shaped patterns parallel to the first center line. That is, the first alignment mark 21 is in a grid shape, and the corresponding grid marks formed by the first alignment mark 21 in the reference layer mark 205, the first set of layer marks 206, and the second set of layer marks 207 respectively. The grid marks can optimize the penetration of optical or electron beam signals by adjusting the line width / spacing in different material layers, ensuring the alignment consistency of multi-layer lithography.
[0065] In some embodiments, the second alignment mark 22 includes a plurality of strip-shaped patterns parallel to the second center line.
[0066] Please refer to Figure 3 and Figure 4 , Figure 3 is a schematic structural diagram of a mask in another embodiment of the present application, Figure 4 is Figure 3 a schematic diagram of the overlay marks formed by the mask on the wafer in the embodiment. In some embodiments, multiple groups of the first alignment mark 21 can be provided in pairs, and the multiple groups of the first alignment mark 21 are offset along the first direction. Similarly, multiple groups of the second alignment mark 22 can also be provided in pairs, and the multiple groups of the second alignment mark 22 are offset along the second direction. By increasing the number of the first alignment mark 21 and the second alignment mark 22, the amount of effective information extraction in the acquisition of the alignment mark image can be increased, thereby further improving the measurement accuracy of the overlay error.
[0067] Please refer to Figure 5 and Figure 6 , Figure 5 which is a schematic structural diagram of a reticle in another embodiment of the present application, Figure 6 and Figure 5 is a schematic diagram of the alignment marks formed by the reticle on the wafer in the embodiment. In some embodiments, the first alignment mark 21 and the second alignment mark 22 can also be rectangles. In other embodiments, the first alignment mark 21 and the second alignment mark 22 can also be special-shaped structures such as crosshairs and box-in-boxes.
[0068] In some embodiments, the distance from each first alignment mark 21 to the rotation center 103 is greater than 5 mm; and / or, the distance from each second alignment mark 22 to the rotation center 103 is greater than 5 mm. As the distance between the first alignment mark 21 and the second alignment mark 22 from the rotation center 103 increases, when the reticle 100 rotates around the rotation center 103, the displacement of the first alignment mark 21 relative to the second alignment mark 22 will be more obvious. By restricting the distance between the first alignment mark 21 and / or the second alignment mark 22 and the rotation center 103, it can be ensured that when calculating the rotation error using the alignment marks corresponding to these alignment marks, the result is more accurate.
[0069] Please refer to Figure 1 , in some embodiments, the graphic structures of the first alignment mark 21 and the second alignment mark 22 are the same and the length is d. The distance from the center of the first alignment mark 21 to the first center line is d, and the distance from the second alignment mark 22 to the second center line is 3d; or, the distance from the center of the first alignment mark 21 to the first center line is 3d, and the distance from the second alignment mark 22 to the second center line is d. In this way, it can be ensured that during the process of detecting the overlay error by rotating the reticle 100 multiple times, the respective marks corresponding to the alignment graphic structure 20 can just be staggered, that is, the alignment marks corresponding to the first alignment mark 21 and the second alignment mark 22 in the reference layer mark 205, the first overlay layer mark 206, and the second overlay layer mark 207 do not interfere with each other, so as to be able to measure each alignment mark more accurately.
[0070] Please continue to refer to Figure 1 , in some embodiments, the reticle 100 includes a scribe lane region 102 provided on the outer periphery of the intermediate region 101. The intermediate region 101 is a rectangular region. One of the first center line and the second center line extends along the width direction of the intermediate region 101, and the other extends along the length direction of the intermediate region 101. The scribe lane region 102 is an annular rectangular region, and the alignment graphic structure 20 is located in the scribe lane region 102. The scribe lane region 102 corresponds to the interval region between adjacent chips on the wafer 200 and is used to divide the wafer 200 into individual chips by mechanical cutting or laser cutting after manufacturing.
[0071] Please refer to Figure 1 and Figure 2 In some embodiments, the overlay pattern structure 10 includes a first set of lithography pattern groups 11, a first reference pattern group 12, a second set of lithography pattern groups 13, and a second reference pattern group 14 that are sequentially arranged circumferentially along the rotation center 103. When the mask 100 is in the initial position, the regions corresponding to the first set of lithography pattern groups 11, the first reference pattern group 12, the second set of lithography pattern groups 13, and the second reference pattern group 14 on the wafer 200 are the first quadrant region 201, the second quadrant region 202, the third quadrant region 203, and the fourth quadrant region 204 in sequence. Among them, the first reference pattern group 12 and the second reference pattern group 14 are centrosymmetric structures; when the first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 rotate around the rotation center 103 to the second quadrant region 202 or the fourth quadrant region 204 respectively, the marks mapped by the first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 on the wafer 200 are in a mutually offset layout and do not coincide with the marks mapped by the first reference pattern group 12 and the second reference pattern group 14 on the wafer 200.
[0072] It should be noted that the first set of lithography pattern groups 11, the second set of lithography pattern groups 13, the first reference pattern group 12, and the second reference pattern group 14 are fixedly formed in the middle region 101 of the mask 100. The first quadrant region 201, the second quadrant region 202, the third quadrant region 203, and the fourth quadrant region 204 divided on the wafer 200 are divided according to the reference position of the mask 100. Therefore, depending on the position of the mask 100, the overlay pattern structures 10 corresponding to each quadrant region can be different. The first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 rotating around the rotation center 103 to the second quadrant region 202 respectively means that the first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 rotate to the positions corresponding to the second quadrant region 202 of the wafer 200 successively. Similarly, the first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 rotating around the rotation center 103 to the fourth quadrant region 204 respectively means that the first set of lithography pattern groups 11 and the second set of lithography pattern groups 13 rotate to the positions corresponding to the fourth quadrant region 204 of the wafer 200 successively.
[0073] Please refer to Figure 2 and Figure 7 , Figure 7 is a schematic flowchart of an overlay error measurement method in some embodiments of the present application. In some embodiments, an overlay error measurement method is provided, including the following steps:
[0074] S100. Provide the mask 100 as described in any of the foregoing embodiments;
[0075] S200. After placing the reticle 100 at the initial position, obtain the reference layer mark 205;
[0076] S300. After placing the reticle 100 at the first position, obtain the first set of etched layer marks 206. The first position is obtained by rotating the initial position 90° clockwise;
[0077] S400. After placing the reticle 100 at the second position, obtain the second set of etched layer marks 207. The second position is obtained by rotating the first position 90° counterclockwise;
[0078] S500. Measure the reference layer mark 205, the first set of etched layer marks 206, and the second set of etched layer marks 207 to obtain the overlay error.
[0079] In this embodiment, an imaging inspection module on the lithography machine or a third-party detection device such as a feature measurement machine can be used to measure, analyze, and statistically process the reference layer mark 205, the first set of etched layer marks 206, and the second set of etched layer marks 207, thereby achieving the measurement of the overlay accuracy. In the overlay error measurement method of this embodiment, only by rotating a reticle 100 relative to the wafer 200, non-overlapping reference layer marks 205, first set of etched layer marks 206, and second set of etched layer marks 207 can be formed in the second quadrant region 202 and the fourth quadrant region 204 of the wafer 200.
[0080] Among them, the development process batches of the first set of etched layer marks 206 and the second set of etched layer marks 207 are the same. In this way, when calculating the overlay error between the first set of etched layer marks 206 and the second set of etched layer marks 207, the influence brought by process differences can be excluded. The overlay error between the reference layer mark 205 and the first set of etched layer marks 206 and / or the overlay error between the reference layer mark 205 and the second set of etched layer marks 207 can be measured together as the overlay error of the etched layer relative to the reference layer, and the statistics of its distribution can help analyze the sources of overlay errors.
[0081] Please refer to Figure 8 , Figure 8 is Figure 7 The schematic flow chart of the refinement of step S200 in the embodiment. In some embodiments, after placing the reticle 100 at the initial position, obtaining the reference layer mark 205 includes:
[0082] S201. Place the wafer 200 coated with photoresist on the wafer stage;
[0083] S202. Place the reticle 100 at the initial position on the reticle stage;
[0084] S203. After performing mask alignment, expose and develop.
[0085] Please refer to Figure 9 ,Figure 9 Yes Figure 7 Figure 7 is a schematic flow chart showing the refinement of step S300 in the embodiment. In some embodiments, obtaining the first set of layer alignment marks 206 after placing the mask 100 at the first position includes:
[0086] S301: Remove the mask 100 from the mask stage and then place the mask 100 at the first position;
[0087] S302: Remove the wafer 200 with the fiducial mark layer from the wafer stage and then load the wafer 200 in situ;
[0088] S303: Perform mask alignment and wafer 200 alignment, then expose and develop;
[0089] Please refer to Figure 10 , Figure 10 Yes Figure 7 Figure 7 is a schematic flow chart showing the refinement of step S400 in the embodiment. In some embodiments, obtaining the second set of layer alignment marks 207 after placing the mask 100 at the second position includes:
[0090] S401: Remove the mask 100 from the mask stage and then place the mask 100 at the second position;
[0091] S402: Remove the wafer 200 with the fiducial layer mark 205 and the first set of layer alignment marks 206 from the wafer stage and then load the wafer 200 in situ;
[0092] S403: Perform mask alignment and wafer 200 alignment, then expose and develop.
[0093] It should be noted that in this embodiment, the wafer undergoes two development processes. The first is to develop the fiducial layer mark 205 in step S203, and the second is to develop the first set of layer alignment marks 206 and the second set of layer alignment marks 207 simultaneously in step S403. This can minimize the time interval between the formation processes of the first set of layer alignment marks 206 and the second set of layer alignment marks 207 to reduce the effect of the slow change of the photoresist over time, and it does not come into contact with any solution, such as development or cleaning, during the process to ensure the consistency of the active state of the photoresist. In this way, it can be ensured that the formation processes of the first set of layer alignment marks 206 and the second set of layer alignment marks 207 are the same, thereby improving the accuracy of the overlay error measurement under the same process. At the same time, the overlay error distribution of the first set of layer alignment marks 206 and / or the second set of layer alignment marks 207 relative to the fiducial layer mark 205 can be measured and statistically analyzed to analyze the source of the overlay error.
[0094] By removing the reticle 100, rotating it appropriately and reinstalling it on the reticle stage, a new reticle 100 loading can be simulated. Similarly, by removing the wafer 200 and reloading it in place, a new wafer 200 loading can be simulated. The positions between the reticle 100 and the reticle stage and between the wafer 200 and the wafer stage have changed, and it re-enters the pre-alignment stage. In this way, all systematic errors introduced during the reticle 100 transfer and pre-alignment processes will be reset, thus avoiding the omission of error checks.
[0095] The overlay error measurement method in this application does not need to cooperate with the etching or growth process. The detection of overlay error can be completed only by using exposure and development, imaging inspection, and the analysis and statistics of overlay results.
[0096] In some embodiments, measuring the fiducial layer mark 205, the first overlay layer mark 206, and the second overlay layer mark 207 to obtain the overlay error includes:
[0097] Obtaining a first alignment feature and a second alignment feature, where the first alignment feature is the information feature formed by the alignment pattern structure 20 in the first overlay layer mark 206, and the second alignment feature is the information feature formed by the alignment pattern structure 20 in the second overlay layer mark 207;
[0098] Calculating the rotation error based on the first alignment feature and the second alignment feature.
[0099] In the overlay error measurement method of this embodiment, since the alignment pattern structure 20 is cleverly designed on the periphery of the test pattern structure 10, the rotation radius of the alignment pattern structure 20 is larger than that of the test pattern structure 10. Therefore, during the rotation of the reticle 100 around the rotation center 103, the displacement of the alignment pattern structure 20 is more significant, making the rotation error of the alignment pattern structure 20 easier to observe and correct, and further making the rotation error calculated through the overlay alignment marks corresponding to the alignment pattern structure 20 more accurate.
[0100] The above are only some embodiments of this application, and thus do not limit the protection scope of this application. Any equivalent device or equivalent process transformation made using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.
Claims
1. A photomask, characterized in that, It includes a test pattern structure provided in the middle area of the reticle and an alignment pattern structure provided on the outer periphery of the test pattern structure. The test pattern structure is used to form an overlay mark on the wafer, and the alignment pattern structure is used to perform reticle alignment. Wherein, the center of the reticle is defined as the rotation center. The alignment pattern structure includes two first alignment marks, and the two first alignment marks are respectively located on the opposite sides of the test pattern structure. The straight line where the two first alignment marks are located is parallel to and does not coincide with the first center line, and the first center line is a reference line passing through the rotation center in the plane of the reticle.
2. The mask according to claim 1, characterized in that, The alignment pattern structure further includes two second alignment marks, and the two second alignment marks are respectively located on the opposite sides of the test pattern structure. The straight line where the two second alignment marks are located is parallel to and does not coincide with the second center line, and the second center line is a reference line passing through the rotation center in the plane of the reticle and perpendicular to the first center line. Wherein, The distance from the end of the second alignment mark close to the second center line to the second center line is greater than the distance from the end of the first alignment mark far from the first center line to the first center line; Or, the distance from the end of the first alignment mark close to the first center line to the first center line is greater than the distance from the end of the second alignment mark far from the second center line to the second center line.
3. The mask according to claim 2, wherein The first alignment mark includes a plurality of strip-shaped patterns parallel to the first center line; And / or, the second alignment mark includes a plurality of strip-shaped patterns parallel to the second center line.
4. The reticle according to claim 2, wherein The distance from each first alignment mark to the rotation center is greater than 5 mm; And / or, the distance from each second alignment mark to the rotation center is greater than 5 mm.
5. The reticle according to any one of claims 2-4, characterized in that, The graphic structures of the first alignment mark and the second alignment mark are the same and the length is d. The distance from the center of the first alignment mark to the first center line is d, and the distance from the second alignment mark to the second center line is 3d; Or, the distance from the center of the first alignment mark to the first center line is 3d, and the distance from the second alignment mark to the second center line is d.
6. The mask according to any one of claims 2-4, characterized in that, The reticle includes a scribe lane area provided on the outer periphery of the middle area. The middle area is a rectangular area. One of the first center line and the second center line extends along the width direction of the middle area, and the other extends along the length direction of the middle area. The scribe lane area is an annular rectangular area, and the alignment pattern structure is located in the scribe lane area.
7. The photomask according to any one of claims 2-4, characterized in that, The test pattern structure includes a first overlay pattern group, a first reference pattern group, a second overlay pattern group, and a second reference pattern group arranged in sequence along the circumferential direction of the rotation center. It is defined that when the reticle is in the initial position, the areas corresponding to the first overlay pattern group, the first reference pattern group, the second overlay pattern group, and the second reference pattern group on the wafer are the first quadrant area, the second quadrant area, the third quadrant area, and the fourth quadrant area in sequence. Wherein, The first reference pattern group and the second reference pattern group are centrosymmetric structures; When the first set of pattern groups and the second set of pattern groups rotate around the rotation center to the second quadrant area or the fourth quadrant area respectively, the marks mapped by the first set of pattern groups and the second set of pattern groups on the wafer are in a mutually offset layout and neither of them coincides with the marks mapped by the first reference pattern group and the second reference pattern group on the wafer.
8. A method for measuring overlay error, characterized in that, Including the following steps: Provide a mask as described in any one of claims 1-7; After placing the mask in the initial position, obtain the reference layer marks; After placing the mask in the first position, obtain the first set of etched layer marks, where the first position is obtained by rotating the initial position forward by 90°; After placing the mask in the second position, obtain the second set of etched layer marks, where the second position is obtained by rotating the position backward by 90°; Measure the reference layer marks, the first set of etched layer marks, and the second set of etched layer marks to obtain the overlay error.
9. The overlay error measurement method according to claim 8, characterized in that The obtaining the reference layer marks after placing the mask in the initial position includes: Place the wafer coated with photoresist on the wafer stage; Place the mask in the initial position on the mask stage; Perform mask alignment, then expose and develop; And / or, the obtaining the first set of etched layer marks after placing the mask in the first position includes: Remove the mask from the mask stage and then place the mask in the first position; Remove the wafer with the reference mark layer from the wafer stage and then load the wafer in place; Perform mask alignment and wafer alignment, then expose and develop; And / or, the obtaining the second set of etched layer marks after placing the mask in the second position includes: Remove the mask from the mask stage and then place the mask in the second position; Remove the wafer with the reference layer marks and the first set of etched layer marks from the wafer stage and then load the wafer in place; Perform mask alignment and wafer alignment, then expose and develop.
10. The overlay error measurement method according to claim 8, characterized in that, The measuring the reference layer marks, the first set of etched layer marks, and the second set of etched layer marks to obtain the overlay error includes: Obtain a first alignment feature and a second alignment feature, where the first alignment feature is the information feature formed by the alignment pattern structure in the first set of etched layer marks, and the second alignment feature is the information feature formed by the alignment pattern structure in the second set of etched layer marks; Calculate the rotation error based on the first alignment feature and the second alignment feature.