Method, device and equipment for preventing illegal winding of IP pin in N12 design and medium

Abstract

The invention provides an IP pin anti-violation winding method, device, equipment and medium in N12 design, and can automatically generate two blocking areas at an external connection pin of an error report IP, the left and right sections of the front side edge of the external connection pin are blocked by the two blocking areas, and the remaining middle section forms a central wiring section, the length of the left section and the length of the right section are both larger than or equal to 0.02 micrometers, and the width of the center wiring section is the same as that of the wiring, so that the tool can only lead out the wiring from the center wiring section during winding, and external connection pins and the wiring form concentric connection. And the distance between the left edge of the connecting line and the left edge of the pin and the distance between the right edge of the connecting line and the right edge of the pin are both greater than or equal to 0.02 [mu] m, so that violation is avoided, and compared with a manual repair mode in the prior art, the efficiency is greatly improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip design, and particularly relates to a method, device, equipment and medium for preventing IP pin violations in N12 design during routing. Background Art

[0002] In the back-end design of chips, a lot of IPs are used. IP refers to pre-designed functional unit modules, which can be circuit units with various functions, such as processor cores, memory controllers, interface modules, encryption modules, etc. IPs can be provided by third-party suppliers or developed by the company's internal design team. Using pre-designed IPs can significantly reduce development time and costs, and improve the reliability and performance of the design, because these IPs usually have been fully verified and optimized.

[0003] IP is a black box to designers, and its internal logic is invisible. It only provides some interfaces (pins) that need to be connected to the outside. The size and position of the pins are provided by the IP provider. Designers only need to connect the pins to the external metal connecting lines (nets). To avoid DRC violations of Mxe.L.5, it is required that the distance between the left edge of the connecting line and the left edge of the pin and the distance between the right edge of the connecting line and the right edge of the pin are both greater than or equal to 0.02um. In the implementation process, it is found that if the pin is wide, automatic routing can easily meet the above requirements. If the pin is narrow, such as the pin width is 0.08um and the wiring width is 0.04um, then the connecting line needs to be concentrically connected to the pin to meet the above requirements. However, the existing automatic routing tools are difficult to ensure concentric connection between the two, resulting in a large number of DRC violations. These violations will not be reported by the automatic routing tools, resulting in a lot of Mxe.L.5 drc error reports being found only after the final gdsmerge (gdsmerge is used to integrate multiple GDS files into a complete layout in the semiconductor design process).

[0004] In the case of few IPs, when Mxe.L.5 drc error reports occur, the problem is generally solved by manual repair (manually moving the metal connecting line and setting its attribute to fixed), so that the tool will not move it. However, when it comes to scenarios with a large number of IPs, the manual repair workload is very large. Summary of the Invention

[0005] Based on this, in view of the above technical problems, a method, device, equipment and medium for preventing IP pin violations in N12 design during routing are provided.

[0006] The technical solution adopted by the present invention is as follows:

[0007] As a first aspect of the present invention, there is provided a method for preventing IP pin wiring violations in N12 design, characterized in that the method is based on a chip design tool and includes:

[0008] S101. Determine the reported IP, where the reported IP refers to the IP that has a Mxe.L.5 DRC violation;

[0009] S102. Use the y-direction center line of the external connection pins of the reported IP as the axis of symmetry to generate two axially symmetric rectangular blocking regions, which are used to block at least the left and right segments of the front side of the external connection pins and form a central wiring segment in the remaining middle segment to constrain the wiring of the reported IP to be led out from its central wiring segment during automatic wiring;

[0010] Wherein, the width of the central wiring segment is the same as the width of the wiring, and its y-direction center line coincides with the y-direction center line of the external connection pins. The y direction refers to the length direction of the external connection pins, and the lengths of the left and right segments are both greater than or equal to 0.02 um;

[0011] S103. Start automatic wiring.

[0012] As a second aspect of the present invention, there is provided a device for preventing IP pin wiring violations in N12 design, characterized in that the device is based on a chip design tool and includes:

[0013] A first module for determining the reported IP, where the reported IP refers to the IP that has a Mxe.L.5 DRC violation;

[0014] A second module for using the y-direction center line of the external connection pins of the reported IP as the axis of symmetry to generate two axially symmetric rectangular blocking regions, which are used to block at least the left and right segments of the front side of the external connection pins and form a central wiring segment in the remaining middle segment to constrain the wiring of the reported IP to be led out from its central wiring segment during automatic wiring;

[0015] Wherein, the width of the central wiring segment is the same as the width of the wiring, and its y-direction center line coincides with the y-direction center line of the external connection pins. The y direction refers to the length direction of the external connection pins, and the lengths of the left and right segments are both greater than or equal to 0.02 um;

[0016] A third module for starting automatic wiring.

[0017] As a third aspect of the present invention, there is provided an electronic device, characterized in that it includes a storage module, and the storage module includes instructions loaded and executed by a processor. When the instructions are executed, the processor executes the method for preventing IP pin wiring violations in N12 design according to the first aspect above.

[0018] As a fourth aspect of the present invention, there is provided a computer-readable storage medium storing one or more programs, characterized in that when the one or more programs are executed by a processor, an IP pin anti-violation routing method in a N12 design as described in the first aspect above is implemented.

[0019] The present invention can automatically generate two blocking regions at the external connection pins of the reported IP. The two blocking regions block the left and right segments of the front side of the external connection pins, leaving the remaining middle segment as the central wiring segment. Among them, the lengths of the left and right segments are both greater than or equal to 0.02um, and the width of the central wiring segment is the same as the width of the wiring. In this way, when the tool routes the wire, it can only lead out the wire from the central wiring segment, making the external connection pin and the wire form a concentric connection, and the distance between the left edge of the connecting wire and the left edge of the pin and the distance between the right edge of the connecting wire and the right edge of the pin both satisfy being greater than or equal to 0.02um, thereby avoiding violations. Compared with the manual repair method in the prior art, the efficiency is greatly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be described in detail below in conjunction with the drawings and specific embodiments:

[0021] Figure 1 It is a flowchart of an IP pin anti-violation routing method in a N12 design provided by an embodiment of the present invention;

[0022] Figure 2 It is a schematic diagram of an IP pin anti-violation routing device in a N12 design provided by an embodiment of the present invention;

[0023] Figure 3 It is a schematic diagram of an electronic device provided by an embodiment of the present invention;

[0024] Figure 4 It is a schematic diagram of an external connection pin provided by an embodiment of the present invention;

[0025] Figure 5 It is an exemplary schematic diagram of a first form of a blocking region provided by an embodiment of the present invention;

[0026] Figure 6 (a) and Figure 6 (b) are two exemplary schematic diagrams of a second form of a blocking region provided by an embodiment of the present invention;

[0027] Figure 7 It is an exemplary schematic diagram of a third form of a blocking region provided by an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The embodiments of the present invention will be described below in conjunction with the accompanying drawings of the specification. It should be noted that the embodiments involved in this specification are not exhaustive and do not represent the only embodiments of the present invention. The following corresponding embodiments are only for clearly explaining the inventive content of the present invention patent and do not limit its embodiments. For those of ordinary skill in the art, different forms of changes and modifications can be made on the basis of the description of this embodiment. Any changes or modifications that belong to the technical concept and inventive content of the present invention and are obvious are also within the protection scope of the present invention.

[0029] The embodiment of the present application provides a method for preventing IP pin violation routing in N12 design. Based on a chip design tool (such as IC Compiler II), when performing N12 design, relevant files of N12 need to be imported. In order to reuse the IP of N16, relevant files of the IP of N16 also need to be imported into the pr tool (automatic routing tool). The relevant files include design files such as netlist, LEF (Library Exchange Format), Logical libraries, SDC, and DEF.

[0030] Taking the IC Compiler II tool as an example, the method of the embodiment of the present application is implemented through a TCL script, as Figure 1 shown, and its specific process is as follows:

[0031] S101. Determine the reported IP.

[0032] Among them, the reported IP refers to the IP that has a Mxe.L.5 DRC violation. Specifically, after placing IP and other hardmacros (hard cores) in the FP stage, ICC2 performs multiple rounds of automatic routing through the pr tool. When the drc check is run through the calibre tool (in the signoff check drc stage after gdsmerge), the reported IP is found. Then, the script grabs it by the name of the IP. For example, it can be implemented using the get_cells xxx command of the ICC2 (IC Compiler II) tool, and xxx represents the hierarchical name of the IP in the design.

[0033] S102. Taking the center line C of the y direction of the external connection pin 101 of the reported IP as the axis of symmetry, generate two axially symmetric rectangular routing blockages 102, which are used to block at least the left and right segments 101a-1 of the front side 101a of the external connection pin 101, and form a central wiring segment 101a-2 in the remaining middle segment, so as to constrain the wiring of the reported IP to lead out from its central wiring segment 101a-2 during automatic routing. See Figure 4 .

[0034] Among them, the function of the blocking area is to prevent the wire winding tool from wiring in the area covered by the blocking area. The width of the central wiring segment 101a-2 is the same as the width of the wiring (determined by the process), and its center line in the y direction coincides with the center line in the y direction of the external connection pin 101. The y direction refers to the length direction of the external connection pin 101. The lengths of the left segment and the right segment are both greater than or equal to 0.02um. In this way, when the wiring leads out from the central wiring segment 101a-2, the external connection pin 101 and the wiring can form a concentric connection, and the distance between the left edge of the connection line and the left edge of the pin and the distance between the right edge of the connection line and the right edge of the pin both meet the requirement of being greater than or equal to 0.02um.

[0035] It should be noted that the front side 101a of the external connection pin 101 is the side edge for external wiring.

[0036] The blocking area 102 can adopt three forms, which will be described separately below.

[0037] The first form: Two blocking areas 102 completely cover the left and right sides of the external connection pin 101, and the inner distance D between them is equal to the width of the central wiring segment 101a-2. See Figure 5 , and this form is more beautiful.

[0038] The second form: Two blocking areas 102 only completely cover the left and right sides of the external connection pin 101 in the x direction. The inner distance D between them is equal to the width of the central wiring segment 101a-2. The front side edges 102a of the two blocking areas 102 respectively coincide with the left and right segments 101a-1 of the front side 101a of the external connection pin 101 or extend beyond the front side 101a of the external connection pin 101 in the y direction. Among them, the x direction refers to the width direction of the external connection pin 101. See Figure 6 (a) and (b).

[0039] The third form: The rear side edges 102b of the two blocking areas 102 respectively coincide with the left and right segments 101a-1 of the front side 101a of the external connection pin 101. The inner distance D between them is equal to the width of the central wiring segment 101a-2. The lengths of the rear side edges 102b of the two blocking areas 102 are greater than or equal to the length of the left or right segment of the front side 101a of the external connection pin 101. See Figure 7 .

[0040] Taking the first form as an example, assuming that the external connection pin 101 of the IP is an M5 pin with a width of 0.08um, the width of the wiring for automatic wire winding is 0.04um, and the width of the blocking area 102 is 0.06um, the specific process of step S102 is as follows:

[0041] 1. Capture the boundary box corresponding to the M5 pin of the IP reporting the error.

[0042] In this embodiment, the script is implemented by the get_terminals-of_objects[get_pins-of_objects[get_cells xxx]-filter "layer_name==M5"] command of ICC2.

[0043] Among them, the IP external connection pins include signal pins and power pins. Usually, the signal pin will have an error, which is generally at a low level, such as M5.

[0044] 2. Use the lower left corner coordinates of the bounding box of the captured pin to move 0.04um downward and to the left respectively to obtain the lower left corner coordinates of the blocking area to be covered on the left side of the pin.

[0045] 3. Using the coordinates of the upper left corner of the bounding box of the captured pin, move 0.04um and 0.02um upward and rightward respectively to obtain the coordinates of the upper right corner of the blocking area to be covered on the left side of the pin.

[0046] 4. Use the lower right corner coordinates of the bounding box of the captured pin to move 0.04um downward and to the right respectively to obtain the lower right corner coordinates of the blocking area to be covered on the right side of the pin.

[0047] 5. Using the upper right corner coordinates of the bounding box of the captured pin, move 0.04um and 0.02um upward and left respectively to obtain the upper left corner coordinates of the blocking area to be covered on the right side of the pin.

[0048] 6. Using the lower left corner coordinates and upper right corner coordinates of the blocking area to be covered on the left and the lower right corner coordinates and upper left corner coordinates of the blocking area to be covered on the right, the script generates the blocking area to be covered on the left and the blocking area to be covered on the right of the pin through the create_routing_blockage command.

[0049] 7. Repeat 1-6 above to generate the blocked area to be covered on the left and the blocked area to be covered on the right for all the pins of the error-reporting IP.

[0050] S103, start automatic winding.

[0051] Specifically, the script automatically routes the wires through the route_eco command of the IC Compiler II tool. For the error IP, two blocking areas are generated at its external connection pins, which can block the left and right segments of the front side of the external connection pins, and make the remaining middle segment the center wiring segment. In this way, the IC Compiler II tool can only lead out the wiring from the center wiring segment when routing.

[0052] As can be seen from the above, an IP pin anti-violation routing method in the N12 design provided by the embodiment of the present application can automatically generate two blocking regions at the external connection pins of the reported IP. The two blocking regions block the left and right segments of the front side of the external connection pins, leaving the remaining middle segment as the central wiring segment. The lengths of the left and right segments are both greater than or equal to 0.02 um, and the width of the central wiring segment is the same as the width of the wiring. In this way, the tool can only draw the wiring from the central wiring segment during routing, so that the external connection pin and the wiring form a concentric connection, and the distance between the left edge of the connection line and the left edge of the pin and the distance between the right edge of the connection line and the right edge of the pin both meet the requirement of being greater than or equal to 0.02 um, thereby avoiding violations. Compared with the manual repair method in the prior art, the efficiency is greatly improved.

[0053] The following will detail an IP pin anti-violation routing device in the N12 design of one or more embodiments of the present invention. Those skilled in the art can understand that these routing devices can all be configured by using commercially available hardware components through the steps taught by this solution. Figure 2 Figure 7 shows an IP pin anti-violation routing device in the N12 design provided by an embodiment of the present invention. This device is based on a chip design tool (such as IC Compiler II), as Figure 2 shown, this routing device includes a first module 11, a second module 12, and a third module 13.

[0054] The first module 11 is used for S101, determining the reported IP.

[0055] Among them, the reported IP refers to the IP that has a Mxe.L.5 DRC violation. Specifically, after placing IP and other hardmacros (hard cores) in the FP stage, ICC2 performs multiple rounds of automatic routing through pr. After the calibre tool runs the drc check (in the signoff check drc stage after gdsmerge), an IP with an error is found. Then, the script grabs it by the name of the IP. For example, it can be implemented by using the get_cells xxx command of the ICC2 (IC Compiler II) tool, where xxx represents the hierarchical name of the IP in the design.

[0056] The second module 12 is used in S102 to generate two axially symmetric routing blockages 102 with the y-direction center line C of the external connection pin 101 of the reported error IP as the axis of symmetry, which are used to block at least the left and right segments 101a-1 of the front side 101a of the external connection pin 101 and form a central wiring segment 101a-2 in the remaining middle segment, so as to constrain the wiring of the reported error IP to lead out from its central wiring segment 101a-2 during automatic wiring. See Figure 4 。

[0057] Among them, the role of the blocking area is to prevent the routing tool from routing in the area covered by the blocked area. The width of the central wiring segment 101a-2 is the same as the width of the wiring (determined by the process), and its y-direction center line coincides with the y-direction center line of the external connection pin 101. The y direction refers to the length direction of the external connection pin 101. The lengths of the left and right segments are both greater than or equal to 0.02um. In this way, when the wiring leads out from the central wiring segment 101a-2, the external connection pin 101 and the wiring can form a concentric connection, and the distance between the left edge of the connection line and the left edge of the pin and the distance between the right edge of the connection line and the right edge of the pin both meet the requirement of being greater than or equal to 0.02um.

[0058] It should be noted that the front side 101a of the external connection pin 101 is the side edge for external wiring.

[0059] The blocking area 102 can adopt three forms, which will be described separately below.

[0060] The first form: The two blocking areas 102 completely cover the left and right sides of the external connection pin 101, and the inner spacing D between them is equal to the width of the central wiring segment 101a-2. See Figure 5 This form is more beautiful.

[0061] The second form: The two blocking areas 102 only completely cover the left and right sides of the external connection pin 101 in the x direction, and the inner spacing D between them is equal to the width of the central wiring segment 101a-2. The front sides 102a of the two blocking areas 102 coincide with the left and right segments 101a-1 of the front side 101a of the external connection pin 101 respectively or extend beyond the front side 101a of the external connection pin 101 in the y direction. Among them, the x direction refers to the width direction of the external connection pin 101. See Figure 6 (a) and (b).

[0062] The third form: The rear sides 102b of the two blocking regions 102 respectively coincide with the left and right segments 101a-1 of the front side 101a of the external connection pin 101. The inner distance D between the two is equal to the width of the central wiring segment 101a-2. The length of the rear sides 102b of the two blocking regions 102 is greater than or equal to the length of the left or right segment of the front side 101a of the external connection pin 101. See Figure 7 .

[0063] Taking the first form as an example, assume that the external connection pin 101 of the IP is an M5 pin, its width is 0.08um, the wiring width of the automatic wire routing is 0.04um, and the width of the blocking region 102 is 0.06um. The specific process of step S102 is as follows:

[0064] 1. Grab the boundary box of the M5 pin corresponding to the reported error IP.

[0065] In this embodiment, the script is implemented by the ICC2 command get_terminals-of_objects[get_pins-of_objects[get_cells xxx]-filter “layer_name==M5”].

[0066] Among them, the external connection pins of the IP include signal pins and power supply pins. Usually, signal pins will report errors, and they generally occur at a low level, such as M5.

[0067] 2. Using the lower left coordinate of the boundary box of the grabbed pin, move 0.04um down and 0.04um to the left respectively to obtain the lower left coordinate of the blocking region to be covered on the left side of the pin.

[0068] 3. Using the upper left coordinate of the boundary box of the grabbed pin, move 0.04um up and 0.02um to the right respectively to obtain the upper right coordinate of the blocking region to be covered on the left side of the pin.

[0069] 4. Using the lower right coordinate of the boundary box of the grabbed pin, move 0.04um down and 0.04um to the right respectively to obtain the lower right coordinate of the blocking region to be covered on the right side of the pin.

[0070] 5. Using the upper right coordinate of the boundary box of the grabbed pin, move 0.04um up and 0.02um to the left respectively to obtain the upper left coordinate of the blocking region to be covered on the right side of the pin.

[0071] 6. Using the lower left corner coordinates and upper right corner coordinates of the blocking area to be covered on the left and the lower right corner coordinates and upper left corner coordinates of the blocking area to be covered on the right, the script generates the blocking area to be covered on the left and the blocking area to be covered on the right of the pin through the create_routing_blockage command.

[0072] 7. Repeat 1-6 above to generate the blocked area to be covered on the left and the blocked area to be covered on the right for all the pins of the error-reporting IP.

[0073] The third module 13 is used for S103, starting automatic winding.

[0074] Specifically, the script automatically routes the wires through the route_eco command of the IC Compiler II tool. For the error IP, two blocking areas are generated at its external connection pins, which can block the left and right segments of the front side of the external connection pins, and make the remaining middle segment the center wiring segment. In this way, the IC Compiler II tool can only lead out the wiring from the center wiring segment when routing.

[0075] In summary, the IP pin anti-violation wiring device in the N12 design provided in the above embodiment can execute the IP pin anti-violation wiring method in the N12 design provided in the above embodiments.

[0076] The same as above concept, Figure 2 The structure of the IP pin anti-violation winding device in the N12 design shown can be implemented as an electronic device. Figure 3 A schematic block diagram of the structure of an electronic device provided by an embodiment of the present invention is shown.

[0077] Exemplarily, the electronic device includes a storage module 21 and a processor 22, the storage module 21 includes instructions loaded and executed by the processor 22, and when the instructions are executed, the processor 22 performs the steps of various exemplary embodiments of the present invention described in the section on the anti-violation winding method in the above-mentioned N12 design in this specification.

[0078] It should be understood that the processor 22 can be a central processing unit (CPU), and the processor 22 can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0079] An embodiment of the present invention also provides a computer-readable storage medium that stores one or more programs. When the one or more programs are executed by a processor, the steps according to various exemplary embodiments of the present invention described in the anti-violation routing method part of the above-mentioned N12 design are implemented.

[0080] Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, and appropriate combinations thereof. In the hardware implementation, the division of the functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component can have multiple functions, or a function or step can be executed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or can be implemented as hardware, or can be implemented as an integrated circuit, such as an application specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include a computer-readable storage medium (or non-transitory medium) and a communication medium (or transitory medium).

[0081] As is known to those of ordinary skill in the art, the term computer-readable storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information such as computer-readable instructions, data structures, program modules, or other data. Computer-readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, as is known to those of ordinary skill in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transmission mechanism, and may include any information delivery medium.

[0082] Exemplarily, the computer-readable storage medium may be an internal storage unit of the electronic device in the foregoing embodiments, such as the hard disk or memory of the electronic device. The computer-readable storage medium may also be an external storage device of the electronic device, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. equipped on the electronic device.

[0083] The electronic devices and computer-readable storage media provided in the foregoing embodiments can automatically generate two blocking regions at the external connection pins of the reported error IP. The two blocking regions block the left and right segments of the front side of the external connection pins, so that the remaining middle segment forms a central wiring segment. The lengths of the left and right segments are both greater than or equal to 0.02 um, and the width of the central wiring segment is the same as the width of the wiring. In this way, when the tool winds the wire, the wire can only be led out from the central wiring segment, so that the external connection pin and the wire form a concentric connection, and the distance between the left edge of the connecting wire and the left edge of the pin and the distance between the right edge of the connecting wire and the right edge of the pin both satisfy being greater than or equal to 0.02 um, thereby avoiding violations. Compared with the manual repair method in the prior art, the efficiency is greatly improved.

[0084] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these changes and modifications.

Claims

1. An IP pin anti-violation routing method in the N12 design, characterized in that This method is based on a chip design tool and includes: S101. Determine the error-reporting IP, where the error-reporting IP refers to the IP that has a Mxe.L.5 DRC violation; S102. Use the y-direction center line of the external connection pins of the error-reporting IP as the axis of symmetry to generate two axially symmetric rectangular blocking regions, which are used to block at least the left and right segments of the front side of the external connection pins and form a central wiring segment in the remaining middle segment to constrain the wiring of the error-reporting IP to be led out from its central wiring segment during automatic routing; Wherein, the width of the central wiring segment is the same as the width of the wiring, and its y-direction center line coincides with the y-direction center line of the external connection pins. The y direction refers to the length direction of the external connection pins, and the lengths of the left and right segments are both greater than or equal to 0.02 um; S103. Start automatic routing.

2. The IP pin anti-violation routing method in the N12 design according to claim 1, wherein, The two blocking regions completely cover the left and right sides of the external connection pins, and the inner spacing between the two is equal to the width of the central wiring segment.

3. The IP pin anti-violation routing method in an N12 design according to claim 1, characterized in that, The two blocking regions only completely cover the left and right sides of the external connection pins in the x direction, and the inner spacing between the two is equal to the width of the central wiring segment. The front sides of the two blocking regions coincide with the left and right segments of the front side of the external connection pins respectively or extend beyond the front side of the external connection pins in the y direction. Here, the x direction refers to the width direction of the external connection pins.

4. The IP pin anti-violation routing method in an N12 design according to claim 1, characterized in that The rear sides of the two blocking regions coincide with the left and right segments of the front side of the external connection pins respectively, the inner spacing between the two is equal to the width of the central wiring segment, and the lengths of the rear sides of the two blocking regions are greater than or equal to the lengths of the left or right segment of the front side of the external connection pins.

5. A method for preventing illegal routing of IP pins in an N12 design according to claim 1, characterized in that The chip design tool uses IC Compiler II.

6. An IP pin anti-violation routing device in the N12 design, characterized in that, This device is based on a chip design tool and includes: The first module is used to determine the error-reporting IP, where the error-reporting IP refers to the IP that has a Mxe.L.5 DRC violation; The second module is used to use the y-direction center line of the external connection pins of the error-reporting IP as the axis of symmetry to generate two axially symmetric rectangular blocking regions, which are used to block at least the left and right segments of the front side of the external connection pins and form a central wiring segment in the remaining middle segment to constrain the wiring of the error-reporting IP to be led out from its central wiring segment during automatic routing; Wherein, the width of the central wiring segment is the same as the width of the wiring, and its y-direction center line coincides with the y-direction center line of the external connection pins. The y direction refers to the length direction of the external connection pins, and the lengths of the left and right segments are both greater than or equal to 0.02 um; The third module is used to start automatic routing.

7. An electronic device, characterized in that, It includes a storage module, and the storage module includes instructions loaded and executed by a processor. When the instructions are executed, the processor executes an IP pin anti-violation routing method in a N12 design according to any one of claims 1-5.

8. A computer-readable storage medium storing one or more programs, characterized in that, When the one or more programs are executed by a processor, they implement an IP pin anti-violation routing method in a N12 design according to any one of claims 1-5.

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