Gate driving circuit, driving method thereof, display substrate and display device

Abstract

A gate drive circuit includes a start control circuit and a signal generation circuit. The start-up control circuit is configured to generate a plurality of start-up control signals. The signal generation circuit is connected with the starting control circuit and is configured to generate a plurality of scanning control signals according to the plurality of starting control signals, process the plurality of scanning control signals and then provide the processed scanning control signals to the pixel circuit. Wherein the plurality of scanning control signals comprise n scanning control pulses, the pixel circuit is controlled by the n scanning control pulses, the n scanning control pulses are controlled by log2 (2n) starting control signals, and n is an integer greater than 1.

Description

Technical Field

[0001] This application relates to, but is not limited to, the field of display technologies, and particularly relates to a gate driving circuit, a driving method thereof, a display substrate, and a display device. Background Art

[0002] Micro Organic Light-Emitting Diode (abbreviated as Micro-OLED) is a micro display developed in recent years, and silicon-based OLED is one of them. Silicon-based OLED is a new display technology that combines semiconductor process manufacturing and OLED display technology to fabricate OLED display devices on a wafer substrate. Due to the advantages of both semiconductor manufacturing processes and OLED display technology, silicon-based OLED not only has a high pixel density (Pixels Per Inch, abbreviated as PPI), but also has advantages such as high brightness, low power consumption, high response speed, high color gamut, and high thermal stability. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this application. This overview is not intended to limit the scope of protection of the claims.

[0004] Embodiments of this application provide a gate driving circuit, a driving method thereof, a display substrate, and a display device.

[0005] On the one hand, this embodiment provides a gate driving circuit, including: a start control circuit and a signal generation circuit. The start control circuit is configured to generate a plurality of start control signals. The signal generation circuit is connected to the start control circuit and is configured to generate a plurality of scan control signals according to the plurality of start control signals, and process the plurality of scan control signals and then provide them to the pixel circuit. Among them, the plurality of scan control signals include n scan control pulses, the pixel circuit is controlled by the n scan control pulses, and the n scan control pulses are controlled by log2(2n) start control signals, where n is an integer greater than 1.

[0006] In some exemplary embodiments, the value of n is 4.

[0007] In some exemplary embodiments, the plurality of scan control signals include: a write switch signal, and the write switch signal includes: a first scan control pulse and a second scan control pulse. The first scan control pulse is configured to control a gate electrode of a driving transistor of the pixel circuit to write a bias voltage, and the second scan control pulse is configured to control the gate electrode of the driving transistor of the pixel circuit to write a data voltage. The plurality of start control signals include: a first start control signal, a second start control signal, and a third start control signal. A time interval between an end time of the first scan control pulse and a start time of the second scan control pulse of the write switch signal is controlled by a start time of a pulse of the second start control signal and an end time of a pulse of the third start control signal.

[0008] In some exemplary embodiments, within one frame period, a time interval between an end time of the first scan control pulse and a start time of the second scan control pulse of the write switch signal is greater than or equal to at least one line period duration.

[0009] In some exemplary embodiments, a duration of an active level of the first scan control pulse of the write switch signal is less than or equal to a duration of an active level of the second scan control pulse.

[0010] In some exemplary embodiments, a start time of the first scan control pulse of the write switch signal is controlled by a start time of a pulse of the first start control signal, and an end time of the second scan control pulse is controlled by an end time of a pulse of the first start control signal.

[0011] In some exemplary embodiments, the plurality of scan control signals further include: a display switch signal, and the display switch signal includes: a third scan control pulse; the third scan control pulse is configured to control the driving transistor of the pixel circuit to perform self-discharge; a start time and an end time of the third scan control pulse are controlled by the second start control signal.

[0012] In some exemplary embodiments, within one frame period, an end time of the first scan control pulse of the write switch signal is earlier than or equal to a start time of the third scan control pulse of the display switch signal, and an end time of the third scan control pulse is later than an end time of the second scan control pulse of the write switch signal. A time duration between the start time of the third scan control pulse and the start time of the second scan control pulse is a self-discharge duration, and the self-discharge duration is greater than or equal to at least one line period duration and less than a duration of a vertical blanking period within one frame period.

[0013] In some exemplary embodiments, the plurality of scan control signals further includes: a display reset signal, and the display reset signal includes: a fourth scan control pulse; the fourth scan control pulse is configured to control the conduction or disconnection of the display reset transistor of the pixel circuit. The start time of the fourth scan control pulse is controlled by the pulse start time of the third start control signal, and the end time of the fourth scan control pulse is controlled by the pulse end time of the second start control signal.

[0014] In some exemplary embodiments, each start control signal is configured to be controlled by a corresponding initial start signal and a clock signal. The initial start signal is configured to be set by at least one of the following parameters: a shift parameter, a first pulse parameter, a second pulse parameter, and a third pulse parameter. The shift parameter is the number of row periods at which the start time of the timing pulse in a frame period is relative to the reference time; the first pulse parameter is the duration of the timing pulse in a frame period; the second pulse parameter is the duration between the start time of a row period and the start time of the timing pulse; the third pulse parameter is the duration between the start time of a row period and the end time of the timing pulse.

[0015] In some exemplary embodiments, the first start control signal is configured to be controlled by a first initial start signal and a first clock signal, and the second start control signal is configured to be controlled by a second initial start signal and a second clock signal. The interval duration between the end time of the first scan control pulse and the start time of the second scan control pulse of the write switch signal is greater than the duration of M row periods, and the value of M is the same as the parameter value of the shift parameter of the first initial start signal; the parameter value of the shift parameter of the first initial start signal is the same as the parameter value of the shift parameter of the second initial start signal.

[0016] In some exemplary embodiments, the signal generation circuit includes: a first arithmetic circuit, and the first arithmetic circuit includes: a first NAND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, and a two-way selector. Wherein, a first input terminal of the first NAND gate is configured to receive the second start control signal, a second input terminal of the first NAND gate is configured to receive the third start control signal, an output terminal of the first NAND gate is connected to an input terminal of the first inverter, an output terminal of the first inverter is connected to a first input terminal of the first NOR gate, a second input terminal of the first NOR gate is configured to receive the first start control signal, an output terminal of the first NOR gate is connected to an input terminal of the second inverter, an output terminal of the second inverter is connected to a first input terminal of the second NOR gate, a second input terminal of the second NOR gate is configured to receive a fourth clock signal, an output terminal of the second NOR gate is connected to an input terminal of the third inverter, an output terminal of the third inverter is connected to a second input terminal of the two-way selector, and a first input terminal of the two-way selector is configured to receive the first start control signal. An input terminal of the fourth inverter is configured to receive a second reset signal, an output terminal of the fourth inverter is connected to a second input terminal of the third NOR gate, a first input terminal of the third NOR gate is configured to receive a first reset signal, and an output terminal of the third NOR gate is connected to a control terminal of the two-way selector; an output terminal of the two-way selector is configured to output the write switch signal.

[0017] In some exemplary embodiments, the signal generation circuit includes: a second arithmetic circuit; the second arithmetic circuit includes: a latch, a second NAND gate, a fourth NOR gate, and a delay circuit. An input terminal of the delay circuit is configured to receive the write switch signal, an output terminal of the delay circuit is connected to an enable input terminal of the latch, a data input terminal of the latch is configured to receive the second start control signal, an output terminal of the latch is connected to a second input terminal of the fourth NOR gate, a first input terminal of the fourth NOR gate is configured to receive an inverted signal of the duty cycle control signal, an output terminal of the fourth NOR gate is connected to a first input terminal of the second NAND gate, a second input terminal of the second NAND gate is configured to receive the second reset signal, and an output terminal of the second NAND gate is configured to output the display switch signal.

[0018] In some exemplary embodiments, the signal generation circuit includes: a third arithmetic circuit; the third arithmetic circuit is connected to the start control circuit and is configured to perform a logical OR operation on the second start control signal and the third start control signal to generate the display reset signal.

[0019] On the other hand, this embodiment provides a driving method for a gate driving circuit, which is applied to the gate driving circuit as described above. The driving method includes: the start control circuit generates a plurality of start control signals; the signal generation circuit generates a plurality of scan control signals according to the plurality of start control signals, and processes the plurality of scan control signals and provides them to the pixel circuit. Among them, the plurality of scan control signals include n scan control pulses, the pixel circuit is controlled by the n scan control pulses, and the n scan control pulses are controlled by log2(2n) start control signals, where n is an integer greater than 1.

[0020] On the other hand, this embodiment provides a display substrate, which includes a display area and a non-display area. The display area includes a plurality of sub-pixels, and at least one sub-pixel includes a pixel circuit and at least one scan signal line, and the scan signal line is configured to provide a scan signal to the connected pixel circuit. The non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scan signal line in the display area, and at least one gate driving circuit includes the gate driving circuit as described above.

[0021] In some exemplary embodiments, within one frame period, the reference voltage written by the pixel circuit during the vertical blanking period has the same magnitude as the bias voltage written during the initialization period of the display period.

[0022] On the other hand, this embodiment provides a display device, which includes the display substrate as described above.

[0023] Other features and advantages of this application will be described in the subsequent specification, and, in part, will become apparent from the specification, or will be understood by implementing this application. Other advantages of this application can be realized and obtained through the solutions described in the specification and the drawings. Description of the Drawings

[0024] The drawings are used to provide an understanding of the technical solutions of this application, and constitute a part of the specification. Together with the embodiments of this application, they are used to explain the technical solutions of this application, and do not constitute a limitation to the technical solutions of this application.

[0025] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device;

[0026] Figure 2 It is a schematic plan view of a display area in a silicon-based OLED display device;

[0027] Figure 3 It is a schematic cross-sectional view of a display area in a silicon-based OLED display device;

[0028] Figure 4A andFigure 4B It is an equivalent circuit diagram of a pixel circuit;

[0029] Figure 5A It is Figure 4A a driving timing diagram of the pixel circuit shown;

[0030] Figure 5B It is Figure 4B a driving timing diagram of the pixel circuit shown;

[0031] Figure 6 It is a schematic structural diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0032] Figure 7 It is a working principle diagram of a startup control circuit according to at least one embodiment of the present disclosure;

[0033] Figures 8A to 8D It is a working timing diagram of a startup control circuit according to at least one embodiment of the present disclosure;

[0034] Figure 8E It is a timing relationship diagram of multiple timing output signals according to at least one embodiment of the present disclosure;

[0035] Figure 9A and Figure 9B It is a schematic diagram of the timing setting of an initial startup signal according to at least one embodiment of the present disclosure;

[0036] Figure 10 It is a working principle diagram of a first scan signal generation circuit according to at least one embodiment of the present disclosure;

[0037] Figure 11 It is a timing diagram of a first operation circuit according to at least one embodiment of the present disclosure;

[0038] Figure 12 It is a working principle diagram of a second scan signal generation circuit according to at least one embodiment of the present disclosure;

[0039] Figure 13 It is a working principle diagram of a third scan signal generation circuit according to at least one embodiment of the present disclosure;

[0040] Figure 14 It is a working timing diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0041] Figure 15 It is Figure 14 a partial schematic diagram;

[0042] Figure 16 It is a timing relationship diagram of a startup control signal and a scan control signal according to at least one embodiment of the present disclosure. Specific embodiments

[0043] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope encompassed by the embodiments described in this application. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be used in combination with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.

[0044] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements disclosed in this application can also be combined with any conventional features or elements to form a unique inventive solution. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those imposed by the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.

[0045] The scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display device and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only schematic diagrams, and one aspect of this disclosure is not limited to the shapes, values, etc. shown in the drawings.

[0046] The ordinal numbers such as "first", "second", "third", etc. in this specification are set to avoid confusion of components and are not intended to limit the quantity. The "multiple" in this specification means two or more numbers.

[0047] In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positional relationships of the constituent elements with reference to the accompanying drawings. This is only for the convenience of describing this specification and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation on the present disclosure. The positional relationships of the constituent elements are appropriately changed according to the directions describing the constituent elements. Therefore, it is not limited to the terms described in the specification and can be appropriately replaced according to the circumstances.

[0048] In this specification, unless otherwise clearly defined and limited, the terms "mounted", "connected", and "coupled" shall be construed broadly. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate member, or the internal communication of two elements. For those of ordinary skill in the art, the meanings of the above terms in the present disclosure can be understood according to the circumstances.

[0049] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows.

[0050] In this specification, in order to distinguish the two poles of a transistor other than the gate electrode, one of the poles is directly described as the first pole and the other as the second pole. Among them, the first pole can be the drain electrode and the second pole can be the source electrode, or the first pole can be the source electrode and the second pole can be the drain electrode. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, etc., the functions of the "source electrode" and "drain electrode" sometimes swap. Therefore, in this specification, the "source electrode" and "drain electrode" can be swapped with each other.

[0051] In this specification, "electrically connected" includes the case where constituent elements are connected together through an element having a certain electrical effect. There is no particular limitation on the "element having a certain electrical effect" as long as it can transmit electrical signals between the constituent elements to be connected. Examples of the "element having a certain electrical effect" include not only electrodes and wirings, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0052] In this specification, "parallel" means a state where the angle formed by two straight lines is more than -10° and less than 10°, and thus also includes the state where the angle is more than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is more than 80° and less than 100°, and thus also includes the state where the angle is more than 85° and less than 95°.

[0053] In this specification, "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be changed to "conductive film". Similarly, sometimes "insulating film" can be changed to "insulating layer".

[0054] Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not in a strict sense, and can be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc. There can be some small deformations caused by tolerances, and there can be chamfers, arc edges, and deformations, etc.

[0055] In this specification, the effective level includes the level for turning on the transistor. For example, the effective level for turning on a P-type transistor is a low level, and the effective level for turning on an N-type transistor is a high level.

[0056] "About", "substantially", "approximately" in this specification mean not strictly defining the boundary and allowing the situation within the process and measurement errors.

[0057] Figure 1 It is a schematic structural diagram of a silicon-based OLED display device. As Figure 1As shown, the silicon-based OLED display device may include: a display area and a non-display area. The display area may include a plurality of scan signal lines, a plurality of data signal lines, and a plurality of sub-pixels PXij forming a plurality of pixel rows and a plurality of pixel columns. The plurality of scan signal lines are respectively disposed in the plurality of pixel rows, and the plurality of data signal lines are respectively disposed in the plurality of pixel columns. Each sub-pixel PXij may at least include: a pixel circuit and a light-emitting device. The pixel circuit is configured to provide the current required for light emission to the connected light-emitting device. The pixel circuit of each sub-pixel PXij may be connected to the scan signal line of the corresponding pixel row and the data signal line of the corresponding pixel column. The sub-pixel PXij may refer to the sub-pixel of the i-th pixel row and the j-th pixel column, and the pixel circuits of the sub-pixel PXij are respectively connected to the i-th scan signal line and the j-th data signal line. Among them, i and j may be natural numbers. The non-display area may include: a display driver integrated circuit (DDIC), a gate driver (GD), and a source driver (SD). The display driver circuit may at least include a timing controller (TCON). The timing controller is configured to generate the timing signals required for the gate driver, such as including a start signal (STV) and a clock signal (CKV), etc., and send the timing signals to the gate driver. The gate driver is respectively connected to the plurality of scan signal lines in the display area. The gate driver is configured to provide the required timing signals (timing) to the connected pixel circuits to implement the display line-by-line scanning function. The data driver is respectively connected to the plurality of data signal lines in the display area. The data driver is configured to provide the required data signals (data) to the connected pixel circuits to implement the switching and control of the display screen.

[0058] In one example, the silicon-based OLED display device may be a single-chip display architecture (One Chip), integrating the gate driver, data driver, clock control unit, image processing unit, storage unit, etc. on the same chip. The chip of the OneChip architecture includes both digital and analog parts and belongs to a mixed-signal chip.

[0059] In another example, the silicon-based OLED display device may be a two-chip display architecture. The gate driving device and the data driving device may be integrated in the display substrate. The clock control unit, the image processing unit, the Mobile Industry Processor Interface (MIPI), and the storage unit may be integrated in one chip, and this chip may be bonded to the display substrate through a Chip On Chip (COC) process.

[0060] Figure 2 It is a schematic plan view of the display area in a silicon-based OLED display device. As Figure 2 shown, on a plane parallel to the display device, the display area may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include: a first sub-pixel P1 that emits first-color light, a second sub-pixel P2 that emits second-color light, and a third sub-pixel P3 that emits third-color light. Each of the three sub-pixels may include a pixel circuit and a light-emitting device. The pixel circuits in the sub-pixels are respectively connected to the scan signal line and the data signal line. The pixel circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and output a corresponding current to the light-emitting device. The light-emitting device in the sub-pixel is connected to the pixel circuit of the sub-pixel where it is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel circuit of the sub-pixel where it is located.

[0061] In some examples, the first sub-pixel P1 may be a red (R) sub-pixel that emits red light, the second sub-pixel P2 may be a blue (B) sub-pixel that emits blue light, and the third sub-pixel P3 may be a green (G) sub-pixel that emits green light.

[0062] In some examples, the planar shape of the light-emitting device of the sub-pixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The light-emitting devices of the three sub-pixels may be arranged in a horizontal side-by-side, vertical side-by-side, or zigzag pattern, etc. The present disclosure does not limit this here. In other possible embodiments, the pixel unit may include four sub-pixels, and the present disclosure does not limit this here.

[0063] Figure 3 It is a schematic cross-sectional view of the display area in a silicon-based OLED display device, Figure 3 illustrating a structure for achieving full color by using white light + color film method. As Figure 3As shown in the figure, in a direction perpendicular to the display device, the silicon-based OLED display device may include: a silicon substrate 101, a driving circuit layer 102 disposed on the silicon substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the silicon substrate 101, a first encapsulation layer 104 disposed on a side of the light-emitting structure layer 103 away from the silicon substrate 101, a color filter structure layer 105 disposed on a side of the first encapsulation layer 104 away from the silicon substrate 101, a second encapsulation layer 106 disposed on a side of the color filter structure layer 105 away from the silicon substrate 101, and a cover plate layer 107 disposed on a side of the second encapsulation layer 106 away from the silicon substrate 101. In some possible implementation manners, the silicon-based OLED display device may include other film layers, which are not limited in this disclosure.

[0064] In some examples, the silicon substrate 101 may be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The driving circuit layer 102 may be fabricated on the silicon substrate 101 through a silicon semiconductor process. The driving circuit layer 102 may include a plurality of circuit units, and the circuit units may at least include pixel circuits. The pixel circuits are respectively connected to a scan signal line and a data signal line. The pixel circuit may include a plurality of transistors and a storage capacitor. Figure 3 Only one transistor is taken as an example herein. The transistor may include: a gate electrode G, a first pole S, and a second pole D. The gate electrode G, the first pole S, and the second pole D may be respectively connected to corresponding connection electrodes through vias filled with tungsten metal (i.e., tungsten vias, W-via), and may be connected to other electrical structures (such as traces, etc.) through the connection electrodes.

[0065] In some examples, the light-emitting structure layer 103 may include a plurality of light-emitting devices. The light-emitting devices may at least include an anode, an organic light-emitting layer, and a cathode. The anode may be connected to the second pole D of the transistor through a connection electrode. The organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The cathode is connected to a second power supply line. The organic light-emitting layer emits light under the drive of the anode and the cathode. In some examples, the organic light-emitting layer may include a light-emitting layer (abbreviated as EML), and any one or more of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In some examples, for the light-emitting devices that emit white light, the organic light-emitting layers of all sub-pixels may be a common layer connected together.

[0066] In some examples, the first encapsulation layer 104 and the second encapsulation layer 106 can adopt the thin film encapsulation (TFE) method, which can prevent external water vapor from entering the light-emitting structure layer. The color film structure layer 105 can at least include: a red filter unit, a blue filter unit, and a green filter unit; the red filter unit is disposed in the red sub-pixel to filter the white light emitted by the light-emitting device into red light; the blue filter unit is disposed in the blue sub-pixel to filter the white light emitted by the light-emitting device into blue light; the green filter unit is disposed in the green sub-pixel to filter the white light emitted by the light-emitting device into green light. The cover layer 107 can be made of glass or a flexible plastic such as colorless polyimide.

[0067] Figure 4A and Figure 4B is an equivalent circuit diagram of a pixel circuit. As Figure 4A and Figure 4B shown, the pixel circuit can be of a 4T2C structure and can include four transistors (for example, including a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4) and two storage capacitors (for example, including a first capacitor C1 and a second capacitor C2). The pixel circuit can be connected to six signal lines (for example, including a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a data signal line DL, a first pixel power supply line ELVDD, and a second pixel power supply line VSS1).

[0068] In some examples, the pixel circuit can include a first pixel node N1, a second pixel node N2, and a third pixel node N3. The first pixel node N1 is respectively connected to the second pole of the first transistor T1, the gate electrode of the third transistor T3, and the first end of the first capacitor C1. The second pixel node N2 is respectively connected to the second pole of the second transistor T2, the first pole of the third transistor T3, the second end of the first capacitor C1, and the first end of the second capacitor C2. The third pixel node N3 is respectively connected to the second pole of the third transistor T3 and the second pole of the fourth transistor T4.

[0069] In some examples, the first transistor T1 can be referred to as a write switch transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first pole of the first transistor T1 is connected to the data signal line DL, and the second pole of the first transistor T1 is connected to the first pixel node N1.

[0070] In some examples, the second transistor T2 may be referred to as a Display Switch transistor. The gate electrode of the second transistor T2 is connected to the second scan signal line S2. The first pole of the second transistor T2 is connected to the first pixel power supply line ELVDD. The second pole of the second transistor T2 is connected to the second pixel node N2.

[0071] In some examples, the third transistor T3 may be referred to as a Driver transistor. The gate electrode of the third transistor T3 is connected to the first pixel node N1. The first pole of the third transistor T3 is connected to the second pixel node N2. The second pole of the third transistor T3 is connected to the third pixel node N3.

[0072] In some examples, the fourth transistor T4 may be referred to as an Auto Zero transistor. The gate electrode of the fourth transistor T4 is connected to the third scan signal line S3. The first pole of the fourth transistor T4 is connected to the second pixel power supply line VSS1. The second pole of the fourth transistor T4 is connected to the third pixel node N3.

[0073] In some examples, the first end of the first capacitor C1 is connected to the first pixel node N1. The second end of the first capacitor C1 is connected to the second pixel node N2. The first end of the second capacitor C2 is connected to the second pixel node N2. The second end of the second capacitor C2 is connected to the first pixel power supply line ELVDD.

[0074] In some examples, the light-emitting device EL may be an organic light-emitting diode (OLED), including a stacked first pole (anode), an organic light-emitting layer, and a second pole (cathode). The first pole of the light-emitting device EL is connected to the third pixel node N3. The second pole of the light-emitting device EL is connected to the common voltage line VCOM.

[0075] In some examples, the signal of the first pixel power supply line ELVDD may be a continuously provided high-level signal. The signals of the second pixel power supply line VSS1 and the common voltage line VCOM may be continuously provided low-level signals.

[0076] In some examples, the first transistor T1 to the fourth transistor T4 may be P-type transistors (PMOS), or may be N-type transistors (NMOS). For example, as Figure 4BAs shown, the first transistor T1 to the fourth transistor T4 are all P-type transistors. Using transistors of the same type in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product. In some examples, the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 may all include a bottom gate (which may also be referred to as a back gate); the bottom gates of the first transistor T1, the second transistor T2, and the third transistor T3 may all be connected to the third pixel power supply line AVDD, and the bottom gate of the fourth transistor T4 may be connected to the second pixel power supply line VSS1. The signal of the third pixel power supply line AVDD may be a continuously provided high-level signal. For example, the signal of the third pixel power supply line AVDD is the same as the signal of the first pixel power supply line ELVDD.

[0077] In some examples, the first transistor T1 to the fourth transistor T4 may include P-type transistors and N-type transistors. For example, the first transistor T1 to the third transistor T3 may be P-type transistors, and the fourth transistor T4 may be an N-type transistor, as Figure 4A shown. In some examples, the first transistor T1, the second transistor T2, and the third transistor T3 may all include a bottom gate, and the bottom gates of the three transistors are all connected to the third pixel power supply line AVDD.

[0078] Figure 5A is Figure 4A a driving timing diagram of the pixel circuit shown. Figure 5B is Figure 4B a driving timing diagram of the pixel circuit shown. In Figure 5A , the signal of the third scan signal line S3 is a high-level signal (i.e., the effective level of the third scan signal is high level), causing the fourth transistor T4 to conduct; in Figure 5B , the signal of the third scan signal line S3 is a low-level signal (i.e., the effective level of the third scan signal is low level), causing the fourth transistor T4 to conduct.

[0079] In some examples, as Figure 5A and Figure 5B shown, the working process of the pixel circuit may include the following stages.

[0080] The first stage A1 is from time t0 to time t1, which can be called the initialization stage. The signals of the first scan signal line S1 and the second scan signal line S2 are low-level signals, and the signal of the third scan signal line S3 is a high-level signal, making the first transistor T1, the second transistor T2, and the fourth transistor T4 conduct. The conduction of the first transistor T1 causes the bias voltage Vofs output by the data signal line DL to be written into the first capacitor C1, and the potential Vg of the first pixel node N1 (i.e., the gate electrode of the third transistor T3) is Vg = Vofs. The conduction of the second transistor T2 causes the first pixel power supply voltage ELVdd output by the first pixel power supply line ELVDD to be written into the second pixel node N2, and the potential Vs of the second pixel node N2 (i.e., the first pole of the third transistor T3) is Vs = ELVdd. At this time, the stored voltage Vini of the first capacitor C1 is Vini = ELVdd - Vofs, and the potential Vd of the third pixel node N3 (i.e., the second pole of the third transistor T3) is Vd = Vg + Vth, preparing for the discharge in the next stage. Among them, ELVdd - Vofs > |Vth|, and Vth is the threshold voltage of the third transistor T3.

[0081] The second stage A2 is from time t1 to time t2, which can be called the self-discharge stage. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 continues to conduct. The signal of the first scan signal line S1 changes from a low-level signal to a high-level signal, causing the first transistor T1 to disconnect first, and the first pixel node N1 floats. Subsequently, the signal of the second scan signal line S2 changes from a low-level signal to a high-level signal, causing the second transistor T2 to disconnect. The second pixel node N2 forms a loop through the conducting third transistor T3, the third pixel node N3, and the conducting fourth transistor T4 and starts to discharge, and the potential of the second pixel node N2 drops. Because the first pixel node N1 floats, the voltage difference across the first capacitor C1 remains unchanged, so the potential of the first pixel node N1 drops as the potential of the second pixel node N2 drops. Due to the body effect of the third transistor T3, the gate-source voltage Vgs of the third transistor T3 remains unchanged, so the equivalent threshold voltage |Vth_EF| of the third transistor T3 gradually increases as the potential of the second pixel node N2 drops. The equivalent threshold voltage |Vth_EF| of the third transistor T3 is |Vth_EF| = α(ELVdd - Vs) + |Vth|, where α is the body effect coefficient. When the equivalent threshold voltage |Vth_EF| of the third transistor T3 increases to the gate-source voltage Vgs of the third transistor T3, the third transistor T3 disconnects, and the second pixel node N2 stops discharging. At this time, |Vth_EF| = α(ELVdd - Vs) + |Vth| = Vini, Vs = AVdd + (|Vth| - Vini) / α, Vg = AVdd + (|Vth| - Vini) / α - Vini. Among them, AVdd is the third pixel power supply voltage output by the third pixel power supply line AVDD.

[0082] The third stage A3 is from time t2 to time t3, which can be called the data writing stage and the threshold compensation stage. The signal of the second scan signal line S2 is a high-level signal, and the second transistor T2 remains off continuously. The signal of the third scan signal line S3 is a high-level signal, and the fourth transistor T4 remains on continuously. The signal of the first scan signal line S1 changes from a high-level signal to a low-level signal, turning on the first transistor T1. The conduction of the first transistor T1 causes the data voltage Vdata output by the data signal line DL to be written into the first pixel node N1, and the potential of the first pixel node N1 changes from Vofs to Vdata. Since the second pixel node N2 is floating, △Vs=(1 - b)△Vg, where b = c2 / (c1 + c2), c1 is the capacitance value of the first capacitor C1, and c2 is the capacitance value of the second capacitor C2. At this time, the voltage of the second pixel node N2 becomes: AVdd-(Vini - |Vth|) / a+(1 - b)(Vdata - AVdd+(Vini - |Vth|) / a+Vini)=Vdata+Vini - bVdata + bAVdd-(b(Vini - |Vth|)) / a - bVini. At this time, |Vgs|=(1-(b / a)-b)Vini+(b / a)|Vth|+b(ELVdd - Vdata). This stage can achieve threshold compensation.

[0083] The fourth stage A4 is after time t4, which can be called the light emitting stage. The signals of the second scan signal line S2 and the third scan signal line S3 are low-level signals, and the signal of the first scan signal line S1 is a high-level signal, turning on the second transistor T2 and turning off the first transistor T1 and the fourth transistor T4. The conduction of the second transistor T2 causes the first pixel power supply voltage output by the first pixel power supply line ELVDD to provide a driving voltage to the first pole of the light emitting device EL through the conducting second transistor T2 and the third transistor T3, driving the light emitting device EL to emit light. The driving current It can be seen that when Ioled is independent of |Vth|, that is, the threshold voltage compensation is completed. Where K is the current coefficient of the third transistor.

[0084] In the light emitting stage, the driving current of the third transistor T3 is not affected by the threshold voltage of the third transistor T3, eliminating the influence of the threshold voltage of the third transistor T3 on the driving current, ensuring the display brightness uniformity of the display product, and improving the display effect of the entire display product.

[0085] In this example, the pixel circuit receives three scan signals (including the first scan signal transmitted by the first scan signal line, the second scan signal transmitted by the second scan signal line, and the third scan signal transmitted by the third scan signal line). In the traditional solution, the three scan signals are usually generated by three gate driving circuits respectively. In other words, each gate driving circuit generates one scan signal. The traditional solution is not conducive to the integrated design of the gate driving circuit.

[0086] Moreover, from the four working stages of the pixel circuit, it can be seen that in the second stage A2, from time t1 to time t2 is the process of threshold voltage reading. This process is achieved by discharging. By using the back-gate effect, the equivalent threshold voltage |Vth_EF| of the driving transistor is increased to Vgs. As the equivalent threshold voltage of the driving transistor increases (getting closer and closer to Vgs), the conduction degree of the driving transistor becomes smaller, the discharge current flowing through the driving transistor becomes smaller, and more time is required for discharging, so that |Vth_EF| = α×(ELVdd - Vs)+|Vth|. In other words, the longer the discharge time, the closer |Vth_EF| is to α×(ELVdd - Vs)+|Vth|, and the more sufficient the threshold voltage reading of the driving transistor is, and the more sufficient the threshold voltage compensation can be in the subsequent third stage.

[0087] In some examples, such as Figure 5A and Figure 5B shown, the self-discharge duration in the self-discharge stage (i.e., the second stage A2) is determined by the rising edge of the second scan signal, the rising edge of the first pulse of the first scan signal, and the falling edge of the second pulse of the first scan signal. The self-discharge duration τ = t2 - t1. If the writing of the bias voltage Vofs (controlled by the first pulse of the first scan signal) and the writing of the data voltage Vdata (controlled by the second pulse of the first scan signal) are both completed in the same row, on the basis of ensuring sufficient discharge duration, it will result in an overly long row time, restricting the display refresh rate. In the design of the traditional solution, the pixel circuit completes three stages of pixel circuit initialization, threshold voltage reading, and data writing within one row period, and emits light (Emission) during the remaining time of one frame period. The writing of the bias voltage Vofs and the writing of the data voltage Vdata are completed in the same row, and the self-discharge duration is less than the duration of one row period. At high resolutions and high refresh rates, the duration of one row period is significantly compressed (for example, at a resolution of 3840 lines, the duration of one row period is about 2.85 microseconds (us)). However, the self-discharge stage is completed through threshold self-pinch-off, so sufficient discharge requires a relatively long duration. Generally, the self-discharge duration needs to be more than 8 us. It can be seen that achieving a high refresh rate and ensuring a sufficiently long threshold voltage reading time to achieve sufficient compensation of the threshold voltage are contradictory to each other. It is impossible to achieve a high refresh rate while ensuring the self-discharge duration, and vice versa.

[0088] This embodiment provides a gate driving circuit, including: a start control circuit and a signal generation circuit. The start control circuit is configured to generate a plurality of start control signals. The signal generation circuit is connected to the start control circuit and is configured to generate a plurality of scan control signals according to the plurality of start control signals, and process the plurality of scan control signals and then provide them to the pixel circuit. Among them, the plurality of scan control signals include n scan control pulses, the pixel circuit is controlled by the n scan control pulses, and the n scan control pulses are controlled by log2(2n) start control signals, where n is an integer greater than 1.

[0089] The gate driving circuit provided in this embodiment can generate n scan control pulses for controlling the pixel circuit by using log2(2n) start control signals, which is beneficial to reducing the number of start control signals and is beneficial to the integrated design of the gate driving circuit.

[0090] In this example, a frame period refers to the process from the start of one frame to the start of the next frame. The duration of a frame period can represent the duration required to refresh the entire display panel. A line period refers to the process from the start of one row of pixels in the display panel to the start of the next row of pixels. The duration of a line period can represent the duration required to scan a complete row of the display panel. For example, the display panel includes 3840 rows, and the duration of a line period is 1 / 3840 of the duration of a frame.

[0091] In some exemplary embodiments, n can be 4 and log2(2n) can be 3. For example, the pixel circuit can be controlled by 4 scan control pulses, and the 4 scan control pulses are controlled by 3 start control signals. In this example, the 4 scan control pulses can include 8 state transitions (including the rising edge and falling edge of the pulses), and the 8 state transitions can be controlled by 3 start control signals, which can make full use of the states of the 3 start control signals, thereby reducing the number of required start control signals.

[0092] In some exemplary embodiments, the plurality of scan control signals may include: a write switch signal, and the write switch signal may include: a first scan control pulse and a second scan control pulse. The first scan control pulse may be configured to control a gate electrode of a driving transistor of a pixel circuit to write a bias voltage, and the second scan control pulse may be configured to control the gate electrode of the driving transistor of the pixel circuit to write a data voltage. The plurality of start control signals may include: a first start control signal, a second start control signal, and a third start control signal. The interval duration between the end time of the first scan control pulse and the start time of the second scan control pulse of the write switch signal is controlled by the start time of the pulse of the second start control signal and the end time of the pulse of the third start control signal. For example, both the second start control signal and the third start control signal may include high-level pulses; the end time of the first scan control pulse of the write switch signal may be controlled by the rising edge of the second start control signal, and the start time of the second scan control pulse of the write switch signal may be controlled by the falling edge of the third start control signal.

[0093] In this example, the pulse end time may refer to the end time of the effective level of the pulse, and the pulse start time may refer to the start time of the effective level of the pulse. For example, for a high-level pulse, the pulse start time may correspond to the rising edge, and the pulse end time may correspond to the falling edge; for a low-level pulse, the pulse start time may correspond to the falling edge, and the pulse end time may correspond to the rising edge.

[0094] In some exemplary embodiments, the start time of the first scan control pulse of the write switch signal is controlled by the start time of the pulse of the first start control signal, and the end time of the second scan control pulse is controlled by the end time of the pulse of the first start control signal. For example, the start time of the first scan control pulse of the write switch signal is controlled by the rising edge of the first start control signal, and the end time of the second scan control pulse is controlled by the falling edge of the first start control signal.

[0095] In some exemplary embodiments, within one frame period, the interval duration between the end time of the first scan control pulse and the start time of the second scan control pulse of the write switch signal may be greater than or equal to at least one line period duration. This example can ensure that the interval duration between writing the bias voltage and writing the data voltage of the pixel circuit is greater than or equal to at least one line period duration, which can not only ensure that the self-discharge duration of the pixel circuit is long enough to fully read and compensate the threshold voltage, is beneficial to complete the threshold compensation of the current-mode pixel circuit on the basis of fully reading the threshold voltage, improve the uniformity of display brightness, but also is beneficial to increasing the refresh rate. For example, the gate driving circuit in this example can meet the requirements of progressive scanning of a microdisplay substrate with a resolution of 4K*4K and a high refresh rate of 90Hz.

[0096] In some examples, after the scan control signal undergoes voltage domain conversion and signal enhancement, it can be provided to the pixel circuit as a scan signal. The multiple scan control signals can include: a write switch signal, a display switch signal, and a display reset signal. Among them, the write switch (WS) signal after voltage domain conversion and signal enhancement can be provided to the pixel circuit as a first scan signal, and the first scan signal can be configured to control the conduction and disconnection of the first transistor T1 in the pixel circuit. The display switch (DS) signal after voltage domain conversion and signal enhancement can be provided to the pixel circuit as a second scan signal, and the second scan signal can be configured to control the conduction and disconnection of the second transistor T2 in the pixel circuit. The display reset (AZ) signal after voltage domain conversion and signal enhancement can be provided to the pixel circuit as a third scan signal, and the third scan signal can be configured to control the conduction and disconnection of the fourth transistor T4 in the pixel circuit.

[0097] In some exemplary embodiments, the duration of the effective level of the first scan control pulse of the write switch signal can be less than or equal to the duration of the effective level of the second scan control pulse. In this example, the duration of the effective level of the second scan control pulse can control the writing duration of the data voltage, and the duration of the effective level of the first scan control pulse can control the writing duration of the bias voltage. The writing duration of the data voltage being greater than or equal to the writing duration of the bias voltage is beneficial for the full writing of the data voltage, thereby improving the display effect.

[0098] In some exemplary embodiments, the display switch signal can include a third scan control pulse. The third scan control pulse can be configured to control the self-discharge of the driving transistor in the pixel circuit. The start time and end time of the third scan control pulse can be controlled by a second start control signal. For example, the start time of the third scan control pulse can be controlled by the pulse start time of the second start control signal, and the end time of the third scan control pulse can be controlled by the pulse end time of the second start control signal. For instance, the start time of the third scan control pulse is controlled by the rising edge of the second start control signal, and the end time of the third scan control pulse is controlled by the falling edge of the second start control signal.

[0099] In some exemplary embodiments, within one frame period, the end time of the first scan control pulse of the write switch signal is earlier than or equal to the start time of the third scan control pulse of the display switch signal, and the end time of the third scan control pulse is later than the end time of the second scan control pulse of the write switch signal. The duration between the start time of the third scan control pulse and the start time of the second scan control pulse is the self-discharge duration, and the self-discharge duration can be greater than or equal to at least one line period duration and less than the duration of the vertical blanking period within one frame period. The write switch signal generated by the gate driving circuit in this example can enable at least one row of pixel circuits (such as including the first row of pixel circuits) to write a bias voltage during the vertical blanking period of one frame period, so that the vertical blanking period can be utilized to increase the self-discharge duration of the pixel circuits, which is beneficial to complete the threshold compensation of the current-type pixel circuits on the basis of fully reading the threshold voltage and improve the uniformity of display brightness.

[0100] In some exemplary embodiments, the display reset signal may include: a fourth scan control pulse. The fourth scan control pulse may be configured to control the conduction or disconnection of the display reset transistor of the pixel circuit. The start time of the fourth scan control pulse may be controlled by the pulse start time of the third start control signal, and the end time of the fourth scan control pulse may be controlled by the pulse end time of the second start control signal. For example, the start time of the fourth scan control pulse is controlled by the rising edge of the third start control signal, and the end time of the fourth scan control pulse is controlled by the falling edge of the second start control signal.

[0101] In some exemplary embodiments, each start control signal may be configured to be controlled by a corresponding initial start signal and a clock signal. Among them, the initial start signal may be configured to be set by at least one of the following parameters: a shift parameter, a first pulse parameter, a second pulse parameter, and a third pulse parameter. The shift parameter is the number of line periods by which the start time of the timing pulse within one frame period is offset from the reference time. The first pulse parameter is the duration of the timing pulse within one frame period. The second pulse parameter is the duration between the start time of one line period and the start time of the timing pulse. The third pulse parameter is the duration between the start time of one line period and the end time of the timing pulse. In this example, by configuring the parameters of the initial start signal, the start control signal can be controlled to generate multiple scan control pulses and meet the self-discharge duration requirements of the pixel circuits.

[0102] In some exemplary embodiments, the first start control signal may be configured to be controlled by a first initial start signal and a first clock signal, and the second start control signal may be configured to be controlled by a second initial start signal and a second clock signal. The interval duration between the end moment of the first scan control pulse of the write switch signal and the start moment of the second scan control pulse is greater than M line cycle durations, where the value of M is the same as the parameter value of the shift parameter of the first initial start signal; the parameter value of the shift parameter of the first initial start signal is the same as the parameter value of the shift parameter of the second initial start signal. The parameter configuration in this example can increase the self-discharge duration of the pixel circuit, which is beneficial to completing the threshold compensation of the current-mode pixel circuit on the basis of fully reading the threshold voltage and improving the uniformity of display brightness.

[0103] The following uses some examples to illustrate the solution of this embodiment.

[0104] In some examples, the gate driving device may be disposed in the non-display area, may be located on one side of the pixel row direction of the display area, or may be respectively located on both sides of the pixel row direction of the display area. The gate driving device may include a plurality of cascaded gate driving circuits, and at least one gate driving circuit may be connected to the scan signal lines in a pixel row in the display area to provide scan signals to the connected scan signal lines. When the gate driving device is disposed on both sides of the pixel row direction of the display area, the scan signal lines in the pixel row may be driven by two gate driving circuits to form a bilateral driving structure, which can ensure the driving ability of a high pixel density and avoid distortion of the driving signal.

[0105] Figure 6 It is a schematic structural diagram of the gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as Figure 6 shown, the gate driving circuit includes: a start control circuit 100 and a signal generation circuit. Among them, the signal generation circuit may include: a first scan signal generation circuit 21, a second scan signal generation circuit 22, and a third scan signal generation circuit 23.

[0106] In some examples, the start control circuit 100 may be a shift register circuit composed of D Flip Flops. The start control circuit 100 is connected to the display driving circuit and receives an initial setting signal generated by the display driving circuit. The initial setting signal may include a plurality of start signals STV (or called initial start signals) and a plurality of clock signals CKV. The flip flop may be configured to perform shift register on the received initial setting signal (such as including the initial start signal), and preliminarily generate a start control signal that can be shifted row by row. In other words, the start control signal can be controlled by the initial start signal and the clock signal. In some examples, the start signal STV may also be called a frame start signal, with one frame as a cycle. The clock signal CKV may be called a line driving clock signal, with one line as a cycle.

[0107] In some examples, the initial setting signal may include: a first initial start signal STV1, a second initial start signal STV2, a third initial start signal STV3, a first clock signal CKV1, a second clock signal CKV2, and a third clock signal CKV3. The plurality of start control signals may include: a first start control signal, a second start control signal, and a third start control signal. The first start control signal can be controlled by the first initial start signal STV1 and the first clock signal CKV1, the second start control signal can be controlled by the second initial start signal STV2 and the second clock signal CKV2, and the third start control signal can be controlled by the third initial start signal STV3 and the third clock signal CKV3.

[0108] In some examples, the first scan signal generation circuit 21 is connected to the start control circuit 100, and is configured to perform a logical operation on the received plurality of start control signals (such as including the first start control signal, the second start control signal, and the third start control signal) to generate a write switch signal, and perform voltage domain conversion and signal enhancement on the write switch signal to generate a first scan signal, and output it to at least one row of pixel circuits. The second scan signal generation circuit 22 is connected to the start control circuit 100 and the first scan signal generation circuit 21, and is configured to perform a logical operation on the received start control signal (such as including the second start control signal) and the write switch signal to generate a display switch signal, and perform voltage domain conversion and signal enhancement on the display switch signal to generate a second scan signal, and output it to at least one row of pixel circuits. The third scan signal generation circuit 23 is connected to the start control circuit 100, and is configured to perform a logical operation on the received start control signal (such as including the second start control signal, the third start control signal) to generate a display reset signal, and perform voltage domain conversion and signal enhancement on the display reset signal to generate a third scan signal, and output it to at least one row of pixel circuits.

[0109] In some examples, since signals such as the start signal and the clock signal are output by the display driving circuit, and their voltage domains are inconsistent with the voltage domain of the pixel circuit, by converting through a level shifter, the required voltages (0V to -2V & -5V) are introduced, which can ensure that the voltage of the output gate driving signal matches the pixel circuit. The signal output capability can be enhanced by a driver power.

[0110] In some examples, the first scan signal generation circuit 21 may include: a first operation circuit 211, a first level shifter 221, and a first driver power 231. The output terminal of the first operation circuit 211 is connected to the input terminal of the first level shifter 221, and the output terminal of the first level shifter 221 is connected to the output terminal of the first driver power 231. The first operation circuit 211 is configured to generate a write switch signal through logical operations, the first level shifter 221 is configured to perform voltage domain conversion on the write switch signal, and the first driver power 231 is configured to enhance the signal output from the first level shifter 221.

[0111] In some examples, the second scan signal generation circuit 22 may include: a second operation circuit 212, a second level shifter 222, and a second driver power 232. The output terminal of the second operation circuit 212 is connected to the input terminal of the second level shifter 222, and the output terminal of the second level shifter 222 is connected to the output terminal of the second driver power 232. The second operation circuit 212 is configured to generate a display switch signal through logical operations, the second level shifter 222 is configured to perform voltage domain conversion on the write switch signal, and the second driver power 232 is configured to enhance the signal output from the second level shifter 222.

[0112] In some examples, the third scan signal generation circuit 23 may include: a third operation circuit 213, a third level shifter 223, and a third driver power 233. The output terminal of the third operation circuit 213 is connected to the input terminal of the third level shifter 223, and the output terminal of the third level shifter 223 is connected to the output terminal of the third driver power 233. The third operation circuit 213 is configured to generate a display reset signal through logical operations, the third level shifter 223 is configured to perform voltage domain conversion on the display reset signal, and the third driver power 233 is configured to enhance the signal output from the third level shifter 223.

[0113] Figure 7 This is the working principle diagram of the startup control circuit of at least one embodiment of the present disclosure. In some examples, such as Figure 7As shown, the start control circuit may include: a first flip-flop 301, a second flip-flop 302, a third flip-flop 303, a fourth flip-flop 304, a first transmission gate 311, a second transmission gate 312, a third transmission gate 313, a fourth transmission gate 314, a fifth transmission gate 315, a sixth transmission gate 316, a seventh transmission gate 317, and an eighth transmission gate 318.

[0114] In some examples, the data input terminal D of the first flip-flop 301 may be configured to receive a first timing input signal (such as A_Dn), the clock signal terminal of the first flip-flop 301 may be configured to receive a first clock signal CKV1, the output terminal Q of the first flip-flop 301 is configured to output a first timing output signal (such as A_Qn), and the inverted output terminal Q_ of the first flip-flop 301 is configured to output an inverted signal of the first timing output signal (such as A_Qn'). For example, the first timing input signal received by the first flip-flop of the start control circuit of the first-stage gate drive circuit may be a first initial start signal STV1. The first end of the first transmission gate 311 is connected to the data input terminal D of the first flip-flop 301 of this stage, and the second end of the first transmission gate 311 is connected to the output terminal of the first flip-flop of the next stage. The first end of the second transmission gate 312 is connected to the output terminal of the first flip-flop 301 of this stage, and the second end of the second transmission gate 312 is connected to the data input terminal of the first flip-flop of the next stage.

[0115] In some examples, the data input terminal D of the second flip-flop 302 may be configured to receive a second timing input signal (such as B_Dn), the clock signal terminal of the second flip-flop 302 may be configured to receive a second clock signal CKV2, the output terminal Q of the second flip-flop 302 is configured to output a first timing output signal (such as B_Qn), and the inverted output terminal Q_ of the second flip-flop 302 is configured to output an inverted signal of the second timing output signal. For example, the first timing input signal received by the second flip-flop of the start control circuit of the first-stage gate drive circuit may be a second initial start signal STV2. The first end of the third transmission gate 313 is connected to the data input terminal D of the second flip-flop 302 of this stage, and the second end of the third transmission gate 313 is connected to the output terminal of the second flip-flop of the next stage. The first end of the fourth transmission gate 314 is connected to the output terminal of the second flip-flop 302 of this stage, and the second end of the fourth transmission gate 314 is connected to the data input terminal of the second flip-flop of the next stage.

[0116] In some examples, the data input terminal D of the third flip-flop 303 may be configured to receive a third timing input signal (such as C_Dn), the clock signal terminal of the third flip-flop 303 may be configured to receive a third clock signal CKV3, the output terminal Q of the third flip-flop 303 is configured to output a third timing output signal (such as C_Qn), and the inverted output terminal Q_ of the third flip-flop 303 is configured to output an inverted signal of the first timing output signal. For example, the third timing input signal received by the third flip-flop of the start control circuit of the first-stage gate drive circuit may be a third initial start signal STV3. The first end of the fifth transmission gate 315 is connected to the data input terminal D of the third flip-flop 303 of this stage, and the second end of the fifth transmission gate 315 is connected to the output terminal of the third flip-flop of the next stage. The first end of the sixth transmission gate 316 is connected to the output terminal of the third flip-flop 303 of this stage, and the second end of the sixth transmission gate 316 is connected to the data input terminal of the third flip-flop of the next stage.

[0117] In some examples, the data input terminal D of the fourth flip-flop 304 may be configured to receive a fourth timing input signal (such as D_Dn), the clock signal terminal of the fourth flip-flop 304 may be configured to receive a fifth clock signal CKV5, the output terminal Q of the fourth flip-flop 304 is configured to output a fourth timing output signal (such as D_Qn), and the inverted output terminal Q_ of the fourth flip-flop 304 is configured to output an inverted signal of the fourth timing output signal (such as D_Qn'). For example, the fourth timing input signal received by the fourth flip-flop of the start control circuit of the first-stage gate drive circuit may be a fourth initial start signal. The first end of the seventh transmission gate 317 is connected to the data input terminal D of the fourth flip-flop 304 of this stage, and the second end of the seventh transmission gate 317 is connected to the output terminal of the fourth flip-flop of the next stage. The first end of the eighth transmission gate 318 is connected to the output terminal of the fourth flip-flop 304 of this stage, and the second end of the eighth transmission gate 318 is connected to the data input terminal of the fourth flip-flop of the next stage.

[0118] In some examples, taking the first transmission gate 311 as an example, the first transmission gate 311 is also connected to the transmission clock signal terminals GSD1 and GSD2. The first flip-flop 301, the second flip-flop 302, the third flip-flop 303, and the fourth flip-flop 304 may also be connected to the first reset terminal LF1 and configured to receive a first reset signal.

[0119] In some examples, for the primary gate driving circuit, the first timing output signal A_Qn output by the first flip-flop 301 can be used as the first start control signal and provided to the first arithmetic circuit; the second timing output signal B_Qn output by the second flip-flop 302 can be used as the second start control signal and provided to the first arithmetic circuit, the second arithmetic circuit, and the third arithmetic circuit; the third timing output signal C_Qn output by the third flip-flop 303 can be used as the third start control signal and provided to the first arithmetic circuit and the third arithmetic circuit. The fourth timing output signal D_Qn output by the fourth flip-flop 304 can be used as the duty ratio control signal and provided to the first arithmetic circuit, the second arithmetic circuit, and the third arithmetic circuit.

[0120] Figures 8A to 8D It is a timing diagram of the start control circuit according to at least one embodiment of the present disclosure. Figure 8A It shows the first row of the first timing input signal (such as A_Q1) generated by shifting the first timing input signal (such as A_D1) row by row through the first flip-flop and the inverted signals of the five rows of the first timing output signals (such as A_Q1’, A_Q2’, A_Q3’, A_Q4’, and A_Q5’). Figure 8B It shows the five rows of the second timing output signals (such as B_Q1, B_Q2, B_Q3, B_Q4, and B_Q5) generated by shifting the second timing input signal (such as B_D1) row by row through the second flip-flop. Figure 8C It shows the five rows of the third timing output signals (such as C_Q1, C_Q2, C_Q3, C_Q4, and C_Q5) generated by shifting the third timing input signal (such as C_D1) row by row through the third flip-flop. Figure 8D It shows the five rows of the fourth timing output signals (such as D_Q1, D_Q2, D_Q3, D_Q4, and D_Q5) generated by shifting the fourth timing input signal (such as D_D1) row by row through the fourth flip-flop.

[0121] In some examples, taking the first flip-flop as an example, the first timing input signal A_D1 can be shifted to form the first timing output signal A_Q1 and the inverted signal A_Q1’ of the first timing output signal after one clock cycle of the first clock signal CKV1. The rising edge of the signal A_Q1’ formed after one clock cycle shift is aligned with the falling edge of the signal A_Q4’ formed after four clock cycle shifts. Similarly, it can be obtained that the rising edge of the signal A_Qn’ can coincide with the falling edge of the signal A_Qn+4’. The shifted signals obtained by the second flip-flop and the third flip-flop have a similar relationship, so they will not be elaborated here.

[0122] Figure 8E It is a timing relationship diagram of multiple timing output signals according to at least one embodiment of the present disclosure. In some examples, such as Figure 8EAs shown, the signals obtained by performing logical operations on the inverted signal A_Q1' of the first timing output signal, the second timing output signal B_Q1, and the third timing output signal C_Q1 can satisfy the phase relationships of the first scan signal, the second scan signal, and the third scan signal required by the pixel circuit. For example, the first timing moment t11 and the second timing moment t12 can define the duration of the first scan control pulse of the first scan signal, and the third timing moment t13 and the fourth timing moment t14 can define the duration of the second scan control pulse of the first scan signal.

[0123] Figure 9A and Figure 9B is a schematic diagram of the timing setting of the initial start signal of at least one embodiment of the present disclosure. In some examples, the initial start signal has a period of one frame. The stages (STATE) of one frame period can include: a display stage (DISPLAY) and a vertical blanking stage, and the vertical blanking stage can include a vertical front porch (VFP, Vertical Front Porch) and a vertical back porch (VBP, Vertical Back Porch). The vertical front porch refers to the time interval between the start moment of a frame of image and the start moment of valid image data. The vertical back porch refers to the time interval between the end moment of valid image data of a frame of image and the end moment of a frame of image. Figure 9A In [description], the vertical synchronization signal VSYNC is used to indicate the start and end of the vertical scan of each image frame. The time interval between the start moments of two adjacent pulses of the vertical synchronization signal VSYNC is the duration of one frame period. The horizontal synchronization signal HSYNC is used to indicate the start and end of the horizontal scan between each image row. The time interval between the start moments of two adjacent pulses of the horizontal synchronization signal HSYNC is the duration of one row period (1H). Figure 9A In [description], an example is given where the vertical front porch includes a duration of four row periods (for example, rows 0 to 3), the vertical back porch includes a duration of four row periods (for example, rows N - 4 to N - 1), and rows 4 to N - 5 are valid image data.

[0124] In some examples, Figure 9A schematically shows three adjustment modes of the initial start signal. In the first adjustment mode (i.e., STVn_SL_SEL = 0), the shift parameter STVn_SL of the initial start signal is the number of row periods by which the start moment of the timing pulse is delayed within one frame period relative to the reference moment (for example, the start moment of the vertical synchronization signal VSYNC). For example, the value of STVn_SL is two row periods; the first pulse parameter STVn_HI of the initial start signal is the duration of the timing pulse within one frame period. For example, the value of STVn_HI is the duration of four row periods.

[0125] In the second adjustment mode (i.e., STVn_SL_SEL = 1), the shift parameter STVn_SL of the initial start signal is the number of line periods by which the start time of the timing pulse within one frame period is advanced relative to the reference time (e.g., the start time of the valid image data, such as the start time of the fourth line as shown in Figure 8A ). For example, the value of STVn_SL is two line periods; the first pulse parameter STVn_HI of the initial start signal is the duration of the timing pulse within one frame period. For example, the value of STVn_HI is four line periods.

[0126] In the third adjustment mode (i.e., STVn_SL_SEL = 2), the shift parameter STVn_SL of the initial start signal is the number of line periods by which the start time of the timing pulse within one frame period is delayed relative to the reference time (e.g., the start time of the valid image data, such as the start time of the fourth line as shown in Figure 8A ). For example, the value of STVn_SL is two line periods; the first pulse parameter STVn_HI of the initial start signal is the duration of the timing pulse within one frame period. For example, the value of STVn_HI is four line periods.

[0127] In some examples, Figure 9B illustrates two cases of the initial start signal within one line period. In the first case SLPC_STV, the timing pulse of the initial start signal is within a single line period. In the second case MLPC_STV, the timing pulse of the initial start signal can be within multiple line periods (e.g., within two line periods). Among them, the second pulse parameter STVn_RE of the initial start signal is the duration between the start time of one line period and the start time of the timing pulse; the third pulse parameter STVn_FE is the duration between the start time of one line period and the end time of the timing pulse. For example, the value units of the second pulse parameter and the third pulse parameter can be nanoseconds.

[0128] In some examples, the phase and duty cycle of the initial start signal can be determined by configuring the shift parameter STVn_SL, the first pulse parameter STVn_HI, the second pulse parameter STVn_RE, and the third pulse parameter STVn_FE of the initial start signal. At least one parameter of at least two of the first initial start signal STV1, the second initial start signal STV2, and the third initial start signal STV3 can be different, so that the phases and duty cycles of the first initial start signal STV1, the second initial start signal STV2, and the third initial start signal STV3 can be different. In this example, by setting the parameters of the first initial start signal STV1, the second initial start signal STV2, and the third initial start signal STV3, write switch signals, display switch signals, and display reset signals that meet the requirements can be generated, so that the first scan signal, the second scan signal, and the third scan signal can control the pixel circuit.

[0129] Figure 10 This is the working principle diagram of the first scan signal generation circuit of at least one embodiment of the present disclosure. In some examples, as Figure 10 shown, the first scan signal generation circuit may include: a first arithmetic circuit. The first arithmetic circuit may include nine parts, and the nine parts may include 4 inverters (Inverter, abbreviated as INV X), 3 NOR gates (NOR Gate, abbreviated as NOR), 1 NAND gate (NAND gate, abbreviated as NAND), and 1 two-way selector (MUX2). As Figure 10 shown, the first arithmetic circuit may include: a first NAND gate 511, a first NOR gate 501, a second NOR gate 502, a third NOR gate 503, a first inverter 401, a second inverter 402, a third inverter 403, a fourth inverter 404, and a two-way selector 530.

[0130] In some examples, the first input terminal of the first NAND gate 511 is configured to receive the second timing output signal B_Qn (i.e., the second start control signal) generated by the start control circuit, and the second input terminal is configured to receive the third timing output signal C_Qn (i.e., the third start control signal) generated by the start control circuit. The output terminal of the first NAND gate 511 is connected to the input terminal of the first inverter 401, and the output terminal of the first inverter 401 is connected to the first input terminal of the first NOR gate 501. The second input terminal of the first NOR gate 501 is configured to receive the first timing output signal A_Qn (i.e., the first start control signal) generated by the start control circuit. The output terminal of the first NOR gate 501 is connected to the input terminal of the second inverter 402, and the output terminal of the second inverter 402 is connected to the first input terminal of the second NOR gate 502. The second input terminal of the second NOR gate 502 is configured to receive the fourth clock signal CKV4. The output terminal of the second NOR gate 502 is connected to the input terminal of the third inverter 403, and the output terminal of the third inverter 403 is connected to the second input terminal of the two-way selector 530. The input terminal of the fourth inverter 404 is configured to receive the second reset signal LF_PUSLE2, and the output terminal of the fourth inverter 404 is connected to the second input terminal of the third NOR gate 503. The first input terminal of the third NOR gate 503 is configured to receive the first reset signal LF_PUSLE1, and the output terminal of the third NOR gate 503 is connected to the control terminal of the two-way selector 530. The first input terminal of the two-way selector 530 is configured to receive the first timing output signal A_Qn, and the output terminal of the two-way selector 530 serves as the output terminal OUT_WS of the first arithmetic circuit.

[0131] In some examples, the working principle of the first arithmetic circuit is as follows: The first NAND gate 511 and the first inverter 401 perform an AND operation on the second timing output signal B_Qn and the third timing output signal C_Qn. The first NOR gate 501 and the second inverter 402 perform an OR operation on the AND operation result and the first timing output signal A_Qn. The second NOR gate 502 and the third inverter 403 perform an OR operation on the OR operation result and the fourth clock signal CKV4. The fourth inverter 404 performs an inversion process on the second reset signal LF_PUSLE2, and the third NOR gate 503 performs a NOR operation on the inversion process result and the first reset signal LF_PUSLE1. The output signal of the third NOR gate 503 serves as the control signal of the two-way selector 530. When the third NOR gate 503 outputs a high level, the output terminal of the two-way selector 530 outputs the first timing output signal A_Qn. When the third NOR gate 503 outputs a low level, the output terminal of the two-way selector 530 outputs the output signal of the third inverter 403.

[0132] In some examples, such as Figure 10As shown, the first scan signal generation circuit may further include: a first level converter 221, a first row driving enhancer 231, and a first test circuit 241. The input end of the first level converter 221 is connected to the output end OUT_WS of the first arithmetic circuit. The first output end of the first level converter 221 is connected to the first input end of the first row driving enhancer 231, and the second output end of the first level converter 221 is connected to the second input end of the first row driving enhancer 231. The output end of the first row driving enhancer 231 may serve as the output end OUT1 of the first scan signal generation circuit. The first level converter 221 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the ground line GND. The first row driving enhancer 231 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the first enable line DR1_EN.

[0133] In some examples, the first test circuit 241 may include a fifth inverter 405 and a sixth inverter 406. The input end of the fifth inverter 405 may be connected to the output end OUT_WS of the first arithmetic circuit. The output end of the fifth inverter 405 is connected to the input end of the sixth inverter 406, and the output end of the sixth inverter 406 serves as the output end TEST_WS of the first test circuit. The output signal of the output end TEST_WS of the first test circuit 241 may be led out from the display substrate through a trace, which is convenient for detecting whether the first arithmetic circuit of the logic arithmetic circuit is working properly.

[0134] Figure 11 It is a timing diagram of the first arithmetic circuit according to at least one embodiment of the present disclosure. Figure 11 It shows the inverted signals (such as A_Q1’, A_Q2’, A_Q3’, A_Q4’), the second timing output signals (such as B_Q1, B_Q2, B_Q3, B_Q4), the third timing output signals (such as C_Q1, C_Q2, C_Q3, C_Q4), and the write switch signals (such as WS1, WS2, WS3, WS4) generated by the first-stage to fourth-stage gate driving circuits. In some examples, Figure 10 As can be seen, the write switch signal WSn generated by the first arithmetic circuit is WSn = B_Qn & C_Qn + A_Qn', where, “+” represents a logical OR operation, and “&” represents a logical AND operation. From Figure 11It can be obtained that the falling edge of the inverted signal A_Qn' of the first timing output signal (e.g., corresponding to the starting moment of the timing pulse) determines the falling edge of the first pulse of the write switch signal WSn (i.e., the first scan control pulse), the rising edge of the second timing output signal B_Qn (e.g., corresponding to the starting moment of the timing pulse) determines the falling edge of the first pulse of the write switch signal WSn, the falling edge of the third timing output signal C_Qn (corresponding to the ending moment of the timing pulse) determines the falling edge of the second pulse of the write switch signal WSn (i.e., the second scan control pulse), and the rising edge of the inverted signal A_Qn' of the first timing output signal determines the rising edge of the second pulse of the write switch signal WSn. Therefore, by simultaneously increasing (or decreasing) the pulse widths of the timing pulses of the inverted signal A_Qn' of the first timing output signal, the second timing output signal B_Qn, and the third timing output signal C_Qn by at least one line period duration, the duration from the rising edge of the first pulse to the falling edge of the second pulse of the write switch signal WSn will also increase (or decrease) by at least one line period duration. In this example, by adjusting the pulse widths of the timing pulses of the inverted signal A_Qn' of the first timing output signal, the second timing output signal B_Qn, and the third timing output signal C_Qn, the distance between the two pulses of the write switch signal WSn can be increased in units of one line period duration. The pulse widths of the first pulses of the write switch signals generated by different-level gate driving circuits are the same, and the pulse widths of the second pulses of the write switch signals generated by different-level gate driving circuits are the same. The pulse width of the first pulse of the write switch signal generated by each level of gate driving circuit can be less than or equal to the pulse width of the second pulse.

[0135] Combined with the timing diagram of the pixel circuit, it can be known that the starting moment of the self-discharge duration of the pixel circuit can be controlled by the rising edge of the first pulse of the first scan signal and the rising edge of the second scan signal, and the ending moment of the self-discharge duration can be controlled by the falling edge of the second pulse of the first scan signal. The first pulse of the first scan signal is controlled by the first scan control pulse of the write switch signal, the second pulse of the first scan signal is controlled by the second scan control pulse of the write switch signal, and the effective level of the second scan signal is controlled by the third scan control pulse of the display switch signal. To meet the purpose of adjusting the self-discharge duration, on the basis of the movement of the rising edge of the first scan control pulse of the write switch signal WSn, moving the rising edge of the display switch signal DSn by the same duration can ensure the phase relationship between the first scan signal and the second scan signal.

[0136] Figure 12 For the working principle diagram of the second scan signal generation circuit of at least one embodiment of the present disclosure. In some examples, such as Figure 12As shown, the second scan signal generation circuit may include: a second arithmetic circuit. The second arithmetic circuit may include six inverters, one NOR gate, one NAND gate, and one latch (D-Latch). As Figure 12 As shown, the second arithmetic circuit may include a second NAND gate 512, a latch 305, a fourth NOR gate 504, and a delay circuit. The delay circuit may include: a seventh inverter 407, an eighth inverter 408, a ninth inverter 409, a tenth inverter 410, an eleventh inverter 411, and a twelfth inverter 412.

[0137] In some examples, the input terminal of the seventh inverter 407 is connected to the output terminal OUT_WS of the first arithmetic circuit to receive the write switch signal WSn output by the first arithmetic circuit. The output terminal of the seventh inverter 407 is connected to the input terminal of the eighth inverter 408. The output terminal of the eighth inverter 408 is connected to the input terminal of the ninth inverter 409. The output terminal of the ninth inverter 409 is connected to the input terminal of the tenth inverter 410. The output terminal of the tenth inverter 410 is connected to the input terminal of the eleventh inverter 411. The output terminal of the eleventh inverter 411 is connected to the input terminal of the twelfth inverter 412. The output terminal of the twelfth inverter 412 is connected to the enable input terminal EN of the latch 305. The data input terminal of the latch 305 is configured to receive the second timing output signal B_Qn. The output terminal of the latch 305 is connected to the second input terminal of the fourth NOR gate 504. The first input terminal of the fourth NOR gate 504 is connected to the inverted signal D_Qn' of the duty ratio control signal. The output terminal of the fourth NOR gate 504 is connected to the first input terminal of the second NAND gate 512. The second input terminal of the second NAND gate 512 is configured to receive the second reset signal LF_PUSLE2. The output terminal of the second NAND gate 512 serves as the output terminal OUT_DS of the second arithmetic circuit.

[0138] In some examples, the operating principle of the second arithmetic circuit is as follows: The seventh inverter 407 to the twelfth inverter 412 delay the input signal WSn of the second arithmetic circuit and then input it to the enable input terminal EN of the latch 305 as the enable signal of the latch 305. The second timing output signal B_Qn serves as the input signal of the latch 305. When the enable signal of the enable input terminal EN is at a low level, the output of the latch 305 remains unchanged. When the enable signal of the enable input terminal EN is at a high level, the output of the latch 305 changes with the second timing output signal. Subsequently, the fourth NOR gate 504 performs a NOR operation on the inverted signal D_Qn' of the duty ratio control signal and the output signal of the latch 305. The second NAND gate 512 performs a NAND operation on the NOR operation result and the second reset signal of the second reset terminal LF2. Its logical expression is: Among them, "+" represents a logical OR operation, "&" represents a logical AND operation, and the overline represents a logical NOT operation. Among them, Q is the output signal of the latch 305, LF_PUSLE2 is the second reset signal, and in the normal working state, the output signal DSn of the second operation circuit is DSn = D_Qn'+Q. When a global reset is required, DSn = 0 for global reset. When the light-emitting time ratio is 100%, D_Qn' remains low, so DSn = Q = B_Qn. When it is necessary to adjust the light-emitting time ratio, it can be achieved by adjusting the duty cycle of D_Qn. Therefore, the display switch signal DSn is determined by the second timing output signal B_Qn. The rising edge of the display switch signal DSn will move synchronously with the rising edge of the first pulse of the write switch signal WSn, so as to ensure the relative relationship between the display switch signal and the write switch signal and realize the adjustment of the self-discharge duration.

[0139] In some examples, such as Figure 12 shown, the second scan signal generation circuit may further include: a second level converter 222, a second row driving enhancer 232, and a second test circuit 242. The input end of the second level converter 222 is connected to the output end OUT_DS of the second operation circuit, the first output end of the second level converter 222 is connected to the first input end of the second row driving enhancer 232, the second output end of the second level converter 222 is connected to the second input end of the second row driving enhancer 232, and the output end of the second row driving enhancer 232 can be used as the output end OUT2 of the second scan signal generation circuit. The second level converter 222 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the ground line GND. The second row driving enhancer 232 may also be connected to the first power supply line VDD, the second power supply line VSS2, and the second enable line DR2_EN.

[0140] In some examples, the second test circuit 242 may include a thirteenth inverter 413 and a fourteenth inverter 414. The input end of the thirteenth inverter 413 may be connected to the output end OUT_DS of the second operation circuit, the output end of the thirteenth inverter 413 is connected to the input end of the fourteenth inverter 414, and the output end of the fourteenth inverter 414 serves as the output end TEST_DS of the second test circuit 242. The output signal of the output end TEST_DS of the second test circuit 242 can be led out from the display substrate through a trace, which is convenient for detecting whether the second operation circuit of the logic operation circuit is working properly.

[0141] Figure 13 This is the working principle diagram of the third scan signal generation circuit of at least one embodiment of the present disclosure. In some examples, the third scan signal generation circuit may include a third operation circuit, and the third operation circuit may include 1 NOR gate and 1 NAND gate. Such as Figure 13As shown, the third arithmetic circuit may include a fifth NOR gate 505 and a third NAND gate 513.

[0142] In some examples, the first input terminal of the fifth NOR gate 505 is configured to receive a third timing output signal C_Qn (i.e., the third start control signal), the second input terminal of the fifth NOR gate 505 is configured to receive a second timing output signal B_Qn (i.e., the second start control signal), the third input terminal of the fifth NOR gate 505 is configured to be connected to a duty ratio control signal D_Qn, the output terminal of the fifth NOR gate 505 is connected to the first input terminal of the third NAND gate 513, the second input terminal of the third NAND gate 513 is configured to receive a second reset signal LF_PUSLE2, and the output terminal of the third NAND gate 513 serves as the output terminal OUT_AZ of the third arithmetic circuit.

[0143] In some examples, the operating principle of the third arithmetic circuit is as follows: The fifth NOR gate 505 performs a NOR operation on the third timing output signal C_Qn, the second timing output signal B_Qn, and the duty ratio control signal D_Qn, and the third NAND gate 513 performs a NAND operation on the NOR operation result and the second reset signal LF_PUSLE2. Its logical expression is: where, "+" represents a logical OR operation, "&" represents a logical AND operation, and the overline represents a logical NOT operation. Among them, LF_PUSLE2 is the second reset signal, which remains high in the normal operating state, then AZn = B_Qn + C_Qn + D_Qn. Assuming D_Qn = 1, then AZn = B_Qn + C_Qn. When the pulse widths of the second timing output signal B_Qn and the third timing output signal C_Qn increase (or decrease) by at least one line period simultaneously, it can be seen that the rising edge of the display reset signal AZn will also move, thereby ensuring the phase relationship between the display reset signal AZn and the write switch signal WSn.

[0144] In some examples, as Figure 13 shown, the third scan signal generation circuit may further include: a third level converter 223, a third row driving enhancer 233, and a third test circuit 243. The input terminal of the third level converter 223 is connected to the output terminal OUT_AZ of the third arithmetic circuit. The first output terminal of the third level converter 223 is connected to the first input terminal of the third row driving enhancer 233, and the second output terminal of the third level converter 223 is connected to the second input terminal of the third row driving enhancer 233. The output terminal of the third row driving enhancer 233 may serve as the output terminal OUT3 of the third scan signal generation circuit. The third level converter 223 may also be connected to a first power supply line VDD, a second power supply line VSS2, and a ground line GND. The third row driving enhancer 233 may also be connected to the first power supply line VDD, the second power supply line VSS2, and a third enable line DR3_EN.

[0145] In some examples, the third test circuit 243 may include a fifteenth inverter 415 and a sixteenth inverter 416. The input terminal of the fifteenth inverter 415 may be connected to the output terminal OUT_AZ of the third arithmetic circuit. The output terminal of the fifteenth inverter 415 is connected to the input terminal of the sixteenth inverter 416, and the output terminal of the sixteenth inverter 416 serves as the output terminal TEST_AZ of the third test circuit 243. The output signal of the output terminal TEST_AZ of the third test circuit 243 may be led out from the display substrate through a trace, which is convenient for detecting whether the third arithmetic circuit of the logic arithmetic circuit is working properly.

[0146] In some examples, the settings of the first initial start signal STV1, the second initial start signal STV2, and the third initial start signal STV3 may be as shown in Table 1.

[0147] Table 1

[0148]

[0149] Figure 14 This is the timing diagram of the operation of the gate driving circuit according to at least one embodiment of the present disclosure. Figure 15 is Figure 14 a partial schematic diagram of Figure 14 and Figure 15 is the timing diagram of the operation of the gate driving circuit with the settings shown in Table 1. Figure 14 and Figure 15 In [diagrams not shown], SSW1, SSW2, SSW3, SSW4, SSW5, and SSW6 are control signals of the multiplexing circuit. For example, the multiplexing circuit may adopt a 1:6 design. Figure 14 Schematically shows the timing relationship of the first initial start signal STV1, the second initial start signal STV2, the third initial start signal STV3, the first clock signal CKV1, the second clock signal CKV2, the third clock signal CKV3, the fourth clock signal CKV4, the output signals of the start control circuits of the first to third stage gate driving circuits (including A_Q1, A_Q1’, A_Q2’, A_Q3’, B_Q1, B_Q2, B_Q3, C_Q1, C_Q2, C_Q3), and the write switch signals (including WS1, WS2, WS3, WS4), display switch signals (including DS1, DS2, DS3, DS4), and display reset signals (including AZ1, AZ2, AZ3, AZ4) generated by the first to fourth stage gate driving circuits. Figure 15 Schematically shows the timing relationship of the write switch signals (including WS1, WS2, WS3), display switch signals (including DS1, DS2, DS3), and display reset signals (including AZ1, AZ2, AZ3) generated by the first to third stage gate driving circuits.

[0150] In some examples, such as Figure 14 and Figure 15 shown, with the settings shown in Table 1, the duration between the rising edge of the first pulse (i.e., the first scan control pulse) and the falling edge of the second pulse (i.e., the second scan control pulse) of the write switch signal DS1 (or DS2, DS3, DS4) generated by the gate drive circuit is greater than 2 line cycle durations and less than 3 line cycle durations, and the duration between the rising edge of the display switch signal WS1 (or WS2, WS3, WS4) and the falling edge of the second pulse of the write switch signal DS1 (or DS2, DS3, DS4) is greater than 2 line cycle durations and less than 3 line cycle durations. The rising edge of the display reset signal AZ1 (or AZ2, AZ3, AZ4) is earlier than the falling edge of the first pulse of the write switch signal DS1 (or DS2, DS3, DS4), and the falling edge of the display reset signal AZ1 (or AZ2, AZ3, AZ4) is later than the rising edge of the second pulse of the write switch signal DS1 (or DS2, DS3, DS4). The phase relationship of the write switch signal, the display switch signal, and the display reset signal generated by the gate drive circuit can achieve an increase in the self-discharge duration. For example, the first scan signal output by the first-stage gate drive circuit according to the write switch signal DS1, the second scan signal output according to the display switch signal WS1, and the third scan signal output according to the display reset signal AZ1 can be provided to the first row of pixel circuits, such that the first row of pixel circuits performs bias voltage writing during the vertical blanking period, and the self-discharge duration F1 of the first row of pixel circuits can be greater than 2 line cycle durations and less than 3 line cycle durations. The first scan signal output by the second-stage gate drive circuit according to the write switch signal DS2, the second scan signal output according to the display switch signal WS2, and the third scan signal output according to the display reset signal AZ2 can be provided to the second row of pixel circuits, such that the second row of pixel circuits performs bias voltage writing during the vertical blanking period, and the self-discharge duration F2 of the second row of pixel circuits can be greater than 2 line cycle durations and less than 3 line cycle durations. The first scan signal output by the third-stage gate drive circuit according to the write switch signal DS3, the second scan signal output according to the display switch signal WS3, and the third scan signal output according to the display reset signal AZ3 can be provided to the third row of pixel circuits, such that the self-discharge duration F3 of the third row of pixel circuits can be greater than 2 line cycle durations and less than 3 line cycle durations. The first scan signal output by the fourth-stage gate drive circuit according to the write switch signal DS4, the second scan signal output according to the display switch signal WS4, and the third scan signal output according to the display reset signal AZ4 can be provided to the third row of pixel circuits, such that the self-discharge duration F4 of the third row of pixel circuits can be greater than 2 line cycle durations and less than 3 line cycle durations.

[0151] Figure 16It is a timing relationship diagram of the start control signal and the scan control signal for at least one embodiment of the present disclosure. In some examples, as Figure 16 shown, the write switch signal WSn may include: a first scan control pulse K1 and a second scan control pulse K2. The display switch signal DSn may include: a third scan control pulse K3. The display reset signal AZn may include: a fourth scan control pulse K4. For example, the first scan control pulse K1 and the second scan control pulse K2 may be low-level pulses, and the third scan control pulse K3 and the fourth scan control pulse K4 may be high-level pulses.

[0152] In some examples, as Figure 16 shown, the first start control signal (i.e., the first timing output signal A_Qn), the second start control signal (i.e., the second timing output signal B_Qn), and the third start control signal (i.e., the third timing output signal C_Qn) may all include high-level timing pulses.

[0153] In some examples, the falling edge of the first scan control pulse K1 may be controlled by the rising edge of the first start control signal A_Qn, and the rising edge of the first scan control pulse K1 may be controlled by the rising edge of the second start control signal B_Qn. The falling edge of the second scan control pulse K2 may be controlled by the falling edge of the third start control signal C_Qn, and the rising edge of the second scan control pulse K2 may be controlled by the falling edge of the first start control signal A_Qn. The rising edge of the third scan control pulse K3 may be controlled by the rising edge of the second start control signal B_Qn, and the falling edge of the third scan control pulse K3 may be controlled by the falling edge of the second start control signal B_Qn. The rising edge of the fourth scan control pulse K4 may be controlled by the rising edge of the third start control signal C_Qn, and the falling edge of the fourth scan control pulse K4 may be controlled by the falling edge of the second start control signal B_Qn. As Figure 14 shown, the timing relationship of the write switch signal WS1, the display switch signal DS1, and the display reset signal AZ1 generated by the first-stage gate drive circuit may be controlled by the first start control signal A_Q1, the second start control signal B_Q1, and the third start control signal C_Q1; the timing relationship of the write switch signal WS2, the display switch signal DS2, and the display reset signal AZ2 generated by the second-stage gate drive circuit may be controlled by the first start control signal A_Q2, the second start control signal B_Q2, and the third start control signal C_Q2; the timing relationship of the write switch signal WS3, the display switch signal DS3, and the display reset signal AZ3 generated by the third-stage gate drive circuit may be controlled by the first start control signal A_Q3, the second start control signal B_Q3, and the third start control signal C_Q3.

[0154] In some examples, the settings of the first initial start signal STV1, the second initial start signal STV2, and the third initial start signal STV3 can be as shown in Table 2. With the settings shown in Table 2, the duration between the rising edge of the first pulse of the write switch signal (i.e., the first scan control pulse) and the falling edge of the second pulse (i.e., the second scan control pulse) generated by the gate driving circuit can be greater than 5 line cycle durations and less than 6 line cycle durations.

[0155] Table 2

[0156]

[0157]

[0158] In some examples, the duration between the end moment of the first pulse of the write switch signal and the start moment of the second pulse can be greater than M line cycle durations. The value of M can be the same as the parameter value of the shift parameter STV1_SL of the first initial start signal, and the parameter value of the shift parameter STV1_SL of the first initial start signal is the same as the parameter value of the shift parameter STV2_SL of the second initial start signal. For example, the value of M can be 2 or 5.

[0159] In some examples, when the light emission ratio is 100%, the duration between the start moment of the effective level of the third scan control pulse of the display switch signal and the start moment of the second pulse of the write switch signal can be the self-discharge duration. The self-discharge duration can be greater than or equal to at least one line cycle duration. The self-discharge duration can be greater than or equal to at least one line cycle duration and less than the duration of the vertical blanking period within one frame period. For example, the vertical blanking period can include VBP and VFP, and the duration of the vertical blanking period can be the sum of the line cycle durations of VBP and VFP. As the light emission ratio decreases, the self-discharge time can further increase. When the self-discharge duration is greater than 10 microseconds, the pixel circuit can achieve a relatively sufficient threshold voltage reading, and the degree of threshold voltage reading can be greater than 90%.

[0160] This embodiment also provides a driving method for a gate driving circuit, which is applied to the gate driving circuit as described above. The driving method includes: the start control circuit generates a plurality of start control signals; the signal generation circuit generates a plurality of scan control signals according to the plurality of start control signals, and provides the plurality of scan control signals to the pixel circuit after processing; wherein, the plurality of scan control signals include n scan control pulses, the pixel circuit is controlled by the n scan control pulses, and the n scan control pulses are controlled by log2(2n) start control signals, and n is an integer greater than 1. For the relevant description of the driving method of this embodiment, reference can be made to the description of the foregoing embodiment, so it will not be repeated here.

[0161] This embodiment also provides a display substrate, including a display area and a non-display area; the display area includes a plurality of sub-pixels, at least one sub-pixel includes a pixel circuit and at least one scanning signal line, and the scanning signal line is configured to provide a scanning signal to the connected pixel circuit; the non-display area includes a plurality of cascaded gate driving circuits, at least one gate driving circuit is connected to the scanning signal line in the display area, and at least one gate driving circuit includes the gate driving circuit as described above.

[0162] In some exemplary embodiments, within one frame period, the reference voltage written by the pixel circuit during the vertical blanking period is the same as the bias voltage written during the initialization period of the display period. In this example, by moving the initialization period of the first row of pixel circuits to the vertical blanking period, the vertical blanking period can be used to increase the self-discharge duration of the pixel circuit. The bias voltage of a part of the pixel circuits is written during the vertical blanking period, and the reference voltage during the vertical blanking period is fixed and non-adjustable. In order to ensure that the bias voltage written during the vertical blanking period is the same as the bias voltage written during the display period, the reference signal during the vertical blanking period can be set to be the same as the bias voltage.

[0163] For the related description of the display substrate provided in this embodiment, reference can be made to the description of the foregoing embodiments, so it will not be elaborated herein.

[0164] This exemplary embodiment of the present disclosure also provides a display device, including the foregoing display substrate. For example, the display device can be a silicon-based OLED display device. The display device of the present disclosure can be used in virtual reality (VR) devices, augmented reality (AR) devices, extended reality (XR) devices, mixed reality (MR) devices, sights and rangefinders, etc.

[0165] Although the disclosed embodiments are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the content shown and described herein. Various modifications, substitutions or omissions can be made to the form and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A gate driving circuit, characterized in that, Comprising: A start control circuit and a signal generation circuit; The start control circuit is configured to generate a plurality of start control signals; The signal generation circuit is connected to the start control circuit and is configured to generate a plurality of scan control signals according to the plurality of start control signals, and process the plurality of scan control signals and provide them to the pixel circuit; wherein, the plurality of scan control signals include n scan control pulses, the pixel circuit is controlled by the n scan control pulses, and the n scan control pulses are controlled by log2(2n) start control signals, and n is an integer greater than 1.

2. The gate driving circuit according to claim 1, wherein The value of n is 4.

3. The gate driving circuit according to claim 1, wherein The plurality of scan control signals include: a write switch signal, and the write switch signal includes: a first scan control pulse and a second scan control pulse; The first scan control pulse is configured to control the gate electrode of the driving transistor of the pixel circuit to write a bias voltage, and the second scan control pulse is configured to control the gate electrode of the driving transistor of the pixel circuit to write a data voltage; The plurality of start control signals include: a first start control signal, a second start control signal, and a third start control signal; the interval duration between the end moment of the first scan control pulse and the start moment of the second scan control pulse of the write switch signal is controlled by the pulse start moment of the second start control signal and the pulse end moment of the third start control signal.

4. The gate driving circuit according to claim 3, wherein Within one frame period, the interval duration between the end moment of the first scan control pulse and the start moment of the second scan control pulse of the write switch signal is greater than or equal to at least one line period duration.

5. The gate driving circuit according to claim 3, wherein The duration of the effective level of the first scan control pulse of the write switch signal is less than or equal to the duration of the effective level of the second scan control pulse.

6. The gate driving circuit according to claim 3, wherein The start moment of the first scan control pulse of the write switch signal is controlled by the pulse start moment of the first start control signal, and the end moment of the second scan control pulse is controlled by the pulse end moment of the first start control signal.

7. The gate driving circuit according to claim 3, wherein The plurality of scan control signals further include: a display switch signal, and the display switch signal includes: a third scan control pulse; the third scan control pulse is configured to control the driving transistor of the pixel circuit to perform self-discharge; the start moment and the end moment of the third scan control pulse are controlled by the second start control signal.

8. The gate driving circuit according to claim 7, wherein Within one frame period, the end moment of the first scan control pulse of the write switch signal is earlier than or equal to the start moment of the third scan control pulse of the display switch signal, and the end moment of the third scan control pulse is later than the end moment of the second scan control pulse of the write switch signal; The duration between the start moment of the third scan control pulse and the start moment of the second scan control pulse is the self-discharge duration, and the self-discharge duration is greater than or equal to at least one line period duration and less than the duration of the vertical blanking stage within one frame period.

9. The gate driving circuit according to claim 3, wherein The multiple scan control signals further include: a display reset signal, and the display reset signal includes: a fourth scan control pulse; the fourth scan control pulse is configured to control the conduction or disconnection of a display reset transistor of the pixel circuit; The start time of the fourth scan control pulse is controlled by the pulse start time of the third start control signal, and the end time of the fourth scan control pulse is controlled by the pulse end time of the second start control signal.

10. The gate driving circuit according to any one of claims 3 to 9, characterized in that, Each start control signal is configured to be controlled by a corresponding initial start signal and a clock signal; The initial start signal is configured to be set by at least one of the following parameters: a shift parameter, a first pulse parameter, a second pulse parameter, and a third pulse parameter; The shift parameter is the number of line periods of the start time of a timing pulse relative to a reference time within one frame period; The first pulse parameter is the duration of the timing pulse within one frame period; The second pulse parameter is the duration between the start time of one line period and the start time of the timing pulse; The third pulse parameter is the duration between the start time of one line period and the end time of the timing pulse.

11. The gate driving circuit according to claim 10, characterized in that, The first start control signal is configured to be controlled by a first initial start signal and a first clock signal, and the second start control signal is configured to be controlled by a second initial start signal and a second clock signal; The interval duration between the end time of the first scan control pulse and the start time of the second scan control pulse of the write switch signal is greater than M line period durations, and the value of M is the same as the parameter value of the shift parameter of the first initial start signal; the parameter value of the shift parameter of the first initial start signal is the same as the parameter value of the shift parameter of the second initial start signal.

12. The gate driving circuit according to claim 3, wherein The signal generation circuit includes: a first arithmetic circuit, and the first arithmetic circuit includes: a first NAND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, a second inverter, a third inverter, a fourth inverter, and a two-way selector; Wherein, the first input terminal of the first NAND gate is configured to receive the second start control signal, the second input terminal of the first NAND gate is configured to receive the third start control signal, the output terminal of the first NAND gate is connected to the input terminal of the first inverter, the output terminal of the first inverter is connected to the first input terminal of the first NOR gate, the second input terminal of the first NOR gate is configured to receive the first start control signal, the output terminal of the first NOR gate is connected to the input terminal of the second inverter, the output terminal of the second inverter is connected to the first input terminal of the second NOR gate, the second input terminal of the second NOR gate is configured to receive a fourth clock signal, the output terminal of the second NOR gate is connected to the input terminal of the third inverter, the output terminal of the third inverter is connected to the second input terminal of the two-way selector, and the first input terminal of the two-way selector is configured to receive the first start control signal; The input terminal of the fourth inverter is configured to receive a second reset signal. The output terminal of the fourth inverter is connected to the second input terminal of the third NOR gate. The first input terminal of the third NOR gate is configured to receive a first reset signal. The output terminal of the third NOR gate is connected to the control terminal of the two-way selector. The output terminal of the two-way selector is configured to output the write switch signal.

13. The gate driving circuit according to claim 7, wherein The signal generation circuit includes: a second arithmetic circuit. The second arithmetic circuit includes: a latch, a second NAND gate, a fourth NOR gate, and a delay circuit. The input terminal of the delay circuit is configured to receive the write switch signal. The output terminal of the delay circuit is connected to the enable input terminal of the latch. The data input terminal of the latch is configured to receive the second start control signal. The output terminal of the latch is connected to the second input terminal of the fourth NOR gate. The first input terminal of the fourth NOR gate is configured to receive the inverted signal of the duty ratio control signal. The output terminal of the fourth NOR gate is connected to the first input terminal of the second NAND gate. The second input terminal of the second NAND gate is configured to receive the second reset signal. The output terminal of the second NAND gate is configured to output the display switch signal.

14. The gate driving circuit according to claim 9, wherein The signal generation circuit includes: a third arithmetic circuit. The third arithmetic circuit is connected to the start control circuit and is configured to perform a logical OR operation on the second start control signal and the third start control signal to generate the display reset signal.

15. A driving method for a gate driving circuit, characterized in that, Applied to the gate driving circuit according to any one of claims 1 to 14. The driving method includes: The start control circuit generates a plurality of start control signals. The signal generation circuit generates a plurality of scan control signals according to the plurality of start control signals, and processes the plurality of scan control signals and provides them to the pixel circuit. Wherein, the plurality of scan control signals include n scan control pulses. The pixel circuit is controlled by the n scan control pulses. The n scan control pulses are controlled by log2(2n) start control signals, and n is an integer greater than 1.

16. A display substrate, characterized in that Including a display area and a non-display area. The display area includes a plurality of sub-pixels. At least one sub-pixel includes a pixel circuit and at least one scan signal line. The scan signal line is configured to provide a scan signal to the connected pixel circuit. The non-display area includes a plurality of cascaded gate driving circuits. At least one gate driving circuit is connected to the scan signal line in the display area. At least one gate driving circuit includes the gate driving circuit according to any one of claims 1 to 14.

17. The display substrate according to claim 16, wherein Within one frame period, the reference voltage written by the pixel circuit during the vertical blanking period is the same as the bias voltage written during the initialization period of the display period.

18. A display device, characterized in that, Including the display substrate according to any one of claims 16 to 17.

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