Memory system

Abstract

A memory system according to an embodiment outputs read enable signals RE and / RE during a standby time tWHR2 required for processing for outputting to a controller, and outputs dummy data preset in signals DQS and / or DQS and DQ from an output circuit.

Description

[0001] Relevant information of divisional application

[0002] This is a divisional application. The parent case of this divisional application is a patent application for an invention titled "Memory System" with an application date of September 13, 2019, an application number of 201980098583.7. Technical Field

[0003] The embodiment relates to a memory system. Background Art

[0004] A NAND (Not-AND) type flash memory known as a semiconductor memory device is known.

[0005] [Prior Art Documents]

[0006] [Patent Documents]

[0007] Patent Document 1: Specification of U.S. Patent No. 8913448 Summary of the Invention

[0008] [Problems to be Solved by the Invention]

[0009] The embodiment provides a memory system capable of improving the read reliability of data.

[0010] [Technical Means for Solving the Problems]

[0011] The memory system of the embodiment includes: a semiconductor memory; and a controller that gives an instruction to read data from the semiconductor memory; and the semiconductor memory includes: memory cell transistors that hold data; an output circuit that processes data read from the memory cell transistors for output to the controller; and a data generation circuit that generates first data; and when reading the data, the controller outputs a first signal to the semiconductor memory during a first period in which the output circuit performs the processing, the semiconductor memory generates a second signal based on the first signal, outputs the first data and the second signal to the controller during the period between the first period and a second period, and after the end of the second period, the semiconductor memory outputs data read from the memory cell transistors and the second signal to the controller. Brief Description of the Drawings

[0012] Figure 1 It is a block diagram conceptually showing the overall configuration of the memory system of the embodiment.

[0013] Figure 2 It is a block diagram showing a configuration example of a NAND type flash memory.

[0014] Figure 3 It is a circuit diagram showing a configuration example of a memory cell array of a NAND flash memory.

[0015] Figure 4 It is a block diagram showing a configuration example of an output circuit.

[0016] Figure 5 It is a flowchart of a comparative object example with the embodiment.

[0017] Figure 6A It is a timing diagram for explaining the data output operation of the comparative object example with the embodiment.

[0018] Figure 6B It is a timing diagram for explaining the stabilization of the power output of the data output operation of the first embodiment.

[0019] Figure 7 It is a flowchart for explaining the stabilization of the power output of the data output operation of the first embodiment.

[0020] Figure 8 It is a timing diagram showing the timing of each signal of the standby time and delay time of the first setting example.

[0021] Figure 9 It is a timing diagram showing the timing of each signal of the standby time and delay time of the second setting example.

[0022] Figure 10 It is a timing diagram showing the timing of each signal of the standby time and delay time of the third setting example.

[0023] Figure 11 It is a timing diagram showing the timing of each signal of the standby time and delay time of the fourth setting example.

[0024] Figure 12 It is a flowchart for explaining the stabilization of the power output of the data output operation of the second embodiment.

[0025] Figure 13 It is a flowchart for explaining the stabilization of the power output of the data output operation of the third embodiment.

[0026] Figure 14 It is a flowchart for explaining the stabilization of the power output of the data output operation of the fourth embodiment.

[0027] Figure 15 It is a timing diagram showing the timing of each signal of the electrical standby time and delay time of the fifth embodiment. Detailed Embodiments

[0028] Hereinafter, the embodiments will be described with reference to the accompanying drawings.

[0029] Embodiments illustrate devices for embodying the technical idea of the invention. The accompanying drawings are schematic or conceptual, and the dimensions and ratios of each drawing are not necessarily the same as those of the actual object. Moreover, the technical idea of the present invention is not specified by the shape, structure, configuration, etc. of the constituent elements. In addition, in the following description, constituent elements having substantially the same functions and configurations are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0030] [First Embodiment]

[0031] The memory system of the first embodiment will be described.

[0032] <Overall Configuration of Memory System>

[0033] Figure 1 It is a block diagram conceptually showing the overall configuration of the memory system 1 of this embodiment.

[0034] The memory system 1 of this embodiment includes at least a semiconductor memory 3 and a memory controller (controller) 2 that controls the semiconductor memory 3. In this embodiment, the semiconductor memory 3 only needs to be a non-volatile memory, and preferably, for example, a NAND flash memory. In the following description, an example in which a NAND flash memory 3 is applied as a semiconductor storage device will be described.

[0035] The memory controller 2 and the NAND flash memory 3 can be combined to form one semiconductor device. As an example thereof, there is a memory card such as an SD (Secure Digital) TM card, or an SSD (solid state drive), etc. In addition, the memory controller 2 can use an SoC (system on chip), etc.

[0036] The NAND flash memory 3 includes a plurality of memory cell transistors and stores data non-volatilely. The memory controller 2 is connected to the NAND flash memory 3 via a NAND bus. In addition, the memory controller 2 is also connected to an external host machine 4 via a host bus. The memory controller 2 controls the NAND flash memory 3 and accesses the NAND flash memory 3 in response to a command received from the host machine 4. The host machine 4 is, for example, a digital camera or a personal computer, etc., and the host bus is a bus based on, for example, SD TM interface. The NAND bus performs signal transmission and reception based on the NAND interface.

[0037] <Configuration of Memory Controller 2>

[0038] Refer to Figure 1 , and the details of the configuration of the memory controller 2 will be described.

[0039] The memory controller 2 controls the NAND flash memory 3. As a specific example, the memory controller 2 controls writing data to the NAND flash memory 3 and reading the stored data from the NAND flash memory 3.

[0040] The memory controller 2 includes a host interface circuit (host I / F) 5, an internal memory (RAM: Random Access Memory) 6, a processor (CPU: Central Processing Unit) 7, a buffer memory 8, a NAND interface circuit (NAND I / F) 9, and an ECC (Error Checking and Correcting) circuit 10. In addition, various other components are mounted according to the design.

[0041] The host interface circuit 5 is connected to the host machine 4 via a host bus, and transmits the commands and data received from the host machine 4 to the processor 7 and the buffer memory 8, respectively. Further, according to the command of the processor 7, the data in the buffer memory 8 is transmitted to the host machine 4.

[0042] The processor 7 controls the overall operation of the memory controller 2. For example, when the processor 7 receives a command to write data from the host machine 4, it issues a write command to the NAND interface circuit 9 based on the reception. The same applies to data reading and erasing. Further, the processor 7 executes various processes for managing the NAND flash memory 3, such as wear leveling. In addition, the operations of the memory controller 2 described below can be implemented by the processor 7 executing software (firmware), or can also be implemented by hardware.

[0043] The NAND interface circuit 9 is connected to the NAND flash memory 3 via a NAND bus and is responsible for communication with the NAND flash memory 3. Further, the NAND interface circuit 9 transmits and receives various signals to and from the NAND flash memory 3 based on the commands received from the processor 7. The buffer memory 8 temporarily holds the write data or the read data.

[0044] The internal memory (RAM) 6 is a semiconductor memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), and is used as a working area for the processor 7. Further, the internal memory 6 holds the firmware for managing the NAND flash memory 3, various management tables, and the like.

[0045] The ECC circuit 10 performs error detection and error correction processing related to the data stored in the NAND flash memory 3. That is, the ECC circuit 10 generates an error correction code when writing data, and gives it to the written data. When reading data, the error correction code is decoded.

[0046] <NAND Bus of NAND Flash Memory>

[0047] Reference Figure 2 , the NAND bus will be described.

[0048] The memory controller 2 and the NAND flash memory 3 are connected through the NAND bus. The NAND bus includes a plurality of signal lines, which are divided into a signal line group connected to the input / output pad group 21 connected to the input / output circuit 12, and a signal line group connected to the logic control pad group 22 connected to the logic control circuit 13.

[0049] The signal lines transmit and receive a chip enable signal / CE, an instruction latch enable signal CLE, an address latch enable signal ALE, a write enable signal / WE, a read enable signal / RE, a write protection signal / WP, and a ready / busy signal / RB, a data signal DQ, a data strobe signal DQS, and / DQS according to the NAND interface. The signals CLE, ALE, / WE, / RE, and / WP are received by the NAND flash memory 3. Moreover, the signal / RB and the signal / CE are respectively received by the NAND flash memory 3.

[0050] The chip enable signal / CE is a signal used to enable the NAND flash memory 3. The instruction latch enable signal CLE can latch an instruction CMD transmitted as the data signal DQ into an instruction register 15A of a register 15 described later. The signal CLE notifies the NAND flash memory 3 that the signal DQ flowing into the NAND flash memory 3 during the period when the signal CLE is at the "H (High)" level is the instruction CMD. The signal DQ is, for example, an 8-bit signal.

[0051] The address latch enable signal ALE can latch an address ADD transmitted as the data signal DQ into an address register 15B of a register 15 described later. The signal ALE notifies the NAND flash memory 3 that the signal DQ transmitted to the NAND flash memory 3 during the period when the signal ALE is at the "H" level is the address ADD. The write enable signal / WE enables writing. The signal / WE instructs to extract the signal DQ transmitted to the NAND flash memory 3 during the period when the signal / WE is at the "L (Low)" level into the NAND flash memory 3.

[0052] The read enable signal RE and / RE indicate the output data signal DQ of the NAND flash memory 3, which is used to control the operation timing of the NAND flash memory 3 when, for example, the output signal DQ is controlled. The write protection signal / WP indicates to the NAND flash memory 3 to prohibit data writing and erasing. The ready / busy signal / RB indicates whether the NAND flash memory 3 is in a ready state (a state of accepting commands from the outside) or a busy state (a state of not accepting commands from the outside), respectively.

[0053] The data signal DQ is, for example, an 8-bit signal. The signal DQ is the entity of the data transmitted and received between the NAND flash memory 3 and the memory controller 2, and includes an instruction CMD, an address ADD, and data DAT. The bidirectional data strobe signals DQS and / DQS, which can be used as reference signals, are used to control the operation timing of the NAND flash memory 3 under the signal DQ, for example.

[0054] <Structure of NAND Flash Memory>

[0055] Next, with reference to Figure 2 , a structural example of the NAND flash memory 3 will be described.

[0056] The NAND flash memory 3 includes a memory cell array 11, an input / output circuit 12, a logic control circuit 13, a register 15, a sequence generator 16, a voltage generation circuit 17, a driver 18, a row decoder 19, a sense amplifier 20, an input / output pad group 21, a logic control pad group 22, a data generation circuit 14, etc.

[0057] The memory cell array 11 includes a plurality of blocks BLK (BLK0, BLK1,...). Each block BLK includes a plurality of non-volatile memory cell transistors (not shown) associated with word lines and bit lines. The block BLK is, for example, a data erasure unit, and the data within the same block BLK is erased uniformly. Each block BLK includes a plurality of string units SU (SU0, SU1,...). Within each string unit SU, a plurality of NAND strings NS are provided. In addition, the number of blocks in the memory cell array 11, the number of string units US within one block BLK, and the number of NAND strings within one string unit SU can be set to arbitrary numbers.

[0058] <Structure of Memory Cell Array>

[0059] Next, with reference to Figure 3 , the structure of the memory cell array of the NAND flash memory 3 will be described. Figure 3 A circuit representing one block BLK in the memory cell array 11.

[0060] As Figure 3As shown, each string unit SU is composed of a set of NAND strings NS. Each of the NAND strings NS includes, for example, 64 memory cell transistors MT (MT0 to MT63), a selection transistor ST1, and a selection transistor ST2. In addition, the number of memory cell transistors MT included in one NAND string NS is not limited to 64, and may also be 8, 16, 96, etc., and its number is not limited. The memory cell transistor MT has a stacked gate including a control gate and a charge storage layer. Each memory cell transistor MT is connected in series between the selection transistor ST1 and ST2. In addition, the connections described below include not only electrical connections in which the connected elements are in contact with each other, but also cases where other conductive elements, such as wirings (metal wirings, polysilicon wirings, etc.), are interposed between at least two elements.

[0061] In any block BLK, the gates of the selection transistors ST1 of the string units SU0 to SU3 are respectively connected to the selection gate lines SGD0 to SGD3. Moreover, the gates of the selection transistors ST2 of all the string units SU in the block BLK are commonly connected to the selection gate line SGS. The control gates of the memory cell transistors MT0 to MT7 in the same block BLK are respectively connected to the word lines WL0 to WL7. That is, the word lines WL of the same address are commonly connected to all the string units SU in the same block BLK, and the selection gate line SGS is commonly connected to all the string units SU in the same block BLK. On the other hand, the selection gate line SGD is connected to only one string unit SU in the same block BLK.

[0062] Moreover, the other ends of the selection transistors ST1 of the NAND strings NS located in the same row among the NAND strings NS arranged in a matrix in the memory cell array 11 are connected to any one of m bit lines BL (BL0 to BL(m - 1) (m is a natural number)). Moreover, the bit lines BL span multiple blocks BLK and are commonly connected to the NAND strings NS in the same column.

[0063] Moreover, the other end of the selection transistor ST2 is connected to the source line SL. The source line SL spans multiple blocks BLK and is commonly connected to multiple NAND strings NS.

[0064] As described above, data erasure is performed uniformly, for example, on the memory cell transistors MT located in the same block BLK. In contrast, the data read operation and write operation can be performed uniformly on the multiple memory cell transistors MT commonly connected to any word line WL of any string unit SU of any block BLK. A group of memory cell transistors MT that share the word line WL in one string unit SU is called, for example, a unit component CU. That is, the unit component CU is a group of memory cell transistors MT that can perform a write operation or a read operation uniformly.

[0065] In addition, one memory cell transistor MT can hold, for example, multiple bits of data. Moreover, within the same cell component CU, a set of 1 bit held by each of the memory cell transistors MT at the same bit is called a "page". That is to say, a "page" can also be defined as a part of the memory space of a group of memory cell transistors MT formed within the same cell component CU. One page is, for example, 128 Kbit (kilobit) (16 KByte (kilobyte)).

[0066] Return to Figure 2 Continuing the explanation. The input / output circuit 12 includes at least an input circuit 12A, an output circuit 12B, and a control circuit 12C. The input / output circuit 12 exchanges data signals DQ with the memory controller 2. The input / output circuit 12 transfers the instruction CMD and the address ADD included in the signal DQ input to the input / output pad group 21 to the instruction register 15A and the address register 15B of the register 15, respectively. Moreover, the input / output circuit 12 transfers the write data DAT included in the signal DQ input to the input / output pad group 21 to the data register 20B of the sense amplifier 20, and at the same time transfers the read data DAT transferred from the data register 20B of the sense amplifier 20 to the input / output pad group 21.

[0067] Figure 4 It is a circuit diagram of the output circuit 12B. As shown in the figure, the output circuit 12B includes a shift register unit 31A and a multiplexer (MUX) 31D [selection circuit]. The shift register unit 31A includes a shift register 31B [holding circuit] composed of a plurality of flip-flops 31C connected in series. The shift register 31B is arranged for each of the signal lines DQ0 to DQ7 and temporarily holds data respectively. The number of flip-flops 31C is appropriately set according to the timing control of the signal DQ, for example, 8.

[0068] At the input terminal D of the flip-flop 31C in the first stage ( Figure 4 at the rightmost side of the paper surface of), one of the multiple input terminals of the multiplexer 31D is connected, and its output terminal Q is connected to the input terminal D of the next-stage flip-flop 31C. The output terminal Q of the next-stage flip-flop 31C is connected to the input terminal D of the flip-flop 31C in the stage after that, and so on. The output terminal Q of the flip-flop 31C in the last stage is connected to one of the signal lines DQ0 to DQ7 ( Figure 4 in the example is the signal line DQ0). At the clock terminal of each flip-flop 31C, an internal clock iCLK with different periods, for example, is input from the sequence generator 16. Each flip-flop 31C latches the input data at the rising timing of the internal clock iCLK input to each clock terminal.

[0069] The multiplexer 31D selects 8 bits from the read data DAT of 1 page (16 KByte) read from the memory cell array 11 to the sense amplifier unit 20A and stored in the data register 20B, and transfers them to the shift register unit 31A. The transferred 8-bit data is sequentially held and transferred by the flip-flop 31C that functions as a buffer. For example, if the memory controller 2 switches the read enable signals RE and / RE after the read data is temporarily held by the shift register 31B, the read data held by the shift register 31B is output as DQ data in 8-bit units from the output terminal Q of the last-stage flip-flop 31C. That is, the output circuit 12B converts the 16 KByte parallel data into 8-bit serial data.

[0070] Return again to Figure 2 Continue the explanation. The logic control circuit 13 receives the signals / CE, CLE, ALE, / WE, / RE, and / WP from the memory controller 2. Moreover, the logic control circuit 13 transmits the signal / RB to the memory controller 2 to notify the memory controller 2 whether the NAND flash memory 3 is in a ready state or a busy state.

[0071] The logic control circuit 13 includes a correction circuit 13a having a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit. The correction circuit 13a has a function of correcting the duty ratios of the input signals RE and / RE, etc. respectively via the pads in the logic control pad group. The correction circuit 13a corrects the duty ratios of the signals RE and / RE based on the control signal from the sequence generator 16, and generates the corrected signals RE and / RE. The corrected signals RE and / RE are sent to, for example, the input / output circuit 12, and the input / output circuit 12 switches the signals DQS and / DQS at the timings corresponding to the corrected signals RE and / RE.

[0072] The register 15 includes an instruction register 15A that holds the instruction CMD and an address register 15B that holds the address ADD. The register 15 transfers the address ADD to the row decoder 19 and the sense amplifier 20, and at the same time transfers the instruction CMD to the sequence generator 16.

[0073] The sequence generator 16 receives the instruction CMD and controls the entire NAND flash memory 3 according to the sequence based on the received instruction CMD. Moreover, the sequence generator 16 sends the temperature information received from a temperature sensor or the like to the memory controller 2 via the input / output circuit 12.

[0074] The voltage generation circuit 17 generates the voltages required for operations such as writing, reading, and erasing data based on the indication from the sequence generator 16. The voltage generation circuit 17 supplies the generated voltages to the driver (driver group) 18.

[0075] Based on the address ADD transmitted from the address register 15B of the register 15, the driver 18 supplies various voltages from the voltage generation circuit 17 to the row decoder 19 and the sense amplifier 20. Based on, for example, the row address in the address, the driver 18 supplies various voltages to the row decoder 19.

[0076] The row decoder 19 receives the row address included in the address ADD transmitted from the address register 15B of the register 15, and selects the memory cell transistors of the row based on the row address. And, for the memory cell transistors of the selected row, the voltage from the driver 18 is transmitted via the row decoder 19.

[0077] The sense amplifier 20 includes a sense amplifier unit 20A and a data register 20B. When reading data, for example, the sense amplifier unit 20A reads (senses) the read data DAT read from the memory cell transistors to the bit lines, and transmits the read read data DAT to the data register 20B. The read data DAT held in the data register 20B is transmitted to the output circuit 12B. When writing data, for example, the write data DAT transmitted from the input circuit 12A to the data register 20B is written by the sense amplifier unit 20A to the memory cell transistors via the bit lines. The sense amplifier 20 receives the column address included in the address ADD from the address register 15B of the register 15, and outputs the column data based on the column address.

[0078] For example, corresponding to the read instruction given from the memory controller 2, the sense amplifier unit 20A reads data from the memory cell transistors and transmits it to the data register 20B, and corresponding to the data output instruction given from the memory controller 2, transmits the data held in the data register 20B to the output circuit 12B.

[0079] The period from when the read instruction is given from the memory controller 2 until the sense amplifier 20A reads data from the memory cell array 11 and holds the read data in the data register 20B is referred to as "period tR". During the period tR, the ready / busy signal R / Bn and the internal busy signal are both at the "L" level (ready state).

[0080] The input / output pad group 21 transmits the data signals DQ, DQS, and / DQS received from the memory controller 2 to the input / output circuit 12. Moreover, the input / output pad group 21 transmits the signal DQ sent from the input / output circuit 12 to the outside of the NAND flash memory 3.

[0081] The pad group 22 for logic control transmits the signals / CE, CLE, ALE, / WE, / RE, and / WP received from the memory controller 2 to the logic control circuit 13. Further, the pad group 22 for logic control transmits / RB transmitted from the logic control circuit 13 to the outside of the NAND flash memory 3.

[0082] Based on an instruction from, for example, the sequence generator 16, the data generation circuit 14 outputs dummy data from the output circuit 12B according to the signals DQS and / DQS. Specifically, the memory controller 2 switches the read enable signals RE and / RE, and the NAND flash memory 3 receives the signals RE and / RE and generates the signals DQS and / DQS. The data generation circuit 14 receives the signals DQS and / DQS, generates preset dummy data, and outputs the same from the output circuit 12B to the memory controller 2. When the memory controller 2 determines that the received data is dummy data, it does not perform processing or processes it as invalid data.

[0083] The dummy data may be, for example, a random pattern. Alternatively, the dummy data may be a pattern in which each signal of the signal lines DQ0 to DQ7 repeats switching between the "H" level and the "L" level, such as 55h-AAh-55h-AAh..., or may be a data pattern of a fixed value. Further, the data generation circuit 14 may be included in the logic control circuit 13 or the input / output circuit 12. For example, the control circuit 12C of the input / output circuit 12 may also have the function of the data generation circuit 14.

[0084] Next, with reference to Figures 1 to 4 and FIG. 6, stabilization of the data output operation from the NAND flash memory 3 to the memory controller 2 using the dummy data output of the data generation circuit 14 according to the present embodiment will be described. Figure 4 FIG. shows a configuration example of the output circuit 12B. Figure 6A FIG. shows a timing chart of data reading in a comparative example, Figure 6B FIG. shows a timing chart of data reading in the present embodiment.

[0085] Figure 6A FIG. shows the standby time t set in the NAND flash memory 3 in the comparative example WHR2 and the delay time (latency). The NAND flash memory 3 in the comparative example has the same circuit configuration as the NAND flash memory 3 in the present embodiment, but the operations related to the standby time t WHR2 and the delay time are different.

[0086] For example, if a read instruction is issued from the memory controller 2 to the NAND flash memory 3, the sense amplifier unit 20A of the sense amplifier 20 reads out data of 1 page (e.g., 16 KByte) from the memory cell array 11, and the data register 20B stores the read data. Next, for example, a data output instruction is issued from the memory controller 2 to the NAND flash memory 3. The data output instruction is, for example, an instruction group including one or more instruction signals ("05h" and "E0h") given as 8-bit signals DQ and one or more address signals (column address ADD and row address ADD) given as 8-bit signals DQ.

[0087] If a data output instruction is issued from the memory controller 2 to the NAND flash memory 3, then as Figure 4 shown, 1 page of data is transferred from the data register 20B to the output circuit 12B. The multiplexer 31D of the output circuit 12B sequentially selects 8-bit data from the transferred 16 KByte of data and transfers it to the shift register unit 31A. The shift register unit 31A holds the 8-bit data through the flip-flop 31C functioning as a buffer while transferring it. Thus, the read data is temporarily held in the shift register 31B. If the state toggle signals RE and / RE are toggled in the said state, then 8-bit DQ data is output from the output terminal Q of the flip-flop 31C of the last stage to the memory controller 2 via the input / output pad group 21.

[0088] Standby time t WHR2 [The first period] is, for example, the time required from when a data output instruction is issued from the memory controller 2 to the NAND flash memory 3 until the 16 KByte of read data read out from the memory cell array 11 is transferred from the data register 20B to the output circuit 12B, and at the same time, the preparation for outputting the first 8 bits of it as DQ data to the memory controller 2 in the output circuit 12B is completed. Therefore, for example, within the standby time t WHR2 period, the first 8 bits of the data in the data register 20B are transferred to the flip-flop 31C of the last stage of the shift register unit 31A of the output circuit 12B, and after passing the standby time t WHR2 the memory controller 2 starts toggling the signals RE and / RE, thereby starting to output 8-bit DQ data to the signal lines DQ0 to DQ7. Assuming that if the standby time t WHR2 is not waited for and the memory controller 2 starts toggling the signals RE and / RE, then it is possible that, for example, incomplete data is output in a state where storing 8-bit data in an output buffer (not shown) connected to the signal lines DQ0 to DQ7 is not completed, or unexpected data is output.

[0089] That is, in the comparative example, after the memory controller 2 issues a data output instruction to the NAND flash memory 3, if it does not wait for the standby time t WHR2 , then it is impossible to switch the signals RE and / RE for instructing data output to the NAND flash memory 3.

[0090] Moreover, as Figure 6A shown, in the comparative example, after the standby time t WHR2 [first period], a delay time (delay time: latency) [second period] is also added.

[0091] If the memory controller 2 starts to switch the signals RE and / RE, then the delay period t DQSRE also starts to switch the signals DQS and / DQS sent from the NAND flash memory 3. For example, the correction circuit 13a of the logic control circuit 13 corrects the duty cycles of the signals RE and / RE input from the memory controller 2 via the logic control pad group 22, and the input / output circuit 12 generates the signals DQS and / DQS based on the corrected signals RE and / RE.

[0092] The signals DQS and / DQS are used to control, for example, the operation timing of the NAND flash memory 3 under the control signal DQ. Therefore, the NAND flash memory 3 can start outputting valid data immediately after the signals DQS and / DQS start to switch.

[0093] However, sometimes the power supply VDD of the NAND flash memory 3 becomes unstable immediately after the memory controller 2 starts to switch the signals RE and / RE. Therefore, for example, in order to retain the output of valid data until the power supply VDD that has become unstable due to the start of the switching of the signals RE and / RE becomes stable, the delay time is set. The timing of starting the output of valid data is delayed by the delay time from the timing of the switching of the signals DQS and / DQS.

[0094] The delay time is preferably long in order to stabilize the power supply VDD, but is preferably short in order to achieve high-speed operation. In addition, there is also a case where the delay time is set in order to ensure the time required for correction processing such as duty cycle correction or timing correction in a phase-locked loop (PLL) or a delay-locked loop (DLL) provided in the correction circuit (DCC) 13a.

[0095] For example, the sequence generator 16 counts either of the signals RE and / RE or either of the signals DQS and / DQS, and starts outputting the data (valid data) transferred from the data register 20B to the output circuit 12B after reaching a specific number of counts.

[0096] Figure 5 is a flowchart showing the data output in the comparative example.

[0097] First, in the comparative example, by a read instruction previously issued from the memory controller 2, the sense amplifier unit 20A of the sense amplifier 20 reads data from the memory cell array 11, for example, 1 page of 16 KByte of data, and the read data is stored by the data register 20B. In this state, the memory controller 2 switches the signal / WE and issues a data output instruction via the data signal lines DQ0 to DQ7 (step S1). The instruction is output to the sense amplifier 20, and starting from the point when the switching of the signal / WE stops, a preset time measurement is started (step S2). In parallel with this, in the NAND flash memory 3, the read data is transferred from the data register 20B to the multiplexer 31D in the output circuit 12B (step S3). During the standby time t WHR2 During this period, the multiplexer 32D selects 16 KByte of data in units of, for example, 8 bits and transfers it to the shift register unit 31A. During the standby time t WHR2 During this period (step S4: NO), it cannot be guaranteed that the preparation for the output circuit 12B to output data to the memory controller 2 has been completed. Therefore, the memory controller 2 does not start switching the read enable signals RE and / RE during the standby time t WHR2 During this period.

[0098] Then, if the period of the standby time t WHR2 ends (step S4: YES), then the preparation for the output circuit 12B to output data to the memory controller 2 has been completed, so the memory controller 2 starts switching the read enable signals RE and / RE (step S5). The NAND flash memory 3 that has received the switching signals RE and / RE starts switching the signals DQS and / DQS. The data generation circuit 14 that has received the switching signals DQS and / DQS outputs preset virtual data from the output circuit 12B.

[0099] The output circuit 12B outputs invalid virtual data to the signal lines DQ0 to DQ7, for example, during a preset delay time, and after the preset delay time ends, outputs the data stored in the shift register unit 31A to the signal lines DQ0 to DQ7 (step S6). In coordination with the above output, data can be continuously transferred from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). In addition, data is output from the output circuit 12B to the memory controller 2.

[0100] In the comparative example, the time from when the data output instruction is issued from the memory controller 2 to when the first valid 8-bit data is output from the NAND flash memory 3 includes at least the standby time t WHR2, and the delay time required to wait for the power supply VDD, which becomes unstable due to the switching of the signals RE and / RE, to stabilize. For example, if the delay time is short, data output starts before the output of the power supply VDD stabilizes, so the level of the output data may become unstable.

[0101] Next, referring to Figure 6B the timing chart shown in Figure 7 and Figure 6A the flowchart shown in Figure 5 the data output of the data generation circuit 14 of the first embodiment will be described. In addition, for operations equivalent to those of

[0102] the timing chart shown in WHR2 and WHR2 the flowchart shown in, there are cases where the same step numbers are marked for simplified description.

[0103] In the present embodiment, when describing the data output operation, it is also assumed in advance that the memory controller 2 issues a read instruction, reads the desired data from the memory cell array 11, and stores it in the data register 20B.

[0104] First, the memory controller 2 issues a data output instruction to the NAND flash memory 3 (step S1). The data output instruction is an instruction group including a first instruction signal "05h" given as an 8-bit signal DQ, a column address signal ADD, a row address signal ADD, and a second instruction signal "E0h". The memory controller 2 switches the signal / WE at a cycle of time t WC .

[0105] Next, the memory controller 2 issues a data output instruction and starts time measurement simultaneously (step S2). Then, within the standby time t WHR2 , that is, after passing t WHR2 which is shorter than the standby time t WHR2’ and then, at time t RC of the periodic switching signal RE and / RE (step S5). The standby time t WHR2 During this period, the switching times and switching start timings of the signals RE and / RE can be appropriately set using, for example, a set feature.

[0106] In parallel with this, after the NAND flash memory 3 receives a data output instruction, the data register 20B transfers, for example, 16 KByte of data held therein to the multiplexer 31D within the input / output circuit 12 (step S3). The multiplexer 31D transfers the 16 KByte of data to each shift register 31B of the shift register unit 31A in units of 8 bits, for example.

[0107] Moreover, after the switching of the signals RE and / RE starts, in the NAND flash memory 3, during the delay period t DQSRE ’, the switching signals DQS and / DQS start to be switched. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8). The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 during a preset delay time (step S11). In Figure 6B the present embodiment shown, an example is shown where the switching of the signals DQS and / DQS starts and at the same time the output of the dummy data starts. However, the timing is not limited thereto. As described above, the memory controller 2 does not process the dummy data. Moreover, by advancing the timing of the start of the switching of the signals RE and / RE, the output of the power supply VDD is more stable at the timing of starting to output valid data instead of dummy data.

[0108] Then, if, for example, the switching count of the signal DQS reaches the set number of times (step S12: Yes), the read data signal DQ is output from the shift register unit 31A of the output circuit 12B to the memory controller 2 (step S6). In coordination with the above output, data can be continuously transferred from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). Data is also output from the output circuit 12B to the memory controller 2. Moreover, the output time or number of cycles (switching count) of the dummy data of the signal DQ is appropriately set and is not limited.

[0109] In Figure 6A the comparative example shown, after the standby time t WHR2After that, start toggling signals RE and / RE, and then start toggling signals DQS and / DQS. Moreover, the timing of starting to output valid data is delayed by a delay time from the timing when the toggling of signals DQS and / DQS starts. When the power supply VDD becomes unstable due to the start of the toggling of signals RE and / RE, by setting the delay time longer, the output of valid data can start after the power supply VDD stabilizes. On the other hand, in the comparative example, the time from when the data output instruction is issued from the memory controller 2 to when the first valid 8-bit data is output from the NAND flash memory 3 is at least longer than the sum of the standby time t WHR2 and the delay time.

[0110] In contrast, in this embodiment, Figure 6B during the standby time t WHR2 [First period], start toggling signals RE and / RE [First signal], and then start toggling signals DQS and / DQS [Second signal]. Moreover, after the toggling of signals DQS and / DQS occurs any number of times, the data generation circuit 14 generates virtual data [First data] and outputs it from the output circuit 12B to the memory controller 2. The memory controller 2 does not process the virtual data as valid data (data read from the memory cell array 11 and stored in the data register 20B), and does not perform data processing. The memory controller 2 can determine whether it is virtual data based on, for example, the number of toggles of the signal DQS. When the virtual data has a repeating toggle pattern such as 55h-AAh-55h-AAh..., instead of the number of toggles of the signal DQS, it can also be determined whether it is virtual data based on the number of toggles of the virtual data.

[0111] As described above, in this embodiment, during the standby time t WHR2 , continuously start toggling signals RE and / RE and signals DQS and / DQS, and then output virtual data. Thus, the standby time t WHR2 and the delay time can be overlapped in time, and the stabilization of the output of the power supply VDD can be achieved earlier than in the comparative example. Therefore, when setting the timing of starting to output valid data to be the same as the timing of the Figure 6A comparative example described, the delay time (latency) used to achieve the stabilization of the power supply output can be set longer. Thus, for example, as Figure 6B shown, after the output of the power supply VDD stabilizes, the output of valid data can start, and the read reliability of the data can be improved.

[0112] Alternatively, if the output of the power supply VDD is stabilized to the same level as in the comparative example and there is no problem with the read reliability of the data, by switching the signals RE and / RE from an earlier period, the delay time for simultaneously outputting the virtual data of the signals DQS and / DQS ends at an earlier period. Therefore, the timing for starting to output valid data can be earlier than in the comparative example, achieving a substantial high-speed operation of the data read time.

[0113] With respect to the standby time t WHR2 , the timing for the memory controller 2 to start switching the signals RE and / RE, or the timing for starting to output valid data after the output of the virtual data ends, is not limited to that shown in the first embodiment Figure 6B , and can be appropriately set according to the design or device specifications. Hereinafter, an example of the timing setting will be described.

[0114] [First Setting Example]

[0115] Figure 8 The first setting example shown in WHR2 sets the end of the switching of the standby time t WHR2 and the end of the output of the virtual data of the latency to the same timing. That is, it is set such that data output can be performed as soon as the standby time t

[0116] ends. WHR2 First, within the period of the standby time t

[0117] , the signals RE and / RE are started to be switched, and then immediately the signals DQS and / DQS are started to be switched, and the virtual data in the signal DQ is started to be output. The switching of the signals RE and / RE and the switching of the signals DQS and / DQS continue until at least the output of the virtual data in the signal DQ ends. WHR2 In the first setting example, the standby time t RC is set to 300 nsec, and the one-cycle time t

[0118] [Second Setting Example]

[0119] Figure 9 The second setting example shown in WHR2 is set such that after the switching of the standby time t WHR2Set to 300 nsec, the one-cycle time t of the switching signals RE and / RE RC is set to 2.5 nsec. At this time, the switching of the signals RE and / RE and the switching of the signals DQS and / DQS start during the standby time t WHR2 and continue until the output of the dummy data of the signal DQ ends.

[0120] [Third setting example]

[0121] Figure 10 In the third setting example shown, during the standby time t WHR2 , the switching of the signals RE and / RE and the switching of the signals DQS and / DQS are temporarily stopped, and then restarted at the end of the standby time t WHR2 . It is set that at the same time as the restart of the switching, the output of the dummy data in the signal DQ of the end delay time (latency) ends.

[0122] Specifically, during the standby time t WHR2 , the switching of the signals RE and / RE and the switching of the signals DQS and / DQS start, and the dummy data starts to be output. In addition, during the standby time t WHR2 , the switching of the signals RE and / RE and the switching of the signals DQS and / DQS that have reached the set number of switchings end, but the output of the dummy data in the signal DQ continues. And, wait for the switching of the signals RE and / RE used to start the data output.

[0123] After that, at the same time as the end of the standby time t WHR2 , the switching of the signals RE and / RE and the signals DQS and / DQS is restarted, and the output of the dummy data in the signal DQ ends.

[0124] In the third setting example, the standby time t WHR2 is set to 300 nsec, and the one-cycle time t of the switching signals RE and / RE RC is set to 2.5 nsec.

[0125] In the third setting example, since the switching of the signals RE and / RE and the switching of the signals DQS and / DQS are interrupted, power consumption can be suppressed.

[0126] [Fourth setting example]

[0127] Figure 11 In the fourth setting example shown, it is set that during the standby time t WHR2 , the switching signal RE and / RE starts, and during the standby time t WHR2After the end latency, the switching of the start signals DQS and / DQS and the output of the dummy data in the signal DQ are started. In the fourth setting example, the standby time t WHR2 is set to 300 nsec, and the one-cycle time t RC of the switching signals RE and / RE is set to 2.5 nsec. In the fourth setting example, similar to the third setting example, power consumption can be suppressed.

[0128] [Second Embodiment]

[0129] Next, with reference to Figure 12 the flowchart shown, the data output operation from the NAND flash memory 3 to the memory controller 2 in the second embodiment will be described. In addition, for operations equivalent to those of the flowchart shown Figure 7 the same step numbers are assigned for simplified description.

[0130] In this embodiment, dummy data is output and the duty ratio of the PLL / DLL of the correction circuit is corrected within the latency of the first embodiment described above.

[0131] First, the memory controller 2 starts switching the signal / WE and issues an address ADD and a data output instruction (step S1). After receiving the data output instruction, the NAND flash memory 3 transfers the data stored in the data register 20B to the multiplexer 31D in the input / output circuit 12 (step S3). The multiplexer 31D stores, for example, 16 KByte of data in each shift register 31B in units of 8 bits t.

[0132] Moreover, from the point in time when the switching of the signal / WE stops simultaneously with the issuance of the data output instruction, the memory controller 2 starts time measurement (step S2). Then, within the standby time t WHR2 the memory controller 2 starts switching the signal RE and / RE with a one-cycle of the standby time t RC . After the switching of the signals RE and / RE starts, the NAND flash memory 3 starts switching the signals DQS and / DQS after a set time. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8).

[0133] The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In parallel with the output of the dummy data, that is, within the standby time and latency, the duty ratio of the PLL / DLL of the correction circuit 13a provided in the logic control circuit 13 is corrected (step S13).

[0134] In the virtual data output, the data stored in data register 20B is transferred to multiplexer 31D (step S3). Multiplexer 31D stores, for example, 16 KByte of data in each shift register 31B in units of 8 bits.

[0135] Then, when the switching of, for example, signal DQS reaches a set number of times (or, the output time of the switching) (step S12: YES), that is, when the latency ends, the data read out to shift register 31B starts to be output to memory controller 2 (step S6). In coordination with the output, data can be continuously transferred from data register 20B to multiplexer 31D of output circuit 12B (step S7). Data is also output from output circuit 12B to memory controller 2.

[0136] In the present embodiment, by achieving the stabilization of the power output from an earlier period than in the comparative example, the data output can be started after the power output is stabilized. In addition, since the stabilization of the power output is sought from an earlier period, the latency can be set longer. Therefore, it is possible to ensure the time for other processes such as the duty ratio correction process during the latency. Moreover, by using the standby time or latency to execute the time for the correction process and being able to use sufficient processing time, the accuracy of the correction can be improved.

[0137] [Embodiment 3]

[0138] Next, with reference to Figure 13 the flowchart shown, the data output operation from NAND flash memory 3 to memory controller 2 in Embodiment 3 will be described. In addition, for operations equivalent to those of the flowchart shown in Figure 7 the same step numbers are assigned for simplified description.

[0139] This embodiment is a process in which the issuance of the data output instruction in the first embodiment and the step of starting the switching of signals RE and / RE are swapped. That is, after starting to switch signals RE and / RE, the data output instruction is issued.

[0140] First, memory controller 2 starts to switch signals RE and / RE (step S5). After that, memory controller 2 issues address ADD and the data output instruction (step S1). After issuing the data output instruction, memory controller 2 starts time measurement (step S2).

[0141] After the start of measurement by memory controller 2, during standby time t WHR2After a preset time or the number of times of switching of signals RE and / RE has elapsed within a period, the signals DQS and / DQS start to be switched. After the signals DQS and / DQS start to be switched, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8).

[0142] During the delay time, the output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In the present embodiment, the memory controller 2 also determines the received data as dummy data and does not perform processing.

[0143] Moreover, after the NAND flash memory 3 receives a data output instruction, the data stored in the data register 20B is transferred to the multiplexer 31D in the input / output circuit 12 (step S3). The multiplexer 31D stores, for example, 16 KByte of data in each shift register 31B in units of 8 bits.

[0144] After that, when the number of times of switching of, for example, the signal DQS reaches a set number (step S12: YES), that is, when the delay time (latency) ends, data is output from the shift register unit 31A of the output circuit 12B to the memory controller 2 (step S6). In cooperation with the output, data can be continuously transferred from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). Data is also output from the output circuit 12B to the memory controller 2.

[0145] As described above, the present embodiment can obtain the same operational effects as those of the first embodiment. In addition, in the present embodiment, the issuance of the data output instruction and the start timing of the switching of the signals RE and / RE are not limited, and the data output instruction may be issued after the start of the switching of the signals RE and / RE. In the present embodiment, during the standby time and the period of outputting dummy data, the data read from the memory cell array 11 by the sense amplifier 20 and transferred to the multiplexer 31D of the output circuit 12B can be processed simultaneously or in parallel, so that the power supply can be stabilized and appropriate data can be output.

[0146] [Fourth Embodiment]

[0147] Next, with reference to Figure 14 the flowchart shown, the data output operation from the NAND flash memory 3 to the memory controller 2 in the fourth embodiment will be described. In addition, for operations equivalent to those of the Figure 7 flowchart shown, the same step numbers are assigned and the description is simplified.

[0148] This embodiment is an example in which the switching signals RE and / RE are started when data is read from the memory cell transistor by issuing a read command, and then a data output command is issued.

[0149] First, the memory controller 2 issues a read command together with an address ADD, etc. to the NAND flash memory 3 (step S14).

[0150] In accordance with the read command, the sense amplifier unit 20A reads data from the memory cell array 11 and stores it in the data register 20B (step S15). In parallel with this, the memory controller 2 starts the switching signals RE and / RE (step S5).

[0151] Moreover, after the NAND flash memory 3 starts the switching signals RE and / RE, it starts the switching signals DQS and / DQS. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B (step S8). The output circuit 12B outputs the dummy data together with the signals DQS and / DQS to the memory controller 2 via the signal lines DQ0 to DQ7 (step S11). In this embodiment, even if the dummy data is output from the output circuit 12B to the memory controller 2, it is determined as invalid data and is not processed.

[0152] Next, the memory controller 2 issues a data output command to the NAND flash memory 3 (step S1). After issuing the data output command, the memory controller 2 starts time measurement (step S2). During the standby time t WHR2 the data stored in the data register 20B is transferred to the multiplexer 31D of the output circuit 12B (step S3). The multiplexer 31D stores, for example, 16 KByte of data in each shift register 31B in units of 8 bits for the first time.

[0153] After that, for example, when the switching of the signal DQS reaches a set number of times (step S12: YES), that is, when the latency ends, data is output from the shift register unit 31A of the output circuit 12B to the memory controller 2 (step S6). In coordination with the said output, data can be continuously transferred from the data register 20B to the multiplexer 31D of the output circuit 12B (step S7). Data is also output from the output circuit 12B to the memory controller 2.

[0154] As described above, this embodiment can obtain the same operational effects as the first embodiment described above. In addition, in this embodiment, the switching signals RE and / RE can be started during the period after issuing the read command and before issuing the data output command.

[0155] [Fifth Embodiment]

[0156] Reference Figure 15 With reference to the timing chart shown below, the data output operation from the NAND flash memory 3 to the memory controller 2 in the fifth embodiment will be described.

[0157] In this embodiment, instead of the read output instruction used in each of the above-described embodiments, a getfeature instruction is used to cause the NAND flash memory 3 to output a preset set value. Specifically, as shown in Figure 15 , after issuing a read instruction XXh for the getfeature instruction, during a period corresponding to the standby time t WHR2 (time t WB + set time t FEAT + time t RP ), the switching signals RE and / RE are started. Correspondingly, the NAND flash memory 3 starts the switching signals DQS and / DQS. After the switching of the signals DQS and / DQS starts, the data generation circuit 14 generates dummy data and outputs it to the output circuit 12B. The output circuit 12B outputs the dummy data to the memory controller 2 via the signal lines DQ0 to DQ7. Further, after the output of the dummy data is completed, the NAND flash memory 3 outputs the set value to the memory controller 2.

[0158] In the NAND flash memory 3 of this embodiment, the set time t FEAT , the timings of the start and end of the switching of the signals RE and / RE, the timings of the start and end of the switching of the signals DQS and / DQS, the number of switching times for each, and / or the output time of the dummy data (when the dummy data is in a repeating switching pattern such as 55h-AAh-55h-AAh...), the set value for each is previously held in a feature register (not shown), and when an operation instruction is received, it operates based on the set value.

[0159] In this embodiment, the same effect as that of the first embodiment can also be achieved.

[0160] Although several embodiments of the present invention have been described, the above-described embodiments are presented as examples and are not intended to limit the scope of the invention. The above-described embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. The above-described embodiments or their variations are included in the scope or gist of the invention, and are also included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: A memory cell array including memory cells capable of storing data; A signal pad to which write data to be written into the memory cells is input from an external controller, and from which read data read from the memory cells is output to the external controller; A first control pad to which a first timing control signal is input from the external controller; and A second control pad from which a second timing control signal is output to the external controller, wherein: During a first period after receiving a data output instruction instructing a data output operation, when the second timing control signal output from the second control pad switches in response to a switch of the first timing control signal input to the first control pad, virtual data is output from the signal pad, and During a second period after the first period, when the second timing control signal output from the second control pad switches in response to a switch of the first timing control signal input to the first control pad, the read data is output from the signal pad.

2. The semiconductor memory device according to claim 1, further comprising: A sense amplifier unit configured to perform a read operation to read the read data from the memory cells; A data register configured to store the read data received from the sense amplifier unit; and An input / output circuit configured to output the read data received from the data register to the signal pad.

3. The semiconductor memory device according to claim 2, further comprising: A virtual data generator configured to generate the virtual data.

4. The semiconductor memory device according to claim 3, further comprising: A sequence generator configured to control the sense amplifier unit to perform the read operation in response to a read instruction, and to control the input / output circuit to perform the data output operation in response to the data output instruction.

5. The semiconductor memory device according to claim 4, further comprising: A power supply section configured to supply a power supply voltage, wherein: During the first period after receiving the data output instruction, the power supply voltage drops to a first level, and During the second period after the first period, the power supply voltage is maintained at a second level higher than the first level.

6. The semiconductor memory device according to claim 5, wherein the first period corresponds to n switches of the first timing control signal input to the first control pad, and n is an integer equal to or greater than 2.

7. The semiconductor memory device according to claim 6, wherein the sequence generator is configured to change the number of n in response to a group characteristic instruction.

8. The semiconductor memory device according to claim 1, further comprising: Word lines connected to gates of the memory cells; and Bit lines connected to the memory cells.

9. The semiconductor memory device according to claim 8, wherein the memory cell array includes NAND strings in which a plurality of memory cells are connected in series, and the plurality of memory cells include the memory cells.

10. The semiconductor memory device according to claim 9, further comprising: a plurality of word lines respectively connected to the plurality of memory cells, wherein the bit line is connected to one end of the NAND string.

11. A storage device, comprising: a semiconductor memory; and a memory controller capable of being connected to a host via a host bus and coupled to the semiconductor memory via a memory bus, wherein: the memory controller has host bus terminals for transmitting and receiving instructions and data, the semiconductor memory includes: a memory cell array including memory cells capable of storing data; a signal pad, write data to be written into the memory cells is input from the memory controller to the signal pad, and read data read from the memory cells is output from the signal pad to the memory controller; a first control pad, a first timing control signal is input from the memory controller to the first control pad; and a second control pad, a second timing control signal is output from the second control pad to the memory controller, during a first period after receiving a data output instruction indicating a data output operation, when the second timing control signal output from the second control pad switches in response to a switch of the first timing control signal input to the first control pad, virtual data is output from the signal pad, and during a second period after the first period, when the second timing control signal output from the second control pad switches in response to a switch of the first timing control signal input to the first control pad, the read data is output from the signal pad.

12. The storage device according to claim 11, wherein the semiconductor memory further includes: a sense amplifier unit configured to perform a read operation to read the read data from the memory cells; a data register configured to store the read data received from the sense amplifier unit; and an input / output circuit configured to output the read data received from the data register to the signal pad.

13. The storage device according to claim 12, wherein the semiconductor memory further includes: a sequence generator configured to control the sense amplifier unit to perform the read operation in response to a read instruction, and control the input / output circuit to perform the data output operation in response to the data output instruction.

14. The storage device according to claim 13, wherein the sequence generator is configured to change the number of n in response to a group characteristic instruction.

15. The storage device according to claim 11, wherein the semiconductor memory further includes: a virtual data generator configured to generate the virtual data.

16. The storage device according to claim 11, wherein the semiconductor memory further includes: A power supply section configured to supply a power supply voltage, wherein: during the first period after receiving the data output instruction, the power supply voltage drops to a first level, and during a second period after the first period, the power supply voltage maintains a second level higher than the first level.

17. The memory device according to claim 11, wherein the first period corresponds to n times of switching of the first timing control signal input to the first control pad, and n is an integer equal to or greater than 2.

18. The memory device according to claim 11, further comprising: a word line connected to the gate of the memory cell; and a bit line connected to the memory cell.

19. The memory device according to claim 18, wherein the memory cell array includes NAND strings in which a plurality of memory cells are connected in series, and the plurality of memory cells include the memory cell.

20. The memory device according to claim 19, further comprising: a plurality of word lines respectively connected to the plurality of memory cells, wherein the bit line is connected to one end of the NAND string.

21. A semiconductor memory device, comprising: a memory cell array including memory cells configured to store data in a non-volatile manner; a data register configured to store the data read out from the memory cell array in a volatile manner; a signal pad, wherein write data to be written into the memory cell array is input from an external controller to the signal pad, and the data read out from the memory cell array and transmitted from the data register is output from the signal pad to the external controller; a first control pad, wherein a first timing control signal is input from the external controller to the first control pad; a second control pad, wherein a second timing control signal is output from the second control pad to the external controller, an internal controller configured to, after receiving a data output instruction from the external controller, output a data signal corresponding to the read data and the second timing control signal in response to the first timing control signal, wherein during a first period after receiving the data output instruction, the internal controller delays outputting the read data in response to the first timing control signal, and during a second period after the first period, the internal controller outputs the read data in response to the first timing control signal.

22. The semiconductor memory device according to claim 21, wherein during the first period, the internal controller outputs the second timing control signal to switch at a timing corresponding to the switching of the first timing control signal.

23. The semiconductor memory device according to claim 22, wherein during the first period, the internal controller outputs dummy data synchronously with the switching of the second timing control signal.

24. The semiconductor memory device according to claim 23, wherein during the second period, the internal controller outputs the read data synchronously with the switching of the second timing control signal.

25. The semiconductor memory device according to claim 23 further comprises: A virtual data generator configured to generate the virtual data.

26. The semiconductor memory device according to claim 21 further comprises: A sense amplifier unit configured to perform a read operation to read the read data from the memory cell and transfer the read data to the data register; and An input / output circuit configured to output the read data received from the data register to the signal pad.

27. The semiconductor memory device according to claim 21 further comprises: A power supply section configured to supply a power supply voltage, wherein: During the first period after receiving the data output instruction, the power supply voltage drops to a first level, and During the second period, the power supply voltage recovers to a second level higher than the first level.

28. The semiconductor memory device according to claim 21, wherein The first period corresponds to n switches of the first timing control signal, where n is an integer equal to or greater than 2.

29. The semiconductor memory device according to claim 28, wherein The internal controller is configured to change the number of n in response to a group feature instruction.

30. The semiconductor memory device according to claim 21 further comprises: A word line connected to the gate of the memory cell; and A bit line connected to the memory cell.

31. The semiconductor memory device according to claim 30, wherein The memory cell array includes NAND strings in which a plurality of memory cells are connected in series, and the plurality of memory cells include the memory cell.

32. The semiconductor memory device according to claim 31, wherein A plurality of the word lines are provided such that the word lines are respectively connected to the memory cells, and The bit line is connected to one end of the NAND string.

33. A semiconductor memory device includes: A signal pad to which write data is input from an external controller and from which read data is output to the external controller; A first control pad to which a first timing control signal is input from the external controller; A second control pad from which a second timing control signal is output to the external controller, A memory cell array including memory cells configured to store data in a non-volatile manner; A data register configured to store the data read from the memory cell array in a volatile manner; An output circuit configured to output a data signal corresponding to the data transferred from the data register to the external controller via the signal pad; wherein During a first period after receiving from the external controller a data output instruction during which the data is transferred from the data register to the output circuit, the internal controller accepts reception of the first timing control signal.

34. A memory system includes: A semiconductor memory device; and A memory controller, wherein The memory controller is configured to: Send the write data to the semiconductor memory device; Send a first timing control signal; and Send a data output instruction to the semiconductor memory device, The semiconductor memory device includes: A memory cell array including memory cells configured to store data in a non-volatile manner; A data register configured to store the data read out from the memory cell array in a volatile manner; A signal pad, the write data is input from a memory controller to the signal pad, and the data read out from the memory cell array and transferred from the data register is output from the signal pad to the memory controller; A first control pad, the first timing control signal is input to the first control pad; A second control pad, a second timing control signal is output from the second control pad to the memory controller, An internal controller configured to output a data signal corresponding to the read data and the second timing control signal in response to the first timing control signal after receiving the data output instruction, During a first period after receiving the data output instruction, the internal controller delays outputting the read data in response to the first timing control signal, and During a second period after the first period, the internal controller outputs the read data in response to the first timing control signal.

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