Semiconductor structure manufacturing method and semiconductor structure

Abstract

The invention discloses a semiconductor structure manufacturing method and a semiconductor structure, and the method comprises the steps: providing a silicon carbide substrate of which one side is provided with a plurality of first mask structures, forming second mask structures on the exposed surfaces of the first mask structures, taking the second mask structures and the first mask structures as masks, and carrying out the etching of the silicon carbide substrate, forming a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate; the material of the second mask structure and the material of the first mask structure are the same hard mask material, the second mask structure is completely etched and removed at the etching end point, and the surface of the remaining first mask structure is exposed. According to the method, the thickness insufficiency of an original mask can be compensated, damage is reduced, the protection effect on the surface of the silicon carbide substrate is improved, the defects caused by the original mask can be overcome, it is ensured that an ideal final etching morphology is obtained, and meanwhile a larger etching depth-to-width ratio can be achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technologies, and particularly to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] With the development of semiconductor devices towards high integration and high performance, silicon carbide (SiC), as a wide-bandgap semiconductor material, has been widely used in high-power, high-frequency, and high-temperature electronic devices due to its excellent physical and chemical properties. However, during the SiC plasma etching process, especially in deep trench etching, due to the insufficient protection effect of the mask layer on the SiC surface, the trench morphology of SiC during etching is not ideal enough. Therefore, it is necessary to study process methods to improve the protection effect of the surface mask layer to obtain an ideal SiC trench morphology. Summary of the Invention

[0003] The purpose of the present application is to overcome the above problems existing in the prior art, and to provide a method for manufacturing a semiconductor structure and a semiconductor structure, so as to improve the protection effect of the mask layer and obtain an ideal SiC etching morphology.

[0004] To achieve the above purpose, the technical solution of the present application is as follows: According to the first aspect of the present application, an embodiment of the present application provides a method for manufacturing a semiconductor structure, including: Providing a silicon carbide substrate, on one side of which a plurality of first mask structures are formed, and there is an opening between two adjacent first mask structures, exposing the surface of the silicon carbide substrate; Depositing a second mask layer on the exposed surface of the first mask structure, the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on the single-side side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact on the top surface and side surface of the first mask structure; Using the second mask structure and the first mask structure as masks, etching the silicon carbide substrate to form a deep trench etching structure with a certain etching depth in the silicon carbide substrate; Wherein, the material of the second mask structure and the material of the first mask structure are the same hard mask material, and the second mask structure is used to compensate for the original thickness of the first mask structure to reduce the original etching consumption of the first mask structure; at the end of etching, the second mask structure is completely etched away, exposing the surface of the remaining first mask structure.

[0005] In some embodiments, the second mask structure is further configured to modify the surface of the first mask structure to improve the topographical defects during the etching of the silicon carbide substrate.

[0006] In some embodiments, it further includes: Comparing the etching depth with the target depth. When the etching depth is less than the target depth, repeat the processes of depositing the second mask layer on the exposed surface of the first mask structure and etching the silicon carbide substrate using the second mask structure and the first mask structure as masks until the etching depth approaches the target depth.

[0007] In some embodiments, the number of times of depositing the second mask layer and etching the silicon carbide substrate is 1 to 3 times.

[0008] In some embodiments, when the number of times of etching the silicon carbide substrate is multiple times, the etching amount for each time decreases in sequence.

[0009] In some embodiments, when the number of times of etching the silicon carbide substrate is multiple times, the etching time for each time decreases in sequence.

[0010] In some embodiments, after etching the silicon carbide substrate, the remaining thickness of the first mask structure is more than 1 / 3 of the sum of the original thickness of the second mask structure and the original thickness of the first mask structure.

[0011] In some embodiments, the ratio of the original thickness of the second mask structure to the original thickness of the first mask structure is 1:10 to 1:2.

[0012] In some embodiments, the materials of the first mask structure and the second mask structure include silicon oxide.

[0013] In some embodiments, an anisotropic etching process is used to etch the silicon carbide substrate.

[0014] In some embodiments, when depositing the second mask layer, the temperature is -10°C to 30°C, the pressure is 10 mtorr to 200 mtorr, the source power is 100 W to 2000 W, and the bias power is 10 W to 100 W.

[0015] In some embodiments, when etching the silicon carbide substrate, the temperature is -10°C to 30°C, the pressure is 10 mtorr to 100 mtorr, the source power is 100 W to 3000 W, and the bias power is 10 W to 1000 W.

[0016] In some embodiments, the aspect ratio of the high aspect ratio etching structure is 5:1 or more.

[0017] According to the second aspect of the present application, embodiments of the present application further provide a semiconductor structure, which is obtained by using the semiconductor structure manufacturing method provided in any one of the embodiments of the first aspect above.

[0018] Embodiments of the present application may / at least have the following advantages: (1) By covering a new mask layer (the second mask layer) on the top surface and side surfaces of the first mask structure (the original mask structure), and making the deposition thickness of the second mask layer on the top surface of the first mask structure greater than the deposition thickness on the exposed surface of the single-side surface of the first mask structure and the silicon carbide substrate, a second mask structure in direct contact is formed on the top surface and side surfaces of the first mask structure, and a composite mask structure is formed with the first mask structure. In this way, when etching the silicon carbide substrate, on the one hand, when first etching away the thinner second mask layer on the surface of the silicon carbide substrate, a relatively large amount of the second mask layer on the top of the first mask structure can be retained during synchronous etching, so the consumption of the second mask layer material at the top of the composite mask structure is hardly affected. Therefore, sufficient consumption of the composite mask structure material can be provided during subsequent etching, increasing the mask thickness that can be consumed, which is equivalent to increasing the etching selectivity between the original mask structure and the silicon carbide substrate, and making the remaining thickness of the original mask structure after etching significantly increase compared with the existing process, effectively solving the problem that in the past high aspect ratio etching process of silicon carbide, due to insufficient mask layer thickness, the protection fails, resulting in large inclination of the silicon carbide trench angle and loss of trench critical dimensions. On the other hand, by forming the second mask layer on the exposed surface after the first mask structure is formed, the original surface of the first mask structure is modified. This can not only pre-improve the defects generated during patterning of the first mask structure, making the morphology of the composite mask structure formed after depositing the second mask layer good (i.e., completely eliminating mask defects), but also avoid the problem of mask etching defects that will ultimately occur when directly depositing the second mask layer for increasing the original mask thickness on the layer before the first mask structure is formed and then etching them together to form the composite mask structure. Therefore, an ideal final etching morphology can be ensured. In addition, since the deposition thickness of the second mask layer on the side surface of the first mask structure is relatively thin and will be gradually consumed during the process of etching the silicon carbide substrate, its influence on the etching critical dimension is also very small, ensuring the final accuracy of the etching dimension.

[0019] (2) By covering a new mask structure on the original mask structure, not only can the original mask structure be protected, but also the substrate material can be more effectively protected, forming a double protection mechanism, and on the basis of ensuring the uniformity and accuracy of the etching morphology, the flexibility and reliability of the etching process are improved.

[0020] (3) Facilitate compatibility with existing processes, reduce manufacturing costs, and improve process flexibility at the same time.

[0021] (4) By covering a new mask structure on the original mask structure, it is equivalent to increasing the etching selectivity between the original mask layer and silicon carbide, so that a larger etching depth-to-width ratio can be achieved (the depth-to-width ratio can reach more than 10:1, and the current level is about 5:1).

[0022] Other advantages of this application will be elaborated in the following specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a flowchart of a method for manufacturing a semiconductor structure according to a preferred embodiment of this application.

[0024] Figure 2 It is a schematic structural diagram after sequentially forming a first mask layer and a third mask layer on a substrate according to a preferred embodiment of this application.

[0025] Figure 3 It is a schematic structural diagram after patterning the third mask layer to form a third mask structure according to a preferred embodiment of this application.

[0026] Figure 4 It is a schematic structural diagram after patterning the first mask layer to form a first mask structure according to a preferred embodiment of this application.

[0027] Figure 5 It is a schematic structural diagram after removing the third mask structure according to a preferred embodiment of this application.

[0028] Figure 6 It is a schematic structural diagram after forming a composite mask structure according to a preferred embodiment of this application.

[0029] Figure 7 It is a schematic structural diagram after forming a trench on the surface of the substrate according to a preferred embodiment of this application.

[0030] In the figure, 10. silicon carbide substrate; 11. first mask layer; 111. first mask structure; 12. third mask layer; 121. third mask structure; 13. opening; 14. second mask layer; 141. second mask structure; 15. composite mask structure; 16. trench. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The current silicon carbide etching process method can meet the requirements of an etching structure with an aspect ratio of 5:1. To improve performance, a larger trench aspect ratio (for example, an aspect ratio of more than 10:1) is required. For the etching of high-aspect-ratio trenches in silicon carbide, due to the extremely high chemical stability and mechanical strength of silicon carbide itself, high-energy plasma is required during the etching process. When using a traditional silicon oxide mask layer as the etching mask, the following defects often exist: (1) Since the etching time of high-aspect-ratio trenches in silicon carbide is relatively long, silicon oxide is easily eroded during the long-term etching process, resulting in mask failure, unable to effectively protect the underlying silicon carbide material, and ultimately leading to problems such as large losses in the trench angle and critical dimensions of the silicon carbide trench.

[0032] (2) The original silicon oxide mask morphology may have morphological defects, such as micro-trenches, footing morphologies, etc., which will ultimately transfer these morphological defects to the silicon carbide trench.

[0033] (3) Under the long-term bombardment of high-energy plasma, silicon oxide is prone to form a micro-mask or polymer deposition on the sidewalls, resulting in an increase in sidewall roughness and transferring it to the underlying silicon carbide material. Or, after a long period of plasma etching, there is not enough silicon oxide to protect the underlying silicon carbide, which will also lead to an increase in the sidewall roughness of the silicon carbide trench, thereby affecting the device performance and stability.

[0034] (4) A large amount of heat is generated during the etching process. When the amount of effective silicon oxide is insufficient, it is easy to cause a local temperature rise, which in turn causes mask deformation, resulting in abnormal morphology of the formed silicon carbide trench.

[0035] In view of the above problems, the embodiments of the present application provide a method for manufacturing a semiconductor structure, including: Providing a silicon carbide substrate, on one side of the silicon carbide substrate, a plurality of first mask structures are formed, and there is an opening between adjacent two of the first mask structures, exposing the surface of the silicon carbide substrate; Depositing a second mask layer on the exposed surface of the first mask structure, and using the different deposition selectivities, making the deposition thickness of the second mask layer on the top surface of the first mask structure greater than the deposition thickness on the single-side side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact on the top surface and side surface of the first mask structure; Using the second mask structure and the first mask structure as masks, etching the silicon carbide substrate to form a high-aspect-ratio etching structure with a certain etching depth in the silicon carbide substrate; Wherein, the material of the second mask structure and the material of the first mask structure are the same hard mask material. The second mask structure is used to compensate for the original thickness of the first mask structure to reduce the original etching consumption of the first mask structure. At the etching end point, the second mask structure is completely etched away, exposing the surface of the remaining first mask structure.

[0036] In the embodiment of the present application, by covering and forming a second mask structure on the top surface and the side surface of the original first mask structure to form a composite mask structure, the damage to the original first mask structure during the etching process can be reduced, and the protection effect on the surface of the silicon carbide substrate is significantly improved. Thus, the problem that in the past, due to the long etching time of the silicon carbide high aspect ratio trench, the silicon oxide mask was easily eroded during the long-time etching process, resulting in mask failure, unable to effectively protect the underlying silicon carbide material, and ultimately leading to a large inclination of the silicon carbide trench angle and a large loss of the critical dimension of the trench is effectively solved.

[0037] Moreover, through the formed second mask structure, the defects brought by the original first mask structure itself can be compensated, and the thickness deficiency of the first mask structure can be compensated to avoid mask deformation. Thus, the sidewall roughness can be reduced during the etching process, a vertical angle can be obtained, and an ideal final etching morphology can be ensured, improving the device performance and stability.

[0038] Therefore, in the embodiment of the present application, by covering a new second mask structure on the original first mask structure, a dual protection mechanism for the original first mask structure and the silicon carbide substrate material can be formed. On the basis of ensuring the uniformity and accuracy of the etching morphology, the flexibility and reliability of the process can be improved, which is convenient for compatibility with the existing process, reduces the manufacturing cost, and at the same time can achieve a larger etching aspect ratio.

[0039] The embodiment of the present application also provides a semiconductor structure obtained by using the semiconductor structure manufacturing method provided by the embodiment of the present application.

[0040] The following will describe in detail the specific embodiments of the present application with reference to the accompanying drawings.

[0041] Reference Figure 1 . The embodiment of the present application provides a semiconductor structure manufacturing method, including the following steps: Step S11: Provide a silicon carbide substrate.

[0042] Reference Figure 2 . In some embodiments, a silicon carbide (SiC) substrate 10 (i.e., the material of the substrate is silicon carbide) is used for manufacturing a semiconductor structure in the embodiment of the present application. However, it can be understood that the semiconductor structure manufacturing method provided by the embodiment of the present application can also be applicable to other substrates other than silicon carbide.

[0043] In some embodiments, the silicon carbide substrate 10 may be undoped.

[0044] In some embodiments, the silicon carbide substrate 10 may be doped, for example, the silicon carbide substrate 10 is N-type doped or P-type doped to provide a silicon carbide substrate 10 that meets the required electrical properties.

[0045] In some embodiments, specific doped regions may also be formed on the silicon carbide substrate 10, such as N-type doped regions or P-type doped regions, etc. The above doped regions may have the same doping concentration or different doping concentrations, etc.

[0046] In some embodiments, an integrated circuit, such as a transistor structure, etc., may be fabricated on the silicon carbide substrate 10.

[0047] Step S12: A first mask layer and a third mask layer are sequentially formed on the surface of the silicon carbide substrate.

[0048] Reference Figure 2 . In some embodiments, first, a hard mask layer deposition technique in a conventional SiC high aspect ratio etching process is used to deposit a first mask layer 11 as a hard mask layer on the upper surface of the silicon carbide substrate 10 (i.e., the material of the first mask layer 11 is a hard mask material). Then, a spin coating technique is used to form a third mask layer 12 on the upper surface of the first mask layer 11.

[0049] In some embodiments, a first dielectric layer is deposited on the upper surface of the silicon carbide substrate 10 by using a PECVD deposition process to form a first mask layer 11. The deposition thickness of the first dielectric layer is the deposition thickness of the dielectric hard mask layer used in a conventional SiC high aspect ratio etching process.

[0050] In some embodiments, the first dielectric layer material includes silicon oxide (SiO2), and a silicon oxide deposition process used in a conventional SiC high aspect ratio etching process is used to deposit a silicon oxide first dielectric layer on the upper surface of the silicon carbide substrate 10, thereby forming a first mask layer 11 made of silicon oxide material. However, it can be understood that the material of the first mask layer 11 is not limited to silicon oxide. Taking the first mask layer 11 made of silicon oxide material as an example below, the semiconductor structure manufacturing method provided by the embodiments of the present application will be further described.

[0051] In some embodiments, a spin coating process is used to form a photoresist layer as the third mask layer 12 on the upper surface of the first mask layer 11 and then dry it. The thickness of the photoresist layer is the same as that used in the conventional SiC deep aspect ratio etching process. Therefore, the material of the third mask layer 12 is different from that of the first mask layer 11, and thus the material of the subsequently formed third mask structure is also different from that of the first mask structure.

[0052] Step S13: Pattern the third mask layer to form a third mask structure.

[0053] Reference Figure 3 . In some embodiments, a photolithography process is used to pattern the photoresist layer as the third mask layer 12, and a plurality of juxtaposed photoresist patterns are formed on the upper surface of the silicon oxide first dielectric layer (the first mask layer 11), and each photoresist pattern serves as a third mask structure 121. That is, the material of the third mask structure 121 includes photoresist.

[0054] It should be noted that Figure 3 only shows a schematic illustration of the case where 3 photoresist patterns (third mask structures 121) are formed on the upper surface of the silicon oxide first dielectric layer. However, it can be understood that at least 2 photoresist patterns can be formed on the upper surface of the silicon oxide first dielectric layer, such as 2 photoresist patterns, 3 photoresist patterns, 4 photoresist patterns, 10 photoresist patterns, etc., and is not limited thereto.

[0055] Step S14: Using the third mask structure as a mask, pattern the first mask layer to form a first mask structure, and then remove the third mask structure.

[0056] Reference Figure 4 . In some embodiments, a hard mask opening process is used. Using the photoresist pattern as the third mask structure 121 as a mask, the silicon oxide first dielectric layer as the first mask layer 11 is etched and patterned, and a plurality of silicon oxide patterns are formed on the upper surface of the silicon carbide substrate 10, and each silicon oxide pattern serves as a first mask structure 111. That is, the material of the first mask structure 111 includes silicon oxide.

[0057] After a plurality of first mask structures 111 are formed on the upper surface of the silicon carbide substrate 10, an opening 13 will be formed between any two adjacent first mask structures 111, and the upper surface of the silicon carbide substrate 10 located at the bottom surface of the opening 13 will be exposed. The above-mentioned opening 13 serves as a window for subsequent etching of the silicon carbide substrate 10.

[0058] In some embodiments, the process of etching and patterning the silicon oxide first dielectric layer as the first mask layer 11 includes a plasma dry etching process.

[0059] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the process gases used include fluorine-based gases, O2, Ar, etc., but are not limited thereto.

[0060] In some embodiments, the fluorine-based gas includes at least one of CHF3, CF4, and C4F8.

[0061] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the temperature is 10°C to 40°C. For example, the temperature can be 10°C, 15°C, 20°C, 25°C, 30°C, 35°C, or 40°C, or any value between any two of the aforementioned temperature values.

[0062] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the pressure is 5 mTorr to 50 mTorr. For example, the pressure can be 5 mTorr, 6 mTorr, 7 mTorr, 8 mTorr, 9 mTorr, 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, or 50 mTorr, or any value between any two of the aforementioned pressure values.

[0063] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the source power is 100 W to 2000 W. For example, the source power can be 100 W, 200 W, 300 W, 600 W, 800 W, 1000 W, 1200 W, 1500 W, or 2000 W, or any value between any two of the aforementioned source power values.

[0064] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the bias power is 10 W to 1000 W. For example, the bias power can be 10 W, 20 W, 60 W, 95 W, 100 W, 200 W, 300 W, 500 W, 700 W, or 1000 W, or any value between any two of the aforementioned bias power values.

[0065] In some embodiments, in the process of etching and patterning the first silicon oxide dielectric layer as the first mask layer 11, the radio frequency (RF) frequency of the RF source for generating the bias power adopts a fixed frequency. For example, the RF frequency can be a fixed 13.56 MHz, but is not limited thereto.

[0066] In some embodiments, a high-temperature resist stripping process (asher process) is used to remove the photoresist, that is, to remove the photoresist pattern as the third mask structure 121. After removing the photoresist pattern, the top surface and side surfaces of the first mask structure 111 will be exposed, and its structure is as Figure 5As shown

[0067] In some embodiments, when using a high-temperature photoresist stripping process to remove the photoresist pattern of the third mask structure 121, the process gas used includes at least one of O2, FG (a mixed gas of H2 and N2), N2, etc., but is not limited thereto.

[0068] In some embodiments, when using a high-temperature photoresist stripping process to remove the photoresist pattern of the third mask structure 121, the temperature is 100°C to 300°C. For example, the temperature can be 100°C, 120°C, 150°C, 180°C, 200°C, 230°C, 270°C, or 300°C, or any value between any two of the aforementioned temperature values.

[0069] In some embodiments, when using a high-temperature photoresist stripping process to remove the photoresist pattern of the third mask structure 121, the pressure is 100 mTorr to 1000 mTorr. For example, the pressure can be 100 mTorr, 200 mTorr, 300 mTorr, 400 mTorr, 500 mTorr, 600 mTorr, 700 mTorr, 800 mTorr, 900 mTorr, or 1000 mTorr, or any value between any two of the aforementioned pressure values.

[0070] In some embodiments, when using a high-temperature photoresist stripping process to remove the photoresist pattern of the third mask structure 121, the source power is 100 W to 5000 W. For example, the source power can be 100 W, 200 W, 500 W, 1000 W, 1500 W, 2000 W, 2500 W, 3000 W, 3500 W, 4000 W, 4500 W, or 5000 W, or any value between any two of the aforementioned source power values.

[0071] In some embodiments, when using a high-temperature photoresist stripping process to remove the photoresist pattern of the third mask structure 121, the bias power is zero.

[0072] Step S15: Form a second mask layer on the exposed surface of the first mask structure to form a second mask structure, and form a composite mask structure composed of the first mask structure and the second mask structure.

[0073] Reference Figure 6 In some embodiments, using a PECVD deposition process, deposit a second dielectric layer as the second mask layer 14 on the upper surface of the exposed silicon carbide substrate 10 and the surface (top surface and side surface) of the first mask structure 111.

[0074] In some embodiments, the material of the second dielectric layer is the same as that of the first dielectric layer, that is, the material of the subsequent second mask structure to be formed is the same as that of the first mask structure 111, and it is the same hard mask material.

[0075] In some embodiments, when the material of the first dielectric layer is silicon oxide, the material of the second dielectric layer is also silicon oxide. Taking the silicon oxide second dielectric layer as the second mask layer 14 as an example, the semiconductor structure manufacturing method provided by the embodiments of the present application will be further described below.

[0076] In some embodiments, a silicon oxide second dielectric layer serving as the second mask layer 14 is deposited on the upper surface of the silicon carbide substrate 10 and the surface of the first mask structure 111. During deposition, by using the different deposition selectivity ratios of the silicon oxide second dielectric layer (second mask layer 14) on the upper surface of the silicon carbide substrate 10, the top surface and the side surface of the first mask structure 111, the silicon oxide second dielectric layer is preferentially deposited on the top surface of the first mask structure 111 made of silicon oxide material, that is, the deposition thickness of the silicon oxide second dielectric layer on the top surface of the first mask structure 111 is significantly greater than the deposition thickness on the single-side side surface of the first mask structure 111 and the upper surface of the silicon carbide substrate 10, so as to form a second mask structure 141 made of silicon oxide material through the second dielectric layer completely coating the surface (top surface and side surface) of the first mask structure 111, and further form a composite mask structure 15 made of an integral silicon oxide material composed of the first mask structure 111 and the second mask structure 141 in direct contact with each other (that is, the material of the composite mask structure 15 is all the same silicon oxide material). Among them, the second mask structure 141 located on the side surface of the first mask structure 111 extends downward along the side surface of the first mask structure 111 until it contacts the upper surface of the silicon carbide substrate 10. In addition, the silicon oxide second dielectric layer deposited on the upper surface of the silicon carbide substrate 10 is not a part of the second mask structure 141.

[0077] Silicon carbide materials themselves have extremely high chemical stability and mechanical strength, so high-energy plasma is required during the etching process. When using a traditional silicon oxide mask layer (equivalent to the first mask layer) as the etching mask, due to the long etching time of silicon carbide high aspect ratio trenches, the silicon oxide mask material is easily eroded during the long etching process, resulting in mask failure and inability to effectively protect the underlying silicon carbide material, ultimately leading to problems such as tilting of the silicon carbide trench angle and significant loss of the critical dimension of the trench. In addition, the original silicon oxide mask (equivalent to the first mask structure) may have morphological defects such as micro-trenches and footing, which will ultimately transfer this morphological defect to the silicon carbide trench. Moreover, under the bombardment of high-energy plasma for a long time, the original silicon oxide mask is prone to forming a micro-mask or polymer deposition on the sidewalls, resulting in an increase in sidewall roughness and transferring it to the underlying silicon carbide material. Or, after a long time of plasma etching, there is not enough silicon oxide mask to protect the underlying silicon carbide, which will also lead to an increase in the sidewall roughness of the silicon carbide trench, thereby affecting the device performance and stability. Additionally, a large amount of heat is generated during the etching process. When the amount of effective silicon oxide mask is insufficient, it is easy to cause a local temperature increase, which in turn causes mask deformation, resulting in abnormal morphology of the formed silicon carbide trench.

[0078] In view of this, the embodiment of the present application adopts a new technology of covering a new mask structure (the second mask structure 141) on the original mask structure (the first mask structure 111). By forming the composite mask structure 15, it plays a role in reducing the damage to the original mask structure during the etching process, can significantly improve the protection effect on the surface of the silicon carbide substrate 10, and thus can effectively solve the problems of tilting of the silicon carbide trench angle and significant loss of the critical dimension of the trench caused by mask layer protection failure during the previous high aspect ratio etching process. And, by covering a new second mask structure 141 on the first mask structure 111, it is used to modify the surface of the first mask structure 111, can effectively improve the defects that may occur during patterning of the first mask structure 111, and plays a role in compensating for the insufficient thickness of the first mask structure 111, that is, it plays a role in reducing the original etching consumption of the first mask structure 111, thereby being able to reduce the sidewall roughness, obtain a vertical angle, and thus can improve the morphological defects during the etching of the silicon carbide substrate 10 to ensure an ideal final etching morphology. At the same time, the second mask structure 141 can not only play a role in protecting the original first mask structure 111, but also play a dual protection role in more effectively protecting the silicon carbide substrate 10 material, so as to improve the flexibility and reliability of the etching process on the basis of ensuring the uniformity and accuracy of the etching morphology.

[0079] In some embodiments, when depositing the second silicon oxide dielectric layer, the process gases used include a combination of HBr, SiCl4, SiF4O2, and Ar.

[0080] It should be noted that during the process of depositing the second silicon oxide dielectric layer, among the components generated by the reaction of the process gases, more are Si and O. Therefore, compared with the silicon carbide interface, it is easier to deposit on the surface of the first mask structure 111 made of silicon oxide material. In particular, it will preferentially deposit on the top surface of the first mask structure 111, while the actual deposition amount on the upper surface of the silicon carbide substrate 10 is very small, and the deposition amount on the side surface of the first mask structure 111 is also small, as Figure 6 shown. The purpose of this step of deposition is to thicken the overall mask layer (composite mask structure 15), so that during the subsequent etching process of the silicon carbide substrate 10, the underlying silicon carbide etching material can be better protected to obtain a better etching profile.

[0081] It should also be noted that the purpose of depositing the second mask layer 14 and forming the second mask structure 141 in the embodiments of the present application is not simply to increase the thickness of the first mask structure 111. Otherwise, only the deposition thickness of the first mask layer 11 needs to be directly increased, or the second mask layer 14 is continuously deposited on the basis of the first mask layer 11, and then a mask structure is formed by one-step etching to achieve the purpose of increasing the mask thickness. Instead, by depositing the second mask layer 14 on the already formed first mask structure 111, the surface of the first mask structure 111 is modified to pre-improve the defects generated during the patterning of the first mask structure 111, so that the morphology of the composite mask structure 15 formed after depositing the second mask layer 14 is good (i.e., mask defects are eliminated), thereby ensuring the acquisition of the final ideal etching profile.

[0082] In some embodiments, when depositing the second silicon oxide dielectric layer as the second mask layer 14, the temperature is -10°C to 30°C. For example, the temperature can be -10°C, -5°C, 0°C, 5°C, 10°C, 20°C, or 30°C, or any value between any two of the foregoing temperature values.

[0083] In some embodiments, when depositing the second silicon oxide dielectric layer, the pressure is 10 mtorr to 200 mtorr. For example, the pressure can be 10 mTorr, 20 mTorr, 30 mTorr, 50 mTorr, 70 mTorr, 100 mTorr, 120 mtorr, 150 mtorr, 180 mtorr, or 200 mtorr, or any value between any two of the foregoing pressure values.

[0084] In some embodiments, when depositing the second silicon oxide dielectric layer, the source power is 100W to 2000W. For example, the source power can be 100W, 300W, 500W, 700W, 900W, 1000W, 1300W, 1500W or 2000W, or any value between any two of the foregoing source power values.

[0085] In some embodiments, when depositing the second silicon oxide dielectric layer, the bias power is 10W to 100W. For example, the bias power can be 10W, 20W, 30W, 40W, 50W, 60W, 70W, 80W, 90W or 100W, or any value between any two of the foregoing bias power values.

[0086] In some embodiments, when depositing the second silicon oxide dielectric layer, the radio frequency (RF) frequency of the RF source for generating the source power uses a fixed frequency. For example, the RF frequency for generating the source power can be a fixed 13.56 MHz, but is not limited thereto.

[0087] In some embodiments, when depositing the second silicon oxide dielectric layer, the RF frequency of the RF source for generating the bias power uses a fixed frequency. For example, the RF frequency for generating the bias power can be a fixed 13.56 MHz, but is not limited thereto.

[0088] In some embodiments, when depositing the second silicon oxide dielectric layer, the RF frequency of the RF source for generating the source power is the same as the RF frequency of the RF source for generating the bias power. For example, the RF frequency of the RF source for generating the source power and the RF frequency of the RF source for generating the bias power are 13.56 MHz, but is not limited thereto.

[0089] In some embodiments, when depositing the second silicon oxide dielectric layer, the deposition time is optimized and adjusted according to the thickness of the original mask layer (the first mask layer 11), and the length of the deposition time is proportional to the deposition thickness of the second mask layer 14 (the second dielectric layer) on the top surface of the first mask structure 111.

[0090] In some embodiments, the ratio of the deposition thickness of the second mask layer 14 on the top surface of the first mask structure 111 to the deposition thickness of the second mask layer 14 on the upper surface of the silicon carbide substrate 10 is not less than 10:3, not less than 10:2 or not less than 10:1, etc., but is not limited thereto.

[0091] By adopting the above process gas system and selecting and combining various process parameter values within the above temperature, pressure, source power, and bias power ranges, a second mask layer 14 with the required thickness and high quality can be formed on the top surface of the first mask structure 111, so as to coat and form the required second mask structure 141 on the surface of the first mask structure 111, and jointly form a composite mask structure 15 with the underlying first mask structure 111, which can significantly improve the protection effect of the entire mask layer on the silicon carbide substrate 10, effectively improve the defects existing in the first mask structure 111, compensate for the deficiency of the original thickness of the first mask structure 111, reduce the sidewall roughness, obtain a vertical angle, and avoid mask deformation caused by high temperature, thereby laying a foundation for obtaining an ideal silicon carbide etching morphology in the subsequent process.

[0092] In some embodiments, in the direction perpendicular to the upper surface of the silicon carbide substrate 10, the ratio of the thickness (original thickness) of the second mask structure 141 to the thickness (original thickness) of the first mask structure 111 is 1:10 to 1:2. For example, the ratio of the thickness of the second mask structure 141 to the thickness of the first mask structure 111 is 1:10, 1:9, 1:8, 1:7, 1:6, 1:5, 1:4, 1:3, or 1:2, or any ratio between any two of the foregoing ratios.

[0093] It should be noted that if the original first mask layer 11 (first mask structure 111) is thick enough, only a relatively thin second mask layer 14 (second mask structure 141) needs to be deposited and formed on the first mask structure 111; vice versa. When etching the silicon carbide substrate 10 subsequently, the second mask layer 14 serves as a dielectric protection layer. Its main function is to prevent the problem of poor etching material morphology caused by the insufficient thickness of the original mask layer, which is difficult to provide a good shielding effect during high aspect ratio etching. Therefore, the thickness of the second mask layer 14 is to appropriately compensate for the thickness of the original mask layer, rather than completely replacing the original mask layer.

[0094] Step S16: Using the composite mask structure as a mask, etch the silicon carbide substrate to form a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate.

[0095] Reference Figure 7 . In some embodiments, using a plasma dry etching process, with the composite mask structure 15 as a mask, etch the silicon carbide substrate 10 downward to form a silicon carbide high aspect ratio etching structure located in the silicon carbide substrate 10 and having a certain etching depth on the upper surface of the silicon carbide substrate 10 (i.e., the bottom surface of the opening 13) between any two adjacent composite mask structures 15 of silicon oxide materials.

[0096] It should be noted that when etching the silicon carbide substrate 10 downward, it is necessary to first etch and remove a small amount of silicon oxide (the second dielectric layer) on the bottom surface of the opening 13, and then continue to etch the exposed silicon carbide substrate 10. Since the thickness of the silicon oxide (the second dielectric layer) on the bottom surface of the opening 13 is very thin, when etching and removing it, there is still a lot of surplus of the silicon oxide second dielectric layer on the top of the composite mask structure 15, and the impact on the consumption of the silicon oxide second dielectric layer material on the top of the composite mask structure 15 is very small. Therefore, it is possible to provide a sufficient consumption amount of the silicon oxide material of the composite mask structure 15 during the etching process, avoiding the problem that the remaining silicon oxide mask material may be insufficient at the etching end point.

[0097] In some embodiments, during the etching process, the silicon oxide material of the composite mask structure 15 will be gradually consumed. Therefore, when reaching the etching end point, the remaining thickness of the composite mask structure 15 will be less than the original thickness of the first mask structure 111. In other words, at the etching end point, at least the second mask structure 141 on the top surface of the first mask structure 111 is removed, exposing the top surface of the remaining first mask structure 111.

[0098] In some embodiments, at the etching end point, the second mask structure 141 is completely etched and removed, exposing the top surface and side surface of the remaining first mask structure 111.

[0099] By coating the second mask layer 14 on the first mask structure 111 to form the second mask structure 141, the thickness of the composed composite mask structure 15 is increased compared to the original thickness of the first mask structure 111, so that the available consumed mask thickness is increased, which is equivalent to increasing the etching selectivity between the silicon oxide of the original mask layer and the silicon carbide substrate 10 (that is, reducing the ratio of the consumption amount of the silicon oxide of the original mask layer to the consumption amount of the silicon carbide substrate 10). The remaining thickness of the silicon oxide mask material after etching in the embodiments of the present application is significantly increased compared to the remaining thickness of the silicon oxide mask material in the existing process, which can avoid causing greater damage to the critical dimension at the top of the etching, thereby ensuring the verticality of the etching angle. And it can avoid the defects such as rough sidewalls caused by the large damage to the mask layer in the previous etching process, so that in the subsequent etching process, it can be avoided that such defects will be directly transmitted to the underlying silicon carbide etching material, resulting in poor roughness of the sidewalls of the etching material.

[0100] In some embodiments, the high aspect ratio etching structure includes trenches (deep trenches), deep vias (Deep Via), through vias (Through Via), etc. with an aspect ratio of 5:1 or more. Hereinafter, taking the trench 16 as the high aspect ratio etching structure as an example, the embodiments of the present application will be further described in detail.

[0101] In some embodiments, an anisotropic etching process is performed to etch the silicon carbide substrate 10 to form trenches 16. The process gases used include at least one of SF6, SiCl4, and SiF4, as well as O2. In addition, at least one of N2, He, Ar, HBr, and BCl3 can be used simultaneously. Among them, N2 and He are used as common dilution dissociation gases, and Ar and BCl3 are used as dissociation gases with a certain bombardment ability. And the etching method is mainly anisotropic etching (different from the isotropic etching of the Bosch process used for deep silicon etching).

[0102] In some embodiments, after etching the silicon carbide substrate 10, the remaining thickness of the first mask structure 111 is more than 1 / 3 of the sum of the original thickness of the second mask structure 141 and the original thickness of the first mask structure 111 (i.e., the original thickness of the composite mask structure 15).

[0103] In some embodiments, when etching the silicon carbide substrate 10, the process gases used include SF6, BCl3, O2, N2, Ar, and He.

[0104] In particular, when a very high aspect ratio is required, such as an aspect ratio reaching 10:1 or more, when etching the silicon carbide substrate 10, the process gases used include HBr and at least one of SiCl4 and SiF4.

[0105] In some embodiments, when etching the silicon carbide substrate 10, the temperature is -10°C to 30°C. For example, the temperature can be -10°C, -5°C, -1°C, 0°C, 3°C, 5°C, 10°C, 20°C, or 30°C, or any value between any two of the aforementioned temperature values.

[0106] In some embodiments, when etching the silicon carbide substrate 10, the pressure is 10 mtorr to 100 mtorr. For example, the pressure can be 10 mTorr, 20 mTorr, 30 mTorr, 40 mTorr, 50 mTorr, 60 mTorr, 70 mtorr, 80 mtorr, 90 mtorr, or 100 mtorr, or any value between any two of the aforementioned pressure values.

[0107] In some embodiments, when etching the silicon carbide substrate 10, the source power is 100 W to 3000 W. For example, the source power can be 100 W, 200 W, 500 W, 800 W, 1000 W, 1500 W, 2000 W, 2500 W, or 3000 W, or any value between any two of the aforementioned source power values.

[0108] In some embodiments, when etching the silicon carbide substrate 10, the bias power is 10 W to 1000 W. For example, the bias power can be 10 W, 50 W, 100 W, 200 W, 300 W, 400 W, 500 W, 600 W, 700 W, 800 W, 900 W, or 1000 W, or any value between any two of the foregoing bias power values.

[0109] In some embodiments, when etching the silicon carbide substrate 10, the radio frequency (RF) frequency of the RF source for generating the source power uses a fixed frequency. For example, the RF frequency for generating the source power can be a fixed 13.56 MHz, but is not limited thereto.

[0110] In some embodiments, when etching the silicon carbide substrate 10, the RF frequency of the RF source for generating the bias power uses a variable frequency. For example, the RF frequency for generating the bias power can alternate between two frequencies of 13.56 MHz and 400 KHz to obtain a trench 16 with a higher aspect ratio (e.g., greater than 10:1), but is not limited thereto.

[0111] Step S17: Compare the etching depth with the target depth. When the etching depth reaches the target depth, execute Step S18; when the etching depth is less than the target depth, return to execute Step S15.

[0112] After performing the etching process on the silicon carbide substrate 10 once as described above, by comparing the etched depth of the formed trench 16 with the target depth and making a judgment, it is determined whether to end the etching process of the silicon carbide substrate 10. Among them, if the etching depth has reached the target depth, the end step (Step S18) is executed. On the contrary, if the etching depth is less than the target depth, return to repeat the process of depositing the second mask layer 14 (Step S15) and etching the silicon carbide substrate 10 (Step S16), that is, repeat the process of depositing the second mask layer 14 on the exposed surface of the first mask structure 111 and etching the silicon carbide substrate 10 using the second mask structure 141 and the first mask structure 111 as masks, until the etching depth (total etching depth, that is, the total depth of the formed trench 16) tends to be consistent with the target depth. At this time, the entire etching process of the silicon carbide substrate 10 is ended, and the manufacturing of the semiconductor structure is completed (i.e., Step S18 is completed).

[0113] The above deposition process of depositing the second mask layer 14 on the top surface of the first mask structure 111 and forming the second mask structure 141, and the process of etching the silicon carbide substrate 10 can be used as two process steps (process links) in the overall process of etching the high aspect ratio trench of silicon carbide. Therefore, it can be included in the process menu for controlling the etching of the high aspect ratio trench of silicon carbide and can be completed in the same plasma etching chamber (equipment).

[0114] It should be noted that when the deposition of the second silicon oxide dielectric layer (the second mask layer 14) is carried out cyclically, a small amount of the second silicon oxide dielectric layer will also be deposited on the inner wall of the formed trench 16. During the subsequent etching step, by using the small amount of the second silicon oxide dielectric layer deposited on the inner wall of the formed trench 16, it can also play a certain protective role for the sidewall of the trench 16 during the etching process, which can avoid over-etching of the sidewall of the trench 16, thereby avoiding the problems of increased roughness of the sidewall of the trench 16 and non-perpendicular angle of the trench 16.

[0115] In some embodiments, the number of cycles of depositing the second mask layer 14 and etching the silicon carbide substrate 10 is 1 to 5 times, 1 to 4 times, or 1 to 3 times. For example, the number of cycles can be 1 time, 2 times, 3 times, 4 times, or 5 times. The number of cycles can be determined according to the thickness of the original mask layer and the requirement for increasing the aspect ratio. When the thickness of the original mask layer is relatively small, the number of cycles needs to be relatively increased. When the aspect ratio increases, the number of cycles also needs to be relatively increased.

[0116] In some embodiments, when the number of cycles of etching the silicon carbide substrate 10 is multiple times, after each etching process of the silicon carbide substrate 10 is performed, the remaining thickness of the composite mask structure 15 is more than 1 / 3 of the original thickness of the composite mask structure 15. For example, after any cycle etching process is performed, the remaining thickness of the composite mask structure 15 is more than 3 / 9, 4 / 9, 4 / 9, 4.5 / 9, 6 / 9, 7 / 9, or 8 / 9 of the original thickness of the composite mask structure 15, etc., but it is not limited thereto.

[0117] In some embodiments, when the number of cycles of etching the silicon carbide substrate 10 is multiple times, the etching amount (depth) of each time is different. However, the total etching depth after multiple etchings should tend to be consistent with the target depth.

[0118] In some embodiments, when the number of cycles of etching the silicon carbide substrate 10 is multiple times, the etching amount of each time decreases in sequence. However, the total etching depth after multiple etchings should tend to be consistent with the target depth.

[0119] In some embodiments, when the number of etching cycles for the silicon carbide substrate 10 is multiple, the etching time for each time is different. However, the total etching time for multiple etchings should be consistent with the overall set etching time in the process menu of the silicon carbide high aspect ratio trench etching process.

[0120] In some embodiments, when the number of etching cycles for the silicon carbide substrate 10 is multiple, the etching time for each time decreases in sequence. However, the total etching time for multiple etchings should be consistent with the overall set etching time in the process menu of the silicon carbide high aspect ratio trench etching process.

[0121] Step S18: End.

[0122] When the etching depth reaches the target depth such that the aspect ratio of the formed trench 16 meets the requirements, the etching of the silicon carbide substrate 10 can be stopped, and the high aspect ratio etching process for the silicon carbide substrate 10 can be completed.

[0123] In some embodiments, after etching is completed, the polymers generated by etching can be completely removed through conventional wet processing (such as chemical cleaning) or a degumming process to ensure the integrity of the final silicon carbide etched morphology.

[0124] In some embodiments, the aspect ratio of the obtained trench 16 is at least 5:1 or more. For example, with the current silicon carbide etching process method, a trench with an aspect ratio of 5:1 can be formed. Using the semiconductor structure manufacturing method provided in the embodiments of the present application, the aspect ratio of the formed trench 16 can reach 10:1 or more.

[0125] The embodiments of the present application further provide a semiconductor structure, which is obtained by using the semiconductor structure manufacturing method corresponding to the above embodiments.

[0126] Reference Figure 7 In some embodiments, the semiconductor structure includes a silicon carbide substrate 10 and a trench 16 formed on the silicon carbide substrate 10 by using the semiconductor structure manufacturing method of the above embodiments to form a silicon carbide device.

[0127] In some embodiments, the aspect ratio of the trench 16 on the semiconductor structure is at least 5:1.

[0128] In some embodiments, the aspect ratio of the trench 16 on the semiconductor structure is 10:1 or more.

[0129] In some embodiments, the trench 16 on the semiconductor structure can be a silicon carbide superjunction trench structure.

[0130] In some embodiments, the silicon carbide device formed through the semiconductor structure can be a Dynamic Random Access Memory (DRAM), a Static Random-Access Memory (SRAM), a flash EPROM, a Ferroelectric Random Access Memory (FeRAM), a Magnetic Random-Access Memory (MRAM), or other types of memories.

[0131] In a third aspect, an embodiment of the present application further provides a plasma processing device, which is used to execute the semiconductor structure manufacturing method corresponding to the above embodiment to manufacture the semiconductor structure corresponding to the above embodiment. The plasma processing device can be, for example, an inductively coupled plasma (ICP) etching device or a capacitively coupled plasma (CCP) etching device, etc.

[0132] In other aspects, an embodiment of the present application further provides an electronic device, including the semiconductor structure of the above embodiment or the semiconductor structure obtained by using the semiconductor structure manufacturing method of the above embodiment. The electronic device can be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

[0133] In summary, in the embodiment of the present application, by covering and forming the second mask structure 141 on the original first mask structure 111 to form the composite mask structure 15, the damage to the first mask structure 111 during the etching process can be reduced, and the protection effect on the surface of the silicon carbide substrate 10 is significantly improved. Moreover, through the formed second mask structure 141, the defects brought by the original first mask structure 111 itself can be compensated, and the thickness deficiency of the second mask structure 141 can be compensated to avoid mask deformation, ensure an ideal final etching morphology, improve the device performance and stability, improve the flexibility and reliability of the process on the basis of ensuring the uniformity and accuracy of the etching morphology, facilitate compatibility with the existing process, reduce the manufacturing cost, and at the same time achieve a larger etching aspect ratio.

[0134] The above are only the preferred embodiments of the present application, and the embodiments are not intended to limit the protection scope of the present application. Therefore, all equivalent changes made by using the description and drawings of the present application should, by the same token, be included in the protection scope of the present application.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, Comprising: Providing a silicon carbide substrate, on one side of which a plurality of first mask structures are formed, and there is an opening between two adjacent first mask structures, exposing the surface of the silicon carbide substrate; Depositing a second mask layer on the exposed surface of the first mask structure, the deposition thickness of the second mask layer on the top surface of the first mask structure is greater than the deposition thickness on the single-side surface of the first mask structure and the exposed surface of the silicon carbide substrate, so as to form a second mask structure in direct contact on the top surface and side surface of the first mask structure; Using the second mask structure and the first mask structure as masks to etch the silicon carbide substrate, and forming a high aspect ratio etching structure with a certain etching depth in the silicon carbide substrate; Wherein, the material of the second mask structure and the material of the first mask structure are the same hard mask material, and the second mask structure is used to compensate for the original thickness of the first mask structure to reduce the original etching consumption of the first mask structure; At the etching end point, the second mask structure is completely etched away, exposing the surface of the remaining first mask structure.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein The second mask structure is further used to modify the surface of the first mask structure to improve the topography defects during the etching of the silicon carbide substrate.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein Also comprising: Comparing the etching depth with the target depth, when the etching depth is less than the target depth, repeatedly execute the processes of depositing the second mask layer on the exposed surface of the first mask structure and etching the silicon carbide substrate using the second mask structure and the first mask structure as masks until the etching depth tends to be consistent with the target depth.

4. The method for manufacturing a semiconductor structure according to claim 3, wherein The number of times of depositing the second mask layer and etching the silicon carbide substrate is 1 to 3 times; and / or when the number of times of etching the silicon carbide substrate is multiple times, the etching amount of each time decreases in sequence; and / or when the number of times of etching the silicon carbide substrate is multiple times, the etching time of each time decreases in sequence.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein After etching the silicon carbide substrate, make the remaining thickness of the first mask structure be more than 1 / 3 of the sum of the original thickness of the second mask structure and the original thickness of the first mask structure.

6. The method for manufacturing a semiconductor structure according to claim 1, wherein The ratio of the original thickness of the second mask structure to the original thickness of the first mask structure is 1:10 to 1:

2.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein, The materials of the first mask structure and the second mask structure include silicon oxide.

8. The method for manufacturing a semiconductor structure according to claim 1, wherein, Using an anisotropic etching process to etch the silicon carbide substrate.

9. The method for manufacturing a semiconductor structure according to claim 1, wherein When depositing the second mask layer, the temperature is -10°C to 30°C, the pressure is 10 mtorr to 200 mtorr, the source power is 100 W to 2000 W, and the bias power is 10 W to 100 W; and / or when etching the silicon carbide substrate, the temperature is -10°C to 30°C, the pressure is 10 mtorr to 100 mtorr, the source power is 100 W to 3000 W, and the bias power is 10 W to 1000 W; and / or the aspect ratio of the high aspect ratio etching structure is 5:1 or more.

10. A semiconductor structure, characterized in that, Obtained by using the method for manufacturing a semiconductor structure according to any one of claims 1-9.

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