Method for reducing generation of defects in polycrystalline silicon etching process
By introducing sacrificial layers and specific dry and wet etching processes during polysilicon etching, the defect problem in polysilicon etching is solved and the yield of CMOS image sensor is improved.
Patent Information
- Application Number
- CN202311846405.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-28
- Publication Date
- 2025-07-08
AI Technical Summary
During the polysilicon etching process of CMOS image sensors, there are a large number of random tapered defects, which affect yield stability, especially specific tapered defects, which will lead to yield loss.
During the polysilicon etching process, by depositing a sacrificial layer on the surface of the polysilicon and forming a patterned first photoresist layer, after F ion implantation, part of the first photoresist layer is removed by dry etching of N2H2 and O2, and the residual sacrificial layer is removed by wet etching to reduce defect generation.
It effectively reduces the polysilicon etching defect caused by the reaction product of F ions and the photoresist layer, and improves the yield of the image sensor.
Smart Images
Figure CN120280343A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuits, and particularly to a method for reducing defect generation during polysilicon etching. Background Art
[0002] In products of CMOS image sensors, polysilicon (Poly) is used as a gate electrode. When the doping concentration of N-type ions (such as phosphorus (P)) is limited, a voltage drop will occur, and there will be an electric field therein. As a result, electrons at the silicon dioxide (SiO2) interface are easily attracted by the electric field to one side of the gate electrode, leading to the appearance of a depletion layer at the interface.
[0003] The main function of the NPO (NMOS Poly pre-dope) process is that for NMOS polysilicon, after polysilicon deposition, the doped N-type ions need to reach the interface between the polysilicon and the gate oxide layer to prevent the occurrence of polysilicon depletion. The injection of F ions incorporated in the NPO process is to improve the Random Telegraph Signal (RTS) noise.
[0004] To etch polysilicon into a better topography, the polysilicon etch (Poly Etch) process usually uses a hard mask (HM) as an etching barrier layer. PEOX (Plasma Enhanced Oxide) is used as HM1, which usually has a relatively low deposition rate and high density to prevent the precipitation of ions in the polysilicon. Low Temperature Oxide (LTO) is used as HM2 to reduce the impact on gate damage.
[0005] For the formation process of CMOS image sensors, a large number of random cone defects have been found in the polysilicon etching process. CMOS image sensors are sensitive to some specific cone defects, and some cone defects will cause loss of yield, seriously affecting the stability of the yield of CMOS image sensors. Summary of the Invention
[0006] Based on the above problems, an embodiment of the present invention provides a method for reducing defect generation during polysilicon etching, at least including: providing a substrate and forming a polysilicon layer on the substrate; depositing a sacrificial layer on the surface of the polysilicon, and forming a patterned first photoresist layer on the sacrificial layer; injecting F ions into the polysilicon layer; removing a part of the first photoresist layer that has reacted with F ions; removing the remaining first photoresist layer and the sacrificial layer that have reacted with F ions and remain on the surface of the sacrificial layer, thereby reducing the generation of defects during subsequent polysilicon etching.
[0007] In some embodiments, the removing a part of the first photoresist layer that has reacted with F ions includes: removing a part of the first photoresist layer that has reacted with F ions by dry etching with N2H2 and O2.
[0008] In some embodiments, the parameters for removing a part of the first photoresist layer that has reacted with F ions by dry etching with N2H2 and O2 include: the process parameters for the first dry etching with N2H2 and O2 are: the pressure range is: 800~2500mT; the radio frequency power range is: 1500~3000w, the radio frequency time range is: 10~120s; the O2 / N2H2 gas flow ratio is: 2 / 1; the process parameters for the second dry etching with N2H2 and O2 are: the pressure range is: 500~2000mT; the radio frequency power range is: 2000~5000w, the radio frequency time range is: 10~120s; the O2 / N2H2 gas flow ratio is: 11 / 1.
[0009] In some embodiments, the sacrificial layer is at least one of silicon oxide, silicon nitride or silicon oxynitride. In some embodiments, the remaining first photoresist layer and the sacrificial layer that have reacted with F ions and remain on the surface of the sacrificial layer are removed by wet etching.
[0010] In some embodiments, the thickness of the patterned first photoresist layer is greater than 3100A.
[0011] In some embodiments, it further includes: forming a hard mask layer on the polysilicon layer; forming a patterned second photoresist layer on the hard mask layer; etching and removing a part of the hard mask layer and a part of the polysilicon layer to form a polysilicon gate.
[0012] In some embodiments, the injecting F ions into the polysilicon layer includes: injecting P ions into the polysilicon layer; injecting F ions into the polysilicon layer.
[0013] In some embodiments, providing a substrate and forming a polysilicon layer on the substrate includes: providing a substrate; forming a gate dielectric layer on the substrate; and forming the polysilicon layer on the gate dielectric layer.
[0014] In some embodiments, the method is applied to a CMOS image sensor.
[0015] The technical solution of the present invention can significantly reduce the defects caused by the reaction products of F ions and the first photoresist layer during the subsequent polysilicon etching by adding a sacrificial layer, thereby improving the yield of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 A method for forming a gate by etching polysilicon for an image sensor according to the present invention.
[0017] Figures 2 to 7 is Figure 1 a schematic structural diagram during the process of forming a gate by etching polysilicon for an image sensor.
[0018] Figure 8 A new method for forming a gate by etching polysilicon for an image sensor according to the present invention.
[0019] Figures 9 to 16 is Figure 8 a schematic structural diagram during the process of forming a gate by etching polysilicon for an image sensor. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some examples or embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, the present invention can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the figures represent the same structure or operation.
[0021] Figure 1 A method for forming a gate by etching polysilicon for an image sensor according to the present invention. The method includes the following steps.
[0022] Step S11: Provide a substrate.
[0023] For step S11, refer to Figure 2, the substrate 101 can be doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI), or a combination thereof. The substrate 101 can include a substrate with multiple epitaxial layers. The substrate 101 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive external optical signals and convert them into electrical signals for imaging. The specific structures of the pixel region and the logic region of the image sensor are not described in detail herein.
[0024] Step S12: Form a first dielectric layer and a polysilicon layer on the substrate.
[0025] For step S12, refer to Figure 2 , the first dielectric layer 102 and the polysilicon layer 103 can be formed on the substrate 101 by deposition. The first dielectric layer 102 is silicon oxide.
[0026] Step S13: Form a patterned first photoresist layer on the polysilicon layer.
[0027] For step S13, refer to Figure 2 , the first photoresist layer 104 can be formed on the polysilicon layer 103 by spin coating. The first photoresist layer 104 is photoresist. Through exposure and development, a patterned first photoresist layer 104 is formed.
[0028] Step S14: Inject at least F ions into the polysilicon layer.
[0029] For step S14, refer to Figure 3 , F ions 105 are injected into the polysilicon layer 103. Part of the F ions 105 are injected into the first photoresist layer 104 and react with the first photoresist layer to form a reaction product 106. A part of the F ions 105 are injected into the polysilicon layer 103. Before injecting the F ions, a step of injecting P ions is also required.
[0030] Step S15: Remove the first photoresist layer after reacting with F ions by dry etching with O2 and N2H2.
[0031] For step S15, refer to Figure 4 , the first photoresist layer (or the reaction product 106) after reacting with F ions is removed by dry etching with O2 and N2H2. In this step, the reaction product 106 on the surface of the polysilicon layer 103 cannot be completely removed, and part of the reaction product 106 remains on the surface of the polysilicon layer 103. The reaction product 106 has relatively high hardness and is prone to forming defects in subsequent etching processes.
[0032] Step S16: Remove the residues on the surface of the polysilicon layer by wet etching.
[0033] For step S16, the residue is removed by wet etching, but the reactant 106 is still very difficult to remove.
[0034] Step S17: Form a hard mask layer on the polysilicon layer, and form a patterned second photoresist layer on the hard mask layer.
[0035] For step S17, refer to Figure 5 , a hard mask layer 107 is deposited and formed on the polysilicon layer 103, and a patterned second photoresist layer 108 is formed on the hard mask layer 107. The hard mask layer 107 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 108 is a photoresist.
[0036] Step S18: Etch away part of the hard mask layer and part of the polysilicon layer to form a polysilicon gate.
[0037] For step S18, refer to Figure 6 and Figure 7 , after etching away part of the hard mask layer 107, there is still the reactant 106 on the surface of the polysilicon layer 103. Due to the presence of the reactant 106, after etching away part of the polysilicon layer 103, there is unremoved polysilicon 103 on the surface of the substrate 101, thus forming a defect 109. This defect 109 will reduce the yield of the image sensor chip.
[0038] To avoid the defect 109 generated during the subsequent etching process of the polysilicon 103 due to the product 106 formed by the reaction of the F ions with the first photoresist layer 104, the present invention also provides a new polysilicon etching process.
[0039] Figure 8 A method for etching polysilicon to form a gate for an image sensor according to the present invention. The method includes the following steps.
[0040] Step S21: Provide a substrate and form a polysilicon layer on the substrate.
[0041] For step S21, refer to Figure 9 , the substrate 201 can be a doped or undoped semiconductor material, such as silicon, germanium, silicon germanium, silicon germanium on insulator (SGOI), or a combination thereof. The substrate 201 can include a substrate with multiple epitaxial layers. The substrate 201 includes a pixel region and a logic region of the image sensor. The pixel region of the image sensor is used to receive an external optical signal and convert it into an electrical signal for imaging. The specific structures of the pixel region and the logic region of the image sensor are not described in detail here. Refer to Figure 9 , the gate oxide layer 202 and the polysilicon layer 203 can be formed on the substrate 201 by deposition. The gate oxide layer 202 can be silicon oxide.
[0042] Step S22: Deposit a sacrificial layer on the surface of the polysilicon, and form a patterned first photoresist layer on the sacrificial layer.
[0043] For step S22, refer to Figure 10 , deposit a sacrificial layer 203a on the surface of polysilicon 203. The first photoresist layer 204 can be formed on the sacrificial layer 203a by spin coating. The sacrificial layer 203a is at least one of silicon oxide, silicon nitride, or silicon oxynitride. The first photoresist layer 204 is a photoresist. Through exposure and development, a patterned first photoresist layer 204 is formed. The thickness of the patterned first photoresist layer 204 is greater than 3100 Å.
[0044] Step S23: Inject F ions into the polysilicon layer.
[0045] For step S23, refer to Figure 11 , inject F ions 205 into the polysilicon layer 203. Part of the F ions 205 are injected into the first photoresist layer 204 and react with the first photoresist layer to form a reaction product 206. A part of the F ions 205 are injected into the polysilicon layer 203. Before injecting F ions, a step of injecting P ions is also required.
[0046] Step S24: Remove part of the first photoresist layer that has reacted with F ions.
[0047] For step S24, refer to Figure 12 , remove part of the first photoresist layer (or reaction product 206) that has reacted with F ions by dry etching with N2H2 and O2.
[0048] The parameters for removing part of the first photoresist layer that has reacted with F ions by dry etching with N2H2 and O2 are as follows: The process parameters for the first dry etching with N2H2 and O2 are: the pressure range is 800 - 2500 mT; the RF power range is 1500 - 3000 w, the RF time range is 10 - 120 s; the O2 / N2H2 gas flow ratio is 2 / 1. The process parameters for the second dry etching with N2H2 and O2 are: the pressure range is 500 - 2000 mT; the RF power range is 2000 - 5000 w, the RF time range is 10 - 120 s; the O2 / N2H2 gas flow ratio is 11 / 1.
[0049] Step S25: Remove the remaining first photoresist layer that has reacted with F ions and the sacrificial layer staying on the surface of the sacrificial layer, thereby reducing the generation of defects during subsequent polysilicon etching.
[0050] For step S25, refer to Figure 13, the remaining first photoresist layer (or reactant 206) after reacting with F ions and the sacrificial layer 203a that remain on the surface of the sacrificial layer 203a are removed by wet etching.
[0051] Further, referring to Figure 14 , a hard mask layer 207 is deposited on the polysilicon layer 203, and a patterned second photoresist layer 208 is formed on the hard mask layer 207. The hard mask layer 207 is made of materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. The second photoresist layer 208 is a photoresist.
[0052] Further, referring to Figure 15 : Part of the hard mask layer 207 and part of the polysilicon layer 203 are etched away to form a polysilicon gate.
[0053] Further, referring to Figure 16 , the substrate 201 is ion-implanted to form the source 208 and drain 209 of the transistor.
[0054] Figure 1 In the embodiment shown, for step S18, referring to Figure 6 and Figure 7 , after part of the hard mask layer 107 is etched away, there is still a reactant 106 on the surface of the polysilicon layer 103. Due to the presence of the reactant 106, after part of the polysilicon layer 103 is etched away, there is unetched polysilicon 103 on the surface of the substrate 101, thus forming a defect 109. This defect 109 will reduce the yield of the image sensor chip.
[0055] Figure 8 The described embodiment can significantly reduce the defects caused by the products of the reaction between F ions and the first photoresist layer during subsequent polysilicon etching, thereby improving the yield of the image sensor.
[0056] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only an example and does not constitute a limitation to the present invention. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to the present invention. Such modifications, improvements, and corrections are proposed in the present invention, so such modifications, improvements, and corrections still fall within the spirit and scope of the exemplary embodiments of the present invention. It should be understood that the embodiments described in the present invention are only used to illustrate the principles of the embodiments of the present invention. Other variations may also fall within the scope of the present invention. Therefore, by way of example and not limitation, alternative configurations of the embodiments of the present invention can be considered to be in accordance with the teachings of the present invention. Accordingly, the embodiments of the present invention are not limited to the embodiments explicitly introduced and described in the present invention.
Claims
1. A method for reducing defect generation during the etching process of polysilicon, characterized in that, At least include: Provide a substrate and form a polysilicon layer on the substrate; Deposit a sacrificial layer on the surface of the polysilicon and form a patterned first photoresist layer on the sacrificial layer; Inject F ions into the polysilicon layer; Remove a part of the first photoresist layer reacted with F ions; Remove the remaining first photoresist layer reacted with F ions and the sacrificial layer staying on the surface of the sacrificial layer, thereby reducing the generation of defects in the subsequent polysilicon etching process.
2. The method according to claim 1, characterized in that, The removing a part of the first photoresist layer reacted with F ions includes: removing a part of the first photoresist layer reacted with F ions by dry etching with N2H2 and O2.
3. The method according to claim 2, characterized in that, The parameters of removing a part of the first photoresist layer reacted with F ions by dry etching with N2H2 and O2 include: The process parameters of the first dry etching with N2H2 and O2 are: The pressure range is: 800~2500mT; The RF power range is: 1500~3000w, and the RF time range is: 10~120s; The O2 / N2H2 gas flow ratio is: 2 / 1; The process parameters of the second dry etching with N2H2 and O2 are: The pressure range is: 500~2000mT; The RF power range is: 2000~5000w, and the RF time range is: 10~120s; The O2 / N2H2 gas flow ratio is: 11 / 1.
4. The method according to claim 1, characterized in that The sacrificial layer is at least one of silicon oxide, silicon nitride or silicon oxynitride.
5. The method according to claim 4, characterized in that, Remove the remaining first photoresist layer reacted with F ions and the sacrificial layer staying on the surface of the sacrificial layer by wet etching.
6. The method according to claim 1, wherein The thickness of the patterned first photoresist layer is greater than 3100A.
7. The method according to claim 1, wherein Further include: Form a hard mask layer on the polysilicon layer; Form a patterned second photoresist layer on the hard mask layer; Etch and remove a part of the hard mask layer and a part of the polysilicon layer to form a polysilicon gate.
8. The method according to claim 1, wherein The injecting F ions into the polysilicon layer includes: Inject P ions into the polysilicon layer; Inject F ions into the polysilicon layer.
9. The method according to claim 1, characterized in that, The providing a substrate and forming a polysilicon layer on the substrate includes: Provide a substrate; Form a gate dielectric layer on the substrate; Form the polysilicon layer on the gate dielectric layer.
10. The method according to claim 1, characterized in that, The method is applied to a CMOS image sensor.