Manufacturing method of packaging substrate, packaging substrate and electronic equipment

Abstract

The invention discloses a manufacturing method of a packaging substrate, the packaging substrate and electronic equipment, and the method comprises the steps: providing a packaging core plate, and forming a groove body which exposes a conductive layer in one side surface of the packaging core plate; forming a soldering tin pad on the conductive layer in the groove body; the thickness of the soldering pad is smaller than the depth of the groove body; forming a resistance welding bridge on one side surface of the packaging core plate; forming a solder ball on the solder pad, so that the solder ball protrudes out of one side surface, deviating from the packaging core plate, of the solder bridge; leveling the side surface, deviating from the packaging core plate, of the solder ball until the distance between the side surface and the side surface, deviating from the packaging core plate, of the solder bridge is within a set threshold range; wherein the set threshold range is greater than 0. According to the manufacturing method of the package substrate, the solder pads are arranged between the solder balls and the conductive layer in the package core plate, so that the outer side of the package core plate is effectively prevented from being damaged, the risk of breaking the conductive layer in the package core plate is reduced, and the reliability of the package substrate is improved.

Description

Technical Field

[0001] The present application relates to the technical field of packaging substrates, and in particular to a method for manufacturing a packaging substrate, a packaging substrate and an electronic device. Background Art

[0002] Nowadays, as a carrier of electronic components and chips, the overall layout density of printed packaging substrates, especially the chip interconnection density, is gradually increasing to achieve richer and higher-quality working performance, thereby reducing the distance between the passive components in the packaging substrate and the chip for welding interconnection.

[0003] In order to prevent the risk of welding and bridging short circuits due to the close distance between the passive components and the chip soldering interconnection area, the industry usually sets a solder resist bridge on the outer ink of the package substrate for blocking. However, due to the setting of the solder resist bridge, when the solder balls used to achieve chip interconnection are mechanically leveled, they will inevitably touch the solder resist bridge, and then the outer ink of the package substrate will be damaged by the solder resist bridge, and there is even a risk of breaking the inner circuit of the package substrate, causing problems with the reliability of the package substrate. Summary of the invention

[0004] The present application provides a method for manufacturing a packaging substrate, a packaging substrate and an electronic device to solve the problem that the manufacturing method of the packaging substrate in the prior art will damage the ink on the outer layer of the packaging substrate when mechanically leveling the solder pads used to achieve chip interconnection, and there is even a risk of breaking the inner layer circuit of the packaging substrate, thereby causing the problem of reliability of the packaging substrate.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing a packaging substrate, wherein the method for manufacturing the packaging substrate includes: providing a packaging core board, and opening a groove body exposing a conductive layer on one side of the packaging core board; forming a solder pad on the conductive layer in the groove body; wherein the thickness of the solder pad is less than the depth of the groove body; forming a solder resist bridge on one side of the packaging core board; forming solder balls on the solder pad so that the solder balls protrude from the side of the solder resist bridge away from the packaging core board; flattening the side of the solder ball away from the packaging core board until the distance between the solder ball and the side of the solder resist bridge away from the packaging core board is within a set threshold range; wherein the set threshold range is greater than 0.

[0006] Among them, the step of forming a solder pad on the conductive layer in the slot body includes: forming a conductive interconnection layer on one side of the packaging core board, the conductive layer and the slot wall of the slot body; setting a photosensitive anti-plating layer in the conductive interconnection layer corresponding to the area of ​​the packaging core board where the slot body is not opened; electroplating a solder pad on the conductive interconnection layer in the slot body; and removing the photosensitive anti-plating layer and part of the conductive interconnection layer on one side of the packaging core board.

[0007] Wherein, a solder mask layer is formed on one side of the encapsulation core board, on the conductive layer, and on the groove wall of the groove body; the solder mask layer is exposed and developed to obtain solder mask bridges.

[0008] Wherein, after the step of forming the solder mask bridges on the encapsulation core board, before the step of forming solder balls on the solder pads so that the solder balls protrude from the side of the solder mask bridges facing away from the encapsulation core board, it further includes: performing a surface leveling treatment on the solder pads.

[0009] Wherein, the solder balls are formed on the solder pads by stencil printing.

[0010] Wherein, the thickness of the solder pads is not less than the thickness of the solder mask bridges.

[0011] Wherein, the set threshold range is 2 - 5 microns.

[0012] To solve the above technical problems, another technical solution adopted by this application is: to provide an encapsulation substrate, wherein, the encapsulation substrate includes: an encapsulation core board, on one side of which there is a groove body exposing the conductive layer; solder pads, arranged on the conductive layer in the groove body; wherein, the thickness of the solder pads is less than the depth of the groove body; solder mask bridges, arranged on one side of the encapsulation core board; solder balls, arranged on the solder pads; wherein, the distance between the side of the solder balls facing away from the encapsulation core board and the side of the solder mask bridges facing away from the encapsulation core board is within the set threshold range, and the set threshold range is greater than 0.

[0013] Wherein, the thickness of the solder pads is not less than the thickness of the solder mask bridges and not less than 5 microns.

[0014] To solve the above technical problems, another technical solution adopted by this application is: to provide an electronic device, wherein, the electronic device includes a housing and an encapsulation substrate connected to each other; wherein, the encapsulation substrate is the encapsulation substrate described in any one of the above.

[0015] The beneficial effect of this application is: different from the prior art, the manufacturing method of the encapsulation substrate provided by this application forms a groove body exposing the conductive layer on one side of the encapsulation core board, forms solder pads on the conductive layer in the groove body, forms solder mask bridges on one side of the encapsulation core board, and then forms solder balls on the solder pads so that the solder balls protrude from the side of the solder mask bridges facing away from the encapsulation core board, and levels the side of the solder balls facing away from the encapsulation core board to make the distance between it and the side of the solder mask bridges facing away from the encapsulation core board within the set threshold range, thereby effectively using the solder pads arranged between the solder balls and the internal conductive layer of the encapsulation core board to lift the height of the solder balls, so that when leveling the solder balls, it can effectively avoid directly contacting the solder mask bridges, and further avoid transmitting stress to the outside of the encapsulation core board, so as to avoid damaging the outside of the encapsulation core board, and effectively reduce the risk of breaking the internal conductive layer of the encapsulation core board, thereby improving the reliability of the encapsulation substrate. Description of the Drawings

[0016] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for description in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0017] Figure 1a is a schematic flow chart of the first embodiment of the manufacturing method of the encapsulation substrate of the present application;

[0018] Figures 1b - 1f is Figure 1a a schematic structural diagram of an embodiment corresponding to S11 - S15 in

[0019] Figure 2a is Figure 1a a schematic flow chart of a specific embodiment corresponding to S12 in

[0020] Figures 2b - 2e is Figure 2a a schematic structural diagram of an embodiment corresponding to S121 - S124 in

[0021] Figure 3 is Figure 1a a schematic flow chart of an embodiment corresponding to S13 in

[0022] Figure 4 a schematic structural diagram of an embodiment of the encapsulation substrate of the present application;

[0023] Figure 5 a schematic structural diagram of an embodiment of the electronic device of the present application. Specific Embodiments

[0024] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the scope of protection of the present application.

[0025] The terms "first", "second", and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", and "third" may explicitly or implicitly include at least one of such features. In the description of this application, the meaning of "a plurality" is at least two, such as two, three, etc., unless otherwise specifically defined. In the embodiments of this application, all directional indications (such as up, down, left, right, front, back...) are only used to explain the relative positional relationship, movement conditions, etc. between components in a specific posture (as shown in the drawings). If the specific posture changes, then the directional indication also changes accordingly. In addition, the terms "comprise" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but optionally further includes steps or units not listed, or optionally further includes other steps or units inherent to these processes, methods, products, or devices.

[0026] Reference to "embodiment" herein means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of this application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0027] The following describes this application in detail with reference to the drawings and embodiments.

[0028] Please refer to Figures 1a - 1f , wherein, Figure 1a is a schematic flowchart of the first embodiment of the manufacturing method of the encapsulation substrate of this application, Figures 1b - 1f is Figure 1a a schematic structural diagram of an embodiment corresponding to S11 - S15 in

[0029] S11: Provide an encapsulation core board, and open a groove on one side of the encapsulation core board to expose the conductive layer.

[0030] Wherein, as Figure 1bAs shown, the encapsulated core board 20 may specifically include an inner core board 21 and a solder mask layer 22 disposed outside the inner core board 21; the inner core board 21 may specifically be a single-layer patterned copper clad laminate, or may include at least two layers of patterned copper clad laminates, and an insulating layer is laminated between each adjacent two of the at least two copper clad laminates, and connections are achieved through metal vias disposed in the insulating layer; and the inner core board 21 may specifically further include passive components, such as any reasonable circuit elements like capacitors, resistors, etc., and / or one or more of other any reasonable materials that can be used to manufacture circuit boards, such as copper plates, electroplated copper layers, conductive posts, heat dissipation plates, thermal conductive adhesives, etc., so as to be able to realize the pre-designed circuit logic through the patterned copper clad laminate, that is, the conductive circuit layer, and circuit units such as conductive posts and buried components. The present application does not make any limitations thereto.

[0031] Specifically, after obtaining the encapsulated core board 20, processes such as drilling and etching may specifically be used to open slots 221 on the solder mask layer 22 outside the encapsulated core board 20 until a partial area of the conductive layer (not shown in the figure), that is, the conductive circuit layer, used for connection with external circuit units in the inner core board 21 is exposed; or, when obtaining the inner core board 21, solder mask openings may specifically also be performed on the inner core board 21 through process flows such as ink coating, exposure, and development and curing, and the conductive layer to be welded with solder balls is exposed.

[0032] Optionally, the conductive layer may specifically be any reasonable material layer with conductive properties, such as a copper clad laminate, a copper plate, or an electroplated copper layer, etc., and the number of the conductive layer and the slots 221 may specifically be one or more, and when there are multiple ones, they are separated by an insulating layer to be used to realize the pre-designed circuit logic. The present application does not make any limitations thereto.

[0033] S12: Form solder pads on the conductive layer in the slots.

[0034] Further, as Figure 1c shown, solder pads 23 are manufactured on the conductive layers in each slot 221 of the encapsulated core board 20.

[0035] Optionally, the solder pads 23 may specifically be obtained by thickening the conductive layer exposed from each slot 221 through a copper deposition process or a nickel-palladium-gold thickening method; or, by successively performing process flows such as attaching a photosensitive anti-plating dry film, electroplating, etching, and removing the photosensitive anti-plating dry film on the encapsulated core board 20 provided with slots 221; or by depositing solder, conductive particles, or other any reasonable conductive materials on the conductive layer exposed in each slot 221. The present application does not make any limitations thereto.

[0036] It should be noted that the solder pads 23 refer to the tin pad planes provided in advance in the encapsulated core board 20 for setting solder balls 25.

[0037] Wherein, the thickness a of the solder pad 23 is less than the depth of the groove 221, that is, the solder pad 23 does not fill the groove 221, so as to facilitate the subsequent manufacture of solder balls 25.

[0038] S13: Form a solder mask bridge on one side of the encapsulated core board.

[0039] Furthermore, as Figure 1d shown, perform the solder mask process again on one side of the encapsulated core board 20 to manufacture a solder mask bridge 24.

[0040] It should be noted that the solder mask bridge 24 specifically refers to the outer layer ink of the encapsulated core board 20, that is, on the solder mask ink layer 22, a solder mask structure formed by secondary ink coating, used to isolate different welding functional areas.

[0041] The welding functional area refers to the area in the encapsulated core board 20 used for flip-chip welding and interconnection with the chip, and / or the area for interconnection with any reasonable circuit unit such as another encapsulated core board 20, and the present application does not limit this.

[0042] S14: Form solder balls on the solder pads so that the solder balls protrude from the side of the solder mask bridge facing away from the encapsulated core board.

[0043] Specifically, as Figure 1e shown, solder balls 25 are manufactured on each solder pad 23 by melting and depositing welding materials, or solder balls 25 are formed on the solder pads 23 by stencil printing, and each solder ball 25 protrudes from the side of the solder mask bridge 24 facing away from the encapsulated core board 20, that is, it is ensured that the maximum distance between the side of the solder ball 25 facing away from the encapsulated core board 20 and one side of the encapsulated core board 20 is greater than the maximum distance between the side of the solder mask bridge 24 facing away from the encapsulated core board 20 and one side of the encapsulated core board 20, so that the solder balls 25 exceed the height of the solder mask bridge 24.

[0044] Optionally, the thickness a of the solder pad 23 is not less than the thickness of the solder mask bridge 24, so as to effectively ensure the height of the solder balls 25 exceeding the solder mask bridge 24 when forming solder balls 25 on the solder pad 23.

[0045] Optionally, the thickness a of the solder pad 23 is greater than 5 microns to ensure that the solder balls 25 can exceed the height of the solder mask bridge 24, and the present application does not limit this.

[0046] S15: Level the side of the solder ball facing away from the encapsulated core board to the distance between the side of the solder mask bridge facing away from the encapsulated core board within a set threshold range.

[0047] Furthermore, as Figure 1fAs shown, the side of the solder ball 25 facing away from the package core board 20 is leveled so that the distance b between the side of the leveled solder ball 25 facing away from the package core board 20 and the side of the solder resist bridge 24 facing away from the package core board 20 is within a set threshold range.

[0048] The set threshold range is greater than 0, that is, the side of the flattened solder ball 25 facing away from the package core board 20 is slightly higher than the side of the solder resist bridge 24 facing away from the package core board 20 .

[0049] Optionally, the threshold value is set in a range of 2-5 micrometers to avoid direct contact with the solder resist bridge 24 when the solder ball 25 is leveled as much as possible, which is not limited in the present application.

[0050] The above scheme sets a solder pad 23 between the solder ball 25 and the internal conductive layer of the packaging core board 20 to raise the height of the solder ball 25, so that when the solder ball 25 is leveled, it can effectively avoid direct contact with the solder resist bridge 24, thereby avoiding the stress from being transferred to the outside of the packaging core board 20, so as to avoid damage to the outside of the packaging core board 20, and effectively reduce the risk of breaking the internal conductive layer of the packaging core board 20, thereby improving the reliability of the packaging substrate.

[0051] Furthermore, in one embodiment, after the above S13 and before S14 , the following step may be specifically included: performing surface planarization treatment on the solder pad 23 .

[0052] It is understandable that by performing surface planarization on the solder pad 23 , when the solder ball 25 is leveled, the stress effect of the solder ball 25 on the solder pad 23 and the outer side of the package core board 20 can be effectively reduced.

[0053] Furthermore, in one embodiment, in the above S14, the step may further include: forming solder balls 25 on the solder pads 23 by screen printing.

[0054] See also Figures 2a - 2e ,in, Figure 2a yes Figure 1a A schematic flow chart of a specific embodiment corresponding to S12, Figures 2b - 2e yes Figure 2a In one embodiment, the above S12 may further include the following steps:

[0055] S121: forming a conductive interconnection layer on one side of the package core board, the conductive layer and the groove wall of the groove body.

[0056] Specifically, Figure 2bAs shown, a conduction and interconnection layer 26 is fabricated on one side of the packaging core board 20, the conductive layer, and the inner wall of the groove 221 through electroless copper plating or sputtering, that is, the area of the packaging core board 20 where the solder pads 23 need to be fabricated is exposed, and other areas are protected by light exposure of the dry film.

[0057] S122: A photosensitive anti-plating layer is provided on the area of the conduction and interconnection layer corresponding to the region of the packaging core board where no groove is opened.

[0058] Further, as Figure 2c shown, a photosensitive anti-plating dry film is attached to the area of the conduction and interconnection layer 26 corresponding to the region of the packaging core board 20 where no groove 221 is opened to form a photosensitive anti-plating layer 27.

[0059] S123: A solder pad is electroplated on the conduction and interconnection layer in the groove.

[0060] Specifically, as Figure 2d shown, pattern electroplating is performed on the conduction and interconnection layer 26 to electroplate and thicken the conduction and interconnection layer 26 in the groove 221 of the packaging core board 20 to obtain an electroplated copper layer 28 to form the solder pad 23.

[0061] It can be understood that the solder pad 23 fabricated by electroplating has lower cost and better flatness compared with the nickel-palladium-gold thickening method.

[0062] S124: The photosensitive anti-plating layer and a part of the conduction and interconnection layer on one side of the packaging core board are removed.

[0063] Further, as Figure 2e shown, pattern stripping and etching are performed on the conduction and interconnection layer 26 to remove the photosensitive anti-plating layer 27 and a part of the conduction and interconnection layer 26 on one side of the packaging core board 20.

[0064] It can be understood that the solder pad 23 obtained by the above process specifically includes the electroplated copper layer 28 and a part of the conduction and interconnection layer 26 that is not removed.

[0065] Please refer to Figure 3 , Figure 3 is Figure 1a a schematic flow chart of an embodiment corresponding to S13 in

[0066] S131: A solder resist layer is formed on one side of the packaging core board, the conductive layer, and the inner wall of the groove.

[0067] Specifically, a secondary solder resist process is performed on the outside of the packaging core board 20 provided with the groove 221 to form a solder resist layer (not shown in the figure) on one side of the packaging core board 20, the conductive layer, and the inner wall of the groove 221.

[0068] S132: Expose and develop the solder mask layer to obtain solder mask bridges.

[0069] Further, expose and develop the solder mask layer in sequence to obtain solder mask bridges 24.

[0070] In addition, the present application also provides a packaging substrate. Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of an embodiment of the packaging substrate of the present application. In this embodiment, the packaging substrate 30 includes: a packaging core board 31, a solder pad 32, a solder mask bridge 33, and solder balls 34.

[0071] Specifically, the packaging core board 31 may specifically include an inner core board 311 and a solder mask ink layer 312 disposed outside the inner core board 311; the inner core board 311 may specifically be a single-layer patterned copper clad laminate, or may include at least two layers of patterned copper clad laminates, and an insulating layer is laminated between every two adjacent copper clad laminates of the at least two copper clad laminates, and connections are achieved through metal vias disposed in the insulating layer; and the inner core board 311 may specifically further include passive components, such as any reasonable circuit elements like capacitors, resistors, etc., and / or one or more of other any reasonable materials that can be used for manufacturing circuit boards, such as copper plates, electroplated copper layers, conductive posts, heat dissipation plates, thermal conductive adhesives, etc., so as to be able to realize the pre-designed circuit logic through the patterned copper clad laminate, that is, the conductive circuit layer, and circuit units such as conductive posts and buried components. The present application does not make any limitations in this regard.

[0072] Wherein, one or more slots 221 are further formed on one side surface of the packaging core board 31, and each slot 221 also exposes the conductive layer in the inner core board 311.

[0073] A solder mask bridge 33 is further disposed on one side surface of the packaging core board 31. The solder mask bridge 33 specifically refers to a solder mask structure formed by secondary coating of ink on the outer ink of the packaging core board 31, that is, the solder mask ink layer 312, for isolating different welding functional areas.

[0074] And solder balls 34 are further disposed on the solder pads 32. The distance b between the side surface of the solder balls 34 facing away from the packaging core board 31 and the side surface of the solder mask bridge 33 facing away from the packaging core board 31 is within a set threshold range.

[0075] Wherein, the set threshold range is greater than 0, that is, the side surface of the solder balls 34 facing away from the packaging core board 31 after leveling is slightly higher than the side surface of the solder mask bridge 33 facing away from the packaging core board 31.

[0076] Optionally, the thickness a of the solder pad 32 is not less than the thickness of the solder mask bridge 33, so as to effectively ensure the height of the solder balls 34 exceeding the solder mask bridge 33 when forming the solder balls 34 on the solder pads 32.

[0077] Optionally, the thickness a of the solder pad 32 is greater than 5 micrometers to ensure that the solder ball 34 exceeds the height of the solder resist bridge 33 , which is not limited in the present application.

[0078] Optionally, the threshold value is set in a range of 2-5 micrometers to avoid direct contact with the solder resist bridge 33 when the solder ball 34 is leveled as much as possible, which is not limited in the present application.

[0079] The above scheme sets a solder pad 32 between the solder ball 34 and the internal conductive layer of the packaging core board 31 to raise the height of the solder ball 34, so that when the solder ball 34 is leveled, it can effectively avoid direct contact with the solder resist bridge 33, thereby avoiding the stress from being transferred to the outside of the packaging core board 31, so as to avoid damage to the outside of the packaging core board 31, and effectively reduce the risk of breaking the internal conductive layer of the packaging core board 31, thereby improving the reliability of the packaging substrate 30.

[0080] This application also provides an electronic device, see Figure 5 , Figure 5 1 is a schematic diagram of the structure of an electronic device of the present application. In this embodiment, the electronic device 40 includes a housing 41 and a packaging substrate 42 connected to each other.

[0081] It should be noted that the packaging substrate 42 described in this embodiment is the packaging substrate 30 as described in any of the above items. Figure 4 And the related text content will not be repeated here.

[0082] The beneficial effect of the present application is as follows: different from the prior art, the manufacturing method of the packaging substrate provided by the present application forms a solder pad on the conductive layer in the groove by opening a groove body exposing the conductive layer on one side of the packaging core board, and forms a solder resist bridge on one side of the packaging core board, and then forms a solder ball on the solder pad, so that the solder ball protrudes from the side of the packaging core board that is away from the solder resist bridge, and the side of the solder ball away from the packaging core board is flattened until the distance between the side of the solder ball away from the side of the solder resist bridge away from the packaging core board is within a set threshold range, thereby effectively utilizing the solder pad arranged between the solder ball and the conductive layer inside the packaging core board to raise the height of the solder ball, so that when the solder ball is flattened, it can effectively avoid direct contact with the solder resist bridge, thereby avoiding stress from being transferred to the outside of the packaging core board, thereby avoiding damage to the outside of the packaging core board, and effectively reducing the risk of breaking the conductive layer inside the packaging core board, thereby improving the reliability of the packaging substrate.

[0083] The above are only implementation methods of the present application, and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A manufacturing method of a packaging substrate, characterized in that, The manufacturing method of the encapsulation substrate includes: Providing an encapsulation core board, and forming a groove exposing a conductive layer on one side of the encapsulation core board; Forming a solder pad on the conductive layer in the groove; wherein, the thickness of the solder pad is less than the depth of the groove; Forming a solder mask bridge on one side of the encapsulation core board; Forming solder balls on the solder pad so that the solder balls protrude from the side of the solder mask bridge facing away from the encapsulation core board; Flattening the side of the solder ball facing away from the encapsulation core board to a distance within a set threshold range from the side of the solder mask bridge facing away from the encapsulation core board; wherein, the set threshold range is greater than 0.

2. The manufacturing method of the encapsulation substrate according to claim 1, wherein The step of forming a solder pad on the conductive layer in the groove includes: Forming a conduction interconnection layer on one side of the encapsulation core board, the conductive layer, and the groove wall of the groove; Providing a photosensitive resist coating on the area of the conduction interconnection layer corresponding to the area of the encapsulation core board where the groove is not formed; Electroplating to form the solder pad on the conduction interconnection layer in the groove; Removing the photosensitive resist coating and a part of the conduction interconnection layer on one side of the encapsulation core board.

3. The manufacturing method of the encapsulation substrate according to claim 1, wherein, The step of forming a solder mask bridge on one side of the encapsulation core board includes: Forming a solder mask layer on one side of the encapsulation core board, the conductive layer, and the groove wall of the groove; Exposing and developing the solder mask layer to obtain the solder mask bridge.

4. The manufacturing method of the encapsulation substrate according to claim 1, characterized in that, After the step of forming a solder mask bridge on the encapsulation core board and before the step of forming solder balls on the solder pad so that the solder balls protrude from the side of the solder mask bridge facing away from the encapsulation core board, it further includes: Performing a surface leveling treatment on the solder pad.

5. The manufacturing method of the packaging substrate according to claim 1, characterized in that, The step of forming solder balls on the solder pad includes: Forming the solder balls on the solder pad by stencil printing.

6. The manufacturing method of the encapsulation substrate according to any one of claims 1-5, characterized in that The thickness of the solder pad is not less than the thickness of the solder mask bridge.

7. The manufacturing method of the encapsulation substrate according to any one of claims 1-5, characterized in that The set threshold range is 2-5 microns.

8. An encapsulation substrate, characterized in that, The encapsulation substrate includes: An encapsulation core board, on one side of which a groove exposing a conductive layer is formed; A solder pad, provided on the conductive layer in the groove; wherein, the thickness of the solder pad is less than the depth of the groove; A solder mask bridge, provided on one side of the encapsulation core board; Solder balls, provided on the solder pad; wherein, the distance between the side of the solder ball facing away from the encapsulation core board and the side of the solder mask bridge facing away from the encapsulation core board is within a set threshold range, and the set threshold range is greater than 0.

9. The encapsulation substrate according to claim 8, characterized in that The thickness of the solder pad is not less than the thickness of the solder mask bridge and not less than 5 microns.

10. An electronic device, characterized in that, The electronic device includes a housing and an encapsulation substrate connected to each other; Wherein, the encapsulation substrate is the encapsulation substrate according to any one of claims 7-9.

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