Wafer-level silicon carbide device manufacturing method and silicon carbide device

Abstract

The invention relates to a wafer-level silicon carbide device manufacturing method and a silicon carbide device. The method comprises the steps of providing a silicon carbide wafer; providing a substrate and manufacturing a groove; depositing a diffusion barrier layer on the surface of the substrate, and manufacturing a first copper layer on the surface of the diffusion barrier layer; bonding the silicon carbide wafer into the groove through a sintering process; sequentially depositing a diffusion isolation layer, a first silicon dioxide layer and a silicon thin film layer on the substrate; manufacturing a first metal connecting layer; manufacturing a second copper layer; a plurality of conduction grooves are etched in the third silicon dioxide layer, second through holes extending to the second copper layer are etched in the bottom walls of the conduction grooves, and second metal connecting layers filled into the second through holes and source conduction layers, drain conduction layers and grid conduction layers filled into the conduction grooves are manufactured. According to the invention, the problems of device failure and heat dissipation surface layering caused by high and low junction temperature circulation in the use process due to mismatching of material characteristics are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for fabricating a wafer-level silicon carbide device and a silicon carbide device. Background Art

[0002] In recent years, with the continuous growth of the demand for high-voltage and high-current systems, the third-generation semiconductor technology represented by silicon carbide has developed rapidly. Such semiconductor devices have high power density and heat flux density, and while meeting high-performance applications, they pose higher requirements for heat dissipation and device reliability. However, the traditional device manufacturing processes and heat dissipation structures have become difficult to cope with this development trend, becoming the key bottleneck restricting the further improvement of device performance and reliability.

[0003] The current existing technologies mainly focus on the optimization and improvement of traditional processes. Some technologies adopt double-sided heat dissipation technology in the heat dissipation structure, but due to the complex structure design, the overall manufacturing cost remains high, making it difficult to achieve large-scale economic applications; in addition, another part of the technologies optimize at the chip level and adopt wafer-level processes, but these technologies are mostly used in low-current and low-voltage scenarios and cannot meet the heat dissipation requirements of the third-generation semiconductors under high power density and high heat flux density. Summary of the Invention

[0004] Therefore, the present invention provides a method for fabricating a wafer-level silicon carbide device and a silicon carbide device, which solves the problems of device failure and heat dissipation surface delamination caused by high and low cycling of the junction temperature during the use of traditional third-generation semiconductor devices due to material property mismatch during the manufacturing process.

[0005] To solve the above technical problems, the present invention provides a method for fabricating a wafer-level silicon carbide device, including: Providing a silicon carbide wafer; Providing a substrate, and fabricating a groove on the surface of the substrate that matches the size of the silicon carbide wafer; Depositing a diffusion barrier layer on the surface of the substrate, and fabricating a first copper layer on the surface of the diffusion barrier layer; Bonding the silicon carbide wafer into the groove through a sintering process; Sequentially depositing a diffusion isolation layer, a first silicon dioxide layer, and a silicon thin film layer on the substrate; Etching a plurality of first through-holes on the silicon thin film layer, the first through-holes extending to the first through-holes of the first copper layer and / or the silicon carbide wafer, depositing a first tantalum nitride layer on the inner wall of the first through-holes and then filling with copper metal to form a first metal connection layer; Fabricating a second copper layer connected to the first metal connection layer on the surface of the silicon thin film layer, and patterning it, and then depositing a second silicon dioxide layer on the silicon thin film layer; Deposit a silicon nitride layer and a third silicon dioxide layer on the second silicon dioxide layer in sequence; Etch a plurality of conduction grooves on the third silicon dioxide layer, etch a second through hole extending to the second copper layer on the bottom wall of the conduction groove, deposit a second tantalum nitride layer on the inner walls of the conduction groove and the second through hole, and then fill with copper metal to form a second metal connection layer filled in the second through hole and a source conduction layer, a drain conduction layer, and a gate conduction layer filled in the conduction groove.

[0006] In an embodiment of the present invention, fabricating a first copper layer on the surface of the diffusion barrier layer includes: Deposit a first copper substrate layer on the surface of the diffusion barrier layer by plasma physical vapor deposition; On the basis of the first copper substrate, form a first copper layer through electroplating and annealing processes, and etch away the redundant first copper layer regions according to the required pattern regions.

[0007] In an embodiment of the present invention, the thickness of the first copper layer is 5 - 40 microns.

[0008] In an embodiment of the present invention, bonding the silicon carbide wafer into the groove by a sintering process includes: Adopt a pressure sintering method, with a sintering temperature of 150 - 250 °C, a sintering pressure of 3 - 30 MPa, and a sintering time of 30 - 240 seconds.

[0009] In an embodiment of the present invention, the material of the substrate includes silicon, insulating silicon carbide, or sapphire.

[0010] In an embodiment of the present invention, the thickness of the second copper layer is 1 - 50 microns.

[0011] In an embodiment of the present invention, the diffusion isolation layer includes silicon nitride, silicon oxynitride, tantalum oxide, or polyimide.

[0012] In an embodiment of the present invention, before bonding the silicon carbide wafer into the groove by a sintering process, it further includes: Deposit a metal layer in the groove by PVD or thin film deposition process.

[0013] In an embodiment of the present invention, the material of the metal layer is silver, and the thickness is greater than 4.5 KA.

[0014] The present invention also provides a wafer-level silicon carbide device, which is fabricated by the wafer-level silicon carbide device manufacturing method.

[0015] The above technical solutions of the present invention have the following advantages compared with the prior art: The wafer-level silicon carbide device manufacturing method and silicon carbide device described in the present invention address the chip heat dissipation problem and propose to use a silicon substrate with a groove structure or other similar substrate materials with high thermal conductivity and low dielectric loss to replace additional heat dissipation materials such as traditional ceramic sheets, thereby achieving direct heat transfer between the chip and the heat dissipation system and improving heat dissipation efficiency.

[0016] The present invention aims at the isolation and insulation problems of the chip by setting an insulating filling material, which includes but is not limited to silicon dioxide, silicon nitride, silicon dioxide nitrogen and tantalum pentoxide. The thermal expansion coefficient of the selected insulating material is similar to that of the chip, which effectively solves the problems of chip cracking and breakage caused by the mismatch of thermal expansion coefficients of traditional epoxy resin or silicone filling materials; at the same time, the use of insulating materials with high thermal conductivity can construct a full-scale heat dissipation channel for the chip, further improving the overall heat dissipation performance.

[0017] The present invention aims at solving the problem of uneven current density distribution. In the redistribution layer, the present invention designs corresponding bonding areas according to current densities of different electrodes to optimize current distribution.

[0018] In order to solve the problem of chip load balancing, the present invention designs multiple grooves for chip placement in a specific functional area of ​​the silicon substrate, and uses a three-dimensional rewiring process to realize the interconnection between the chips, thereby achieving the purpose of auxiliary balance within the module and improving the overall operating efficiency.

[0019] Through the above technical scheme, the present invention can not only solve the heat dissipation and reliability problems of traditional devices under high power density and high heat flux density conditions, but also realize the efficient interconnection of multiple chips in the same power module by optimizing the current distribution and load balancing design, and solve the problems of load balance, operating efficiency and other issues in the interconnection of power modules composed of the third-generation semiconductor integrated heat dissipation represented by silicon carbide and its components. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0021] Figure 1 It is a schematic diagram of the structure of the wafer-level silicon carbide device of the present invention.

[0022] Figure 2 It is a schematic diagram of the structure of a silicon carbide wafer.

[0023] Figure 3 It is a schematic diagram of forming the first copper layer.

[0024] Figure 4 is a schematic diagram of bonding a silicon carbide wafer into the groove.

[0025] Figure 5 It is a schematic diagram of a deposition diffusion isolation layer, a first silicon dioxide layer, and a silicon thin film layer.

[0026] Figure 6 It is a schematic diagram of fabricating and forming a first metal connection layer.

[0027] Figure 7 It is a schematic diagram of fabricating and forming a second copper layer.

[0028] Explanation of the reference numerals in the drawings of the specification: 1. Substrate; 11. Groove; 12. Metal layer; 2. Diffusion barrier layer; 3. First copper layer; 4. Silicon carbide wafer; 51. Diffusion isolation layer; 52. First silicon dioxide layer; 53. Silicon thin film layer; 54. Second silicon dioxide layer; 55. Silicon nitride layer; 56. Third silicon dioxide layer; 6. First metal connection layer; 61. First tantalum nitride layer; 7. Second copper layer; 8. Second metal connection layer; 81. Second tantalum nitride layer; 91. Source conduction layer; 92. Drain conduction layer; 93. Gate conduction layer; 10. Passivation protection layer. Detailed implementation manners

[0029] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, so that those skilled in the art can better understand the present invention and be able to implement it, but the specific embodiments cited are not intended to limit the present invention.

[0030] In the present invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of the present invention, rather than indicating or implying that the technical features referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation to the present invention.

[0031] In the present invention, the meaning of "several" is one or more, the meaning of "multiple" is two or more, "greater than", "less than", "exceeding", etc. are understood not to include the present number; "above", "below", "within", etc. are understood to include the present number. In the description of the present invention, if "first" and "second" are described, they are only for the purpose of distinguishing technical features and should not be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0032] In the present invention, unless otherwise clearly defined, terms such as "arrange", "install", and "connect" shall be understood in a broad sense. For example, they can be directly connected, or indirectly connected through an intermediate medium; they can be fixedly connected, or detachably connected, or integrally formed; they can be mechanically connected, or electrically connected or capable of communicating with each other; they can be the communication inside two components or the interaction relationship between two components. Those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0033] Referring to Figure 1 As shown, a method for fabricating a wafer-level silicon carbide device includes: S1. Provide a silicon carbide wafer 4. Referring to Figure 2 As shown.

[0034] Specifically, through a series of process steps (including substrate 1 processing, epitaxial growth, cleaning, masking, lithography, etching, deposition, ion implantation, etc.), a silicon carbide wafer 4 that meets the design requirements is prepared. And materials such as polyimide are covered on specific areas of the surface to protect the chip from damage in subsequent processes. Finally, the wafer can be divided into individual silicon carbide chips by mechanical cutting or laser cutting.

[0035] S2. Provide a substrate 1, and make a groove 11 on the surface of the substrate 1 that matches the size of the silicon carbide wafer 4.

[0036] Specifically, a groove 11 that meets the size of the silicon carbide chip is made on the surface of the substrate 1 by chemical or plasma methods. The depth of the groove 11 needs to meet the requirements of the subsequent bonding process of the silicon carbide chip to ensure tight bonding and optimize the heat dissipation performance.

[0037] The material of the substrate 1 is preferably a material with high thermal conductivity and low dielectric loss as the substrate 1 material, such as silicon (Si), insulating silicon carbide (SiC), sapphire, etc.

[0038] It can be understood that the silicon carbide wafer 4 is directly placed in the groove 11 of the substrate 1 to achieve a larger area of fitting, which is beneficial to the construction of the heat dissipation channel. The high-thermal-conductivity substrate 1 can ensure the rapid conduction of the heat of the chip in subsequent work and reduce the operating temperature of the device.

[0039] In addition, in order to effectively connect the substrate 1 material to an external radiator, a layer of metal material needs to be deposited on the back of the substrate 1 by PVD or thin film deposition process. In order to improve the connection strength between the metal material and the substrate 1, roughening treatment can be performed on the back of the substrate 1, or roughening can be performed on the surface of the metal material to improve the connection strength between the substrate 1 and the external radiator.

[0040] S3. Deposit a diffusion barrier layer 2 on the surface of the substrate 1, and fabricate a first copper layer 3 on the surface of the diffusion barrier layer 2. Refer to Figure 3 as shown.

[0041] Specifically, first deposit the diffusion barrier layer 2 (such as silicon nitride) on the surface of the substrate 1, with a preferred thickness of 5 microns. Then, generate a thin copper substrate on it by physical vapor deposition (PVD) plasma, and thicken it by electroplating process (such as copper sulfate) to form the first copper layer 3, whose thickness should exceed 1 micron, preferably 5 - 40 microns. After annealing in a nitrogen environment at about 200 °C for 30 minutes, etch away the excess copper area according to the designed pattern.

[0042] It should be noted that the diffusion barrier layer 2 can prevent copper ions from diffusing into the substrate 1 at high temperatures, avoiding device failure caused by metal contamination. First form a thin seed layer by PVD or sputtering, and then the electroplating method can precisely control the thickness of the copper layer, taking into account both conductivity and cost. Annealing in a nitrogen environment at about 200 °C can reduce stress and improve the interfacial bonding between copper and the diffusion barrier layer 2.

[0043] S4. Bond the silicon carbide wafer 4 into the groove 11 through a sintering process. Refer to Figure 4 as shown.

[0044] Specifically, bond the divided silicon carbide wafer 4 (chip) into the groove 11 of the silicon substrate 1 through a sintering process. The chip includes a top electrode bonding area and a bottom metal layer 12, and is bonded to the substrate 1 by sintering or adhesion. A pressure-assisted or non-pressure-assisted sintering method can be selected. Preferably, a pressure sintering method is adopted to improve thermal conductivity and high reliability. Preferably, the sintering temperature is 150 - 250 °C, the sintering pressure is 3 - 30 MPa, and the sintering time is 30 - 240 seconds. Completing chip bonding at 150 - 250 °C and 3 - 30 MPa can avoid damage to the chip structure caused by excessive thermal stress, and improve the interfacial bonding strength and heat conduction efficiency.

[0045] In one embodiment, before bonding the silicon carbide wafer 4 into the groove 11 through a sintering process, it further includes: Deposit a metal layer 12 in the groove 11 by PVD or thin film deposition process to enhance the bonding strength and reliability between the chip and the substrate 1; preferably, the material of the metal layer 12 is silver, and the thickness is greater than 4.5 KA. When using a silver layer as a filler, silver is relatively compatible with the surface energy of silicon carbide, and at the same time, silver has plasticity and high thermal conductivity.

[0046] S5. Sequentially deposit a diffusion isolation layer 51, a first silicon dioxide layer 52, and a silicon thin film layer 53 on the substrate 1. Refer to Figure 5 as shown.

[0047] Specifically, in a high-temperature environment, a silicon nitride thin film is deposited on the substrate 1 by means of thin film deposition process to serve as the diffusion isolation layer 51; then the first silicon dioxide layer 52 is deposited and planarized by CMP; finally, a silicon thin film is deposited. The diffusion isolation layer 51 includes silicon nitride, silicon oxynitride, tantalum oxide or polyimide.

[0048] The isolation layer, the first silicon dioxide layer 52 and the silicon thin film layer 53 are made of materials that are the same as or similar in performance to the substrate 1, reducing the delamination and cracking problems caused by inconsistent thermal expansion coefficients of different materials.

[0049] First deposit the diffusion isolation layer 51 and then deposit the SiO2 layer to form a composite structure, which can effectively prevent external ions / metals from interfering with the device functional area. Chemical mechanical polishing (CMP) can significantly reduce the surface roughness, providing a good flat base for subsequent lithography, etching and metal interconnection. Depositing a silicon thin film on the top layer can serve as the underlying layer for subsequent via etching.

[0050] S6. Etch a plurality of first vias on the silicon thin film layer 53, the first vias extending to the first vias of the first copper layer 3 and / or the silicon carbide wafer 4. After depositing a first tantalum nitride layer 61 on the inner walls of the first vias, copper metal is filled to form the first metal connection layer 6; realizing electrical interconnection with the underlying first copper layer 3 or silicon carbide wafer 4. Refer to Figure 6 shown.

[0051] S7. Fabricate a second copper layer 7 connected to the first metal connection layer 6 on the surface of the silicon thin film layer 53, and pattern it. Then deposit a second silicon dioxide layer 54 on the silicon thin film layer 53. Refer to Figure 7 shown.

[0052] Specifically, the thickness of the second copper layer 7 is between 1 and 50 microns. The manufacturing process of the second copper layer 7 is similar to that of the first copper layer 3.

[0053] S8. Deposit a silicon nitride layer 55 and a third silicon dioxide layer 56 on the second silicon dioxide layer 54 in sequence.

[0054] S9. Etch a plurality of conduction grooves on the third silicon dioxide layer 56, etch second vias extending to the second copper layer 7 on the bottom walls of the conduction grooves. After depositing a second tantalum nitride layer 81 on the inner walls of the conduction grooves and the second vias, copper metal is filled to form a second metal connection layer 8 filled in the second vias and source conduction layers 91, drain conduction layers 92 and gate conduction layers 93 filled in the conduction grooves. Then fabricate a passivation protection layer on the top of the device. Refer to Figure 1 shown.

[0055] Through the above method, by directly bonding the chip to substrates 1 such as silicon and silicon carbide, and realizing wafer-level packaging by means of metal interconnection technology, without traditional plastic packaging materials, the connection of external circuits is thus simplified; by adopting the chip-level interconnection method, the overall thermal conductivity of the chip can be greatly improved and the junction temperature can be reduced, providing a higher operating temperature range for the device; this method also effectively avoids the problems of chip cracking and breakage caused by the mismatch of the thermal expansion coefficients of traditional epoxy resin or silica gel fillers. In addition, by replacing the traditional ceramic substrate with materials such as silicon or silicon carbide as the heat conduction layer, the heat dissipation performance can be further enhanced, and the defects such as uneven heat dissipation and vulnerability caused by the easy generation of voids and delamination in the ceramic substrate can be solved.

[0056] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the technical solutions of the present invention, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A method for fabricating a wafer-level silicon carbide device, characterized in that, Including: Providing a silicon carbide wafer (4); Providing a substrate (1), and making a groove (11) on the surface of the substrate (1) that matches the size of the silicon carbide wafer (4); Depositing a diffusion barrier layer (2) on the surface of the substrate (1), and making a first copper layer (3) on the surface of the diffusion barrier layer (2); Bonding the silicon carbide wafer (4) into the groove (11) through a sintering process; Sequentially depositing a diffusion isolation layer (51), a first silicon dioxide layer (52), and a silicon thin film layer (53) on the substrate (1); Etching a plurality of first through holes in the silicon thin film layer (53), the first through holes extending to the first through holes of the first copper layer (3) and / or the silicon carbide wafer (4), depositing a first tantalum nitride layer (61) on the inner wall of the first through holes and then filling with copper metal to form a first metal connection layer (6); Making a second copper layer (7) connected to the first metal connection layer (6) on the surface of the silicon thin film layer (53), and patterning it, and then depositing a second silicon dioxide layer (54) on the silicon thin film layer (53); Sequentially depositing a silicon nitride layer (55) and a third silicon dioxide layer (56) on the second silicon dioxide layer (54); Etching a plurality of conduction grooves in the third silicon dioxide layer (56), etching a second through hole extending to the second copper layer (7) on the bottom wall of the conduction groove, depositing a second tantalum nitride layer (81) on the inner walls of the conduction groove and the second through hole and then filling with copper metal to form a second metal connection layer (8) filled into the second through hole and a source conduction layer (91), a drain conduction layer (92), and a gate conduction layer (93) filled into the conduction groove; 2. The manufacturing method of a wafer-level silicon carbide device according to claim 1, characterized in that Making a first copper layer (3) on the surface of the diffusion barrier layer (2) includes: Depositing a first copper substrate layer on the surface of the diffusion barrier layer (2) by plasma physical vapor deposition; On the basis of the first copper substrate, forming a first copper layer (3) through electroplating and annealing processes, and etching away the redundant first copper layer (3) region according to the required pattern region.

3. The manufacturing method of a wafer-level silicon carbide device according to claim 1, characterized in that The thickness of the first copper layer (3) is 5 to 40 microns.

4. A method for fabricating a wafer-level silicon carbide device according to claim 1, characterized in that, Bonding the silicon carbide wafer (4) into the groove (11) through a sintering process includes: Adopting a pressure sintering method, with a sintering temperature of 150 to 250 °C, a sintering pressure of 3 to 30 MPa, and a sintering time of 30 to 240 seconds.

5. A method for fabricating a wafer-level silicon carbide device according to claim 1, characterized in that, The material of the substrate (1) includes silicon, insulating silicon carbide, or sapphire.

6. The manufacturing method of a wafer-level silicon carbide device according to claim 1, characterized in that The thickness of the second copper layer (7) is 1 to 50 microns.

7. A method for fabricating a wafer-level silicon carbide device according to claim 1, wherein, The diffusion isolation layer (51) includes silicon nitride, silicon oxynitride, tantalum oxide, or polyimide.

8. The manufacturing method of a wafer-level silicon carbide device according to claim 1, characterized in that, Before bonding the silicon carbide wafer (4) into the groove (11) through a sintering process, it further includes: Depositing a metal layer (12) in the groove (11) by PVD or thin film deposition process.

9. A method for fabricating a wafer-level silicon carbide device according to claim 8, wherein The material of the metal layer (12) is silver, and the thickness is greater than 4.5 KA.

10. A silicon carbide device for a wafer-level silicon carbide device, characterized in that, Manufactured by the method for manufacturing a wafer-level silicon carbide device according to any one of claims 1-9.

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