Electric drive inverter with simplified architecture based on DSP (Digital Signal Processor) chip

Abstract

The invention discloses a DSP chip-based electric drive inverter with a simplified architecture, which comprises a basic function control module and a function checking module, and is characterized in that the basic function control module comprises a power supply chip SBC, a chip DSP1 and a level conversion circuit, and the function checking module comprises a power supply chip LDO1, a power supply chip LDO2 and a chip DSP2. According to the electric drive inverter of the simplified architecture based on the DSP chip, a high-reliability electric drive controller scheme is designed through the DSP, system scheme optimization, cost optimization and low-cost optimization architecture can be achieved on the premise that the system reliability is guaranteed to the maximum extent, and the competitiveness of the whole vehicle can be improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of electric drive inverters, and particularly relates to an electric drive inverter with a simplified architecture based on a DSP chip. Background Art

[0002] For the main arithmetic unit of the electric drive inverter of new energy vehicles, generally, MCU products such as Infineon and NXP are used as the main control chips, or a DSP is used to make an electric drive controller solution with a minimalist architecture.

[0003] The current solutions have the following obvious drawbacks:

[0004] 1) The structures of MCU products such as Infineon and NXP are complex in themselves, and complex peripheral hardware circuit design and software cooperation are required to achieve high diagnostic coverage. The overall system cost is too high and does not have a competitive advantage.

[0005] 2) The traditional DSP solution architecture is too simple. In the states where the external 12V battery has abnormal power supply, the system power SBC chip has an abnormality, or the main arithmetic unit DSP chip has an abnormal operation, etc., it is impossible to effectively control the system to enter a safe state or can only enter a specific preset state; the system flexibility and robustness are both poor, and the high-reliability goal cannot be achieved.

[0006] 3) Directly adding a DSP and its SBC power supply will greatly increase the system chip cost, which is not conducive to improving the product cost performance.

[0007] As the requirements for the reliability of the whole vehicle are getting higher and higher, for MCU products of brands such as Infineon and NXP, although the chips themselves have passed the functional safety Asil-D certification, their prices are not competitive; moreover, they are at a significant disadvantage in the increasingly fierce new energy vehicle inverter parts market. The DSP product with a minimalist architecture electric drive controller solution is difficult to ensure the safety requirements of the electric drive inverter system. When a single DSP or its power supply has a problem, it is difficult to effectively control the system to execute the functional safety state. Although multiple sets of redundant circuits improve the system functional safety level, they will simultaneously increase the system chip material cost significantly.

[0008] Therefore, in view of the above problems, further improvements are made. Summary of the Invention

[0009] The main purpose of the present invention is to provide an electric drive inverter with a simplified architecture based on a DSP chip. By using the DSP to design a high-reliability electric drive controller solution, it is possible to optimize the system solution and cost under the premise of ensuring the system reliability to the greatest extent. The low-cost optimized architecture is conducive to increasing the competitiveness of the whole vehicle.

[0010] Another object of the present invention is to provide an electric drive inverter with a simplified architecture based on a DSP chip. The DSP1, the power supply SBC chip, and the output control loop level conversion circuit are designed as the main operation loop, and the DSP2, the power supply LDO1 chip, and the LDO2 chip are designed as the function verification part. The operation state of the DSP1 software can be verified through the SBC; the CPU and software operation of the DSP1 are verified for the second time through the DSP2, and the correctness of the operation data of the DSP1 is verified simultaneously; thus, the function state of the DSP1 can be confirmed.

[0011] Another object of the present invention is to provide an electric drive inverter with a simplified architecture based on a DSP chip. The function state of the DSP1 can be confirmed through the data verification of the DSP2 on the DSP1. If a fault occurs, the level conditioning circuit can be controlled to enter different functional safety states. If the DSP2 has problems, its impact on the system can be isolated. The DSP1 and the DSP2 cross-verify the operation and power supply states of the SBC, the LDO1, and the LDO2 at the same time. Through multiple verifications at the chip level, the high-reliability operation of the electric drive system is realized.

[0012] Another object of the present invention is to provide an electric drive inverter with a simplified architecture based on a DSP chip. The SBC, the LDO1, and the LDO2 are powered by a 12V battery power supply, and a parallel high-voltage power extraction power supply outputs power, which maximally ensures the reliability of the system.

[0013] To achieve the above object, the present invention provides an electric drive inverter with a simplified architecture based on a DSP chip, including a basic function control module and a function verification module. The basic function control module includes a power supply chip SBC, a chip DSP1, and a level conversion circuit. The function verification module includes a power supply chip LDO1, a power supply chip LDO2, and a chip DSP2, wherein:

[0014] For the basic function control module, wherein:

[0015] The chip DSP1 collects the KL30 voltage provided by the 12V battery. The output voltage of the power supply chip SBC ensures the normal power supply function. The chip DSP1 collects the resolver feedback signal and combines it with the output torque target, and outputs a PWM waveform to the IGBT isolation drive chip. At this time, the level conversion chip is in the open state, and the motor control signal is normally output;

[0016] If a fault including overcurrent and overvoltage occurs in the system, the first - layer shutdown logic is that the output instruction of chip DSP1 outputs according to a preset fixed level; the second - layer shutdown logic is that the output instruction of chip DSP1 directly closes the level conversion circuit through a logic circuit to achieve a faster and more stable shutdown method. The second - layer shutdown logic needs to use an external resistor to make the system enter the predetermined lower - bridge - arm ASC functional safety state, and at the same time, the signal is reported to chip DSP2;

[0017] If an extremely serious abnormal fault occurs in the system (such as a high - voltage interlock problem, an abnormal resolver function, etc.), the output instruction of chip DSP1 directly controls the IGBT isolation drive chip through the emergency shutdown ASC circuit, so as to make the system enter the predetermined functional safety state;

[0018] The power supply chip SBC performs WDG verification on chip DSP1 to ensure the normal function of chip DSP1. If it is found that chip DSP1 itself has abnormal operation (such as abnormal software operation, etc.), the power supply chip SBC directly sends an emergency shutdown signal to the IGBT isolation drive chip to make the system enter the predetermined lower - bridge - arm ASC functional safety state; at the same time, the fault data is fed back to chip DSP2, and chip DSP2 verifies the correctness of the current functional safety state according to the motor system speed parameters;

[0019] Chip DSP1 performs the first verification on the PWM output signal to achieve the first - layer PWM signal monitoring function and ensure the comprehensiveness of system function diagnosis; chip DSP2 synchronously performs the second verification on the PWM output signal, compares the verification result with the first verification result of chip DSP1 to confirm the correctness of chip DSP1's verification, and feeds it back to chip DSP1 for diagnosis (further ensuring the correctness of system function diagnosis);

[0020] For the function verification module, among them:

[0021] Chip DSP2 is independently powered through power supply chip LDO1 and power supply chip LDO2, so as to form a data verification function for chip DSP1;

[0022] Chip DSP2 uses the WDG method to maintain the CPU function normality verification with chip DSP1, forming a multi - level shutdown logic for the system; when the WDG passing between chip DSP1 and chip DSP2 occurs abnormally, chip DSP2, as the verification core, determines that the CPU or software operation of chip DSP1 is abnormal, and thus directly makes the system enter the preset functional safety state through the emergency shutdown ASC circuit;

[0023] Chip DSP2 simultaneously samples the resolver model and (uses a software - based position - less algorithm model to simulate) calculates and outputs the torque target, and verifies the information correctness of the torque target output by chip DSP1.

[0024] As a further preferred technical solution of the above technical solution, it further includes a high-voltage isolation backup power supply. The KL30-1 power supply provided by the high-voltage isolation backup power supply (after DCDC buck-down) is connected in parallel at the power supply end of the 12V storage battery.

[0025] The output voltage of the high-voltage isolation backup power supply is preset to be slightly lower than the voltage of the 12V storage battery. When the 12V battery power supply is working stably, the high-voltage power supply is used as a standby power supply and does not work.

[0026] When the power supply link of the 12V storage battery has an abnormality or instability, the high-voltage isolation backup power supply is connected in parallel to automatically maintain voltage stability and ensure the normal operation of the system.

[0027] As a further preferred technical solution of the above technical solution, the chip DSP1 collects the output supply voltages of the power supply chips LDO1 and LDO2, and the chip DSP2 collects the output supply voltage of the power supply chip SBC, so that the chips DSP1 and DSP2 perform cross-checking of the power supply chips.

[0028] As a further preferred technical solution of the above technical solution, if the chip DSP2 detects that the voltage of the power supply chip is abnormal and the voltage abnormality does not affect the normal operation of the chip DPS1 function, the SBC fault is recorded and reported in the chip DSP2.

[0029] If the voltage abnormality affects the normal operation of the chip DPS1 function, there is a risk of abnormal operation of DSP1 and the correctness of control instructions cannot be guaranteed; the chip DSP2 directly controls to turn off the level conversion circuit, and uses an external resistor to realize the function safety state of the system entering the predetermined lower bridge arm ASC state; simultaneously, the chip DSP2 directly controls the IGBT isolation drive chip to enter the preset safety state through the emergency shutdown ASC circuit, ensuring that the system is in the function safety requirement state.

[0030] As a further preferred technical solution of the above technical solution, if the chip DSP1 detects that the power supplies of the power supply chips LDO1 and LDO2 are abnormal, and if the voltage abnormalities of both do not affect the normal operation of the chip DPS2 function, the DSP2 power supply fault is recorded and reported in the chip DSP1.

[0031] If the voltage abnormalities of both affect the normal operation of the chip DPS2 function, there is a risk of abnormal operation of the chip DSP2 and the correctness of the data cross-checking of the chip DSP1 cannot be guaranteed; the chip DSP1 maintains its normal function, and shields the cross-checking signal and the fault response signal of the chip DSP2. The chip DSP1 internally reports the fault flag of the DSP2 and makes a fault record (the system functions, OC, OV and other fault strategies are not affected).

[0032] As a further preferred technical solution of the above technical solution, if a fault occurs in the resolver system, causing the chip DSP1 to be unable to parse the motor signal, the chip DSP2 will monitor the abnormal signal parsing of the chip DSP1 and record the fault, and calculate the resolver result by itself and deliver the calculation result to the chip DSP1, so that the chip DSP1 operates in a reduced power state.

[0033] The beneficial effects of the present invention are as follows:

[0034] 1) The scheme designs SBC+DSP to form the first set of system control schemes, and designs LDO+DSP to form the system multi-layer verification core fault protection logic scheme. This scheme realizes the electric drive inverter system scheme with high reliability and high diagnostic coverage by using low-cost DSP chips.

[0035] 2) The scheme designs the main operation control and verification to be powered by different power supplies. At the same time, the two DSPs cross-check the power supply status of each other, realizing the double-layer monitoring of the operation status of the main arithmetic unit DSP1 by SBC and DSP2. At the same time, DSP2 can also monitor the operation data results of DSP1, realizing the high reliability of the function diagnosis of the system power supply chip and the main arithmetic unit chip;

[0036] 3) The scheme designs a high-voltage power-taking DCDC power supply circuit, which is connected in parallel at the 12V battery power supply terminal, and designs the output voltage of the high-voltage power-taking power supply to be lower than the 12V battery voltage, but can ensure the normal working voltage value of the system; when the 12V battery power supply voltage is unstable, it can directly intervene in the power supply to ensure the normal power supply of the system; when the 12V battery power supply voltage is stable, it does not work as a backup power supply. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic structural diagram of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0038] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles defined in the following description can be applied to other implementation schemes, deformation schemes, improvement schemes, equivalent schemes, and other technical schemes that do not deviate from the spirit and scope of the present invention.

[0039] In the preferred embodiment of the present invention, those skilled in the art should note that the DSP chips and the like involved in the present invention can be regarded as prior art.

[0040] Preferred embodiment.

[0041] Such as Figure 1As shown, the present invention discloses an electric drive inverter with a simplified architecture based on a DSP chip, including a basic function control module and a function verification module. The basic function control module includes a power supply chip SBC, a chip DSP1, and a level conversion circuit. The function verification module includes a power supply chip LDO1, a power supply chip LDO2, and a chip DSP2, where:

[0042] For the basic function control module, where:

[0043] The chip DSP1 collects the KL30 voltage provided by the 12V battery. The output voltage of the power supply chip SBC ensures the normal power supply function. The chip DSP1 collects the resolver feedback signal and combines it with the output torque target, and outputs a PWM waveform to the IGBT isolation drive chip. At this time, the level conversion chip is in the open state, and the motor control signal is normally output;

[0044] If a fault including overcurrent and overvoltage occurs in the system, the first-level shutdown logic is that the output instruction of the chip DSP1 outputs according to a preset fixed level; the second-level shutdown logic is that the output instruction of the chip DSP1 directly closes the level conversion circuit through a logic circuit to achieve a faster and more stable shutdown method. The second-level shutdown logic needs to use an external resistor to enable the system to enter the predetermined lower-bridge arm ASC functional safety state, and at the same time, the signal is reported to the chip DSP2 (the first-level shutdown logic is that the chip DSP1 directly controls the signal to shut down, and the second-level shutdown logic is that the chip DSP1 detects signal abnormalities and considers itself to have problems and cannot effectively control the correctness of the output signal; the level conversion circuit is closed through other signals (function disable signal));

[0045] If an extremely serious fault occurs in the system (such as a high-voltage interlock problem, resolver function abnormality, etc.), the output instruction of the chip DSP1 directly controls the IGBT isolation drive chip through the emergency shutdown ASC circuit, so as to enable the system to enter the predetermined functional safety state;

[0046] The power supply chip SBC performs WDG verification on the chip DSP1 to ensure the normal function of the chip DSP1. If it is found that the chip DSP1 itself has abnormal operation (such as abnormal software operation, etc.), the power supply chip SBC directly sends an emergency shutdown signal to the IGBT isolation drive chip, making the system enter the predetermined lower-bridge arm ASC functional safety state; at the same time, the fault data is fed back to the chip DSP2, and the chip DSP2 verifies the correctness of the current functional safety state according to the motor system speed parameters;

[0047] The chip DSP1 performs the first verification on the PWM output signal to implement the first-layer PWM signal monitoring function and ensure the comprehensiveness of system function diagnosis; the chip DSP2 synchronously performs the second verification on the PWM output signal, compares the verification result with the first verification result of the chip DSP1 to confirm the correctness of the verification of the chip DSP1, and feeds it back to the chip DSP1 for diagnosis (further ensuring the correctness of system function diagnosis);

[0048] For the function verification module, among them:

[0049] The chip DSP2 is independently powered by the power supply chip LDO1 and the power supply chip LDO2, thereby forming a data verification function for the chip DSP1;

[0050] The chip DSP2 uses the WDG method to maintain the normal operation of the CPU function with the chip DSP1 chip to form a multi-level shutdown logic of the system; when an abnormality occurs in the WDG pass between the chip DSP1 and the chip DSP2, the chip DSP2, as the verification core, determines that the CPU or software of the chip DSP1 is operating abnormally, and thus directly enters the preset functional safety state through the emergency shutdown ASC circuit;

[0051] The chip DSP2 simultaneously samples the resolver model and (uses the software positionless algorithm model simulation) calculates and outputs the torque target to verify the information correctness of the torque target output by the chip DSP1.

[0052] Specifically, it also includes a high-voltage isolation backup power supply. The KL30-1 power supply provided by the high-voltage isolation backup power supply (after DCDC step-down) is connected in parallel at the power supply end of the 12V battery;

[0053] The output voltage of the preset high-voltage isolation backup power supply is slightly lower than the voltage of the 12V battery. When the 12V battery power supply works stably, the high-voltage power supply is used as a backup power supply and does not work;

[0054] When an abnormality or instability occurs in the power supply link of the 12V battery, the high-voltage isolation backup power supply is connected in parallel to automatically maintain voltage stability and ensure the normal operation of the system.

[0055] More specifically, the chip DSP1 collects the output supply voltages of the power supply chip LDO1 and the power supply chip LDO2, and the chip DSP2 collects the output supply voltage of the power supply chip SBC, so that the chip DSP1 and the chip DSP2 perform cross-verification of the power supply chips.

[0056] Furthermore, if the chip DSP2 detects that the voltage of the power supply chip is abnormal and the voltage abnormality does not affect the normal operation of the chip DPS1 function, the SBC fault is recorded and reported in the chip DSP2;

[0057] If the abnormal voltage affects the normal operation of the chip DPS1, there is a risk of abnormal operation of DSP1 and the correctness of control instructions cannot be guaranteed; the chip DSP2 directly controls the shutdown of the level conversion circuit and uses an external resistor to enable the system to enter the predetermined functional safety state of the lower bridge arm ASC state; simultaneously, the chip DSP2 directly controls the IGBT isolation drive chip to enter the preset safety state through the emergency shutdown of the ASC circuit, ensuring that the system is in the state required by functional safety.

[0058] Furthermore, if the chip DSP1 detects that there are abnormalities in the power supplies of the power supply chip LDO1 and the power supply chip LDO2, and if the abnormal voltages of the two do not affect the normal operation of the chip DPS2, the power supply failure of DSP2 will be recorded and reported in the chip DSP1;

[0059] If the abnormal voltages of the two affect the normal operation of the chip DPS2, there is a risk of abnormal operation of the chip DSP2 and the correctness of data verification of the chip DSP1 cannot be guaranteed; the chip DSP1 maintains its normal function, and shields the verification signal and the fault response signal of the chip DSP2. The fault flag of DSP2 is reported internally in the chip DSP1 and a fault record is made (the system functions, OC, OV and other fault strategies are not affected).

[0060] Preferably, if a fault occurs in the resolver system and the chip DSP1 is unable to resolve the motor signal, the chip DSP2 will monitor the abnormal signal resolution of the chip DSP1 and record the fault, calculate the resolver result by itself and deliver the result to the chip DSP1 to enable the chip DSP1 to operate in a reduced power state.

[0061] It is worth mentioning that the technical features such as the DSP chip involved in this invention patent application should be regarded as the prior art. The specific structures, working principles, and possible control methods and spatial layout methods of these technical features can be selected conventionally in the art and should not be regarded as the inventive points of this invention patent. This invention patent will not be further specifically elaborated.

[0062] For those skilled in the art, it is still possible to modify the technical solutions recorded in the foregoing embodiments or perform equivalent replacements on some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A motor drive inverter with a simplified architecture based on a DSP chip, characterized in that, It includes a basic function control module and a function verification module. The basic function control module includes a power supply chip SBC, a chip DSP1, and a level conversion circuit. The function verification module includes a power supply chip LDO1, a power supply chip LDO2, and a chip DSP2. Among them: For the basic function control module, among which: The chip DSP1 collects the KL30 voltage provided by the 12V battery. The power supply chip SBC outputs a voltage to ensure the normal operation of the power function. The chip DSP1 collects the resolver feedback signal and combines it with the output torque target, and outputs a PWM waveform to the IGBT isolation drive chip. At this time, the level conversion chip is in the open state, and the motor control signal is normally output; If a fault including overcurrent and overvoltage occurs in the system, the first - layer shutdown logic is that the output instruction of the chip DSP1 outputs according to a preset fixed level; the second - layer shutdown logic is that the output instruction of the chip DSP1 directly closes the level conversion circuit through a logic circuit to achieve a faster and more stable shutdown method. The second - layer shutdown logic needs to use an external resistor to enable the system to enter the predetermined lower - bridge - arm ASC functional safety state, and at the same time, the signal is reported to the chip DSP2; If an extremely serious abnormal fault occurs in the system, the output instruction of the chip DSP1 directly controls the IGBT isolation drive chip through the emergency shutdown ASC circuit, so as to enable the system to enter the predetermined functional safety state; The power supply chip SBC conducts WDG verification on the chip DSP1 to ensure the normal function of the chip DSP1. If it is found that the chip DSP1 itself has abnormal operation, the power supply chip SBC directly sends an emergency shutdown signal to the IGBT isolation drive chip to make the system enter the predetermined lower - bridge - arm ASC functional safety state; at the same time, the fault data is fed back to the chip DSP2, and the chip DSP2 verifies the correctness of the current functional safety state according to the motor system speed parameters; The chip DSP1 conducts the first verification on the PWM output signal to realize the first - layer PWM signal monitoring function and ensure the comprehensiveness of the system function diagnosis; the chip DSP2 synchronously conducts the second verification on the PWM output signal, compares the verification result with the first verification result of the chip DSP1 to confirm the correctness of the chip DSP1 verification, and feeds it back to the chip DSP1 for diagnosis; For the function verification module, among which: The chip DSP2 is independently powered through the power supply chip LDO1 and the power supply chip LDO2, so as to form a data verification function for the chip DSP1; The chip DSP2 uses the WDG method to maintain the CPU function normality verification with the chip DSP1, forming a multi - level shutdown logic for the system; if an abnormality occurs when the WDG of the chip DSP1 and the chip DSP2 passes, the chip DSP2 acts as a verification core to determine that the CPU or software operation of the chip DSP1 is abnormal, and thus directly makes the system enter the preset functional safety state through the emergency shutdown ASC circuit; The chip DSP2 simultaneously samples the resolver model and calculates the output torque target, and verifies the information correctness of the torque target output by the chip DSP1.

2. The electric drive inverter with a simplified architecture based on a DSP chip according to claim 1, wherein It also includes a high-voltage isolation backup power supply. The KL30-1 power supply provided by the high-voltage isolation backup power supply is connected in parallel at the power supply end of the 12V battery. It is preset that the output voltage of the high-voltage isolation backup power supply is lower than the voltage of the 12V battery. When the 12V battery power supply works stably, the high-voltage power extraction power supply serves as a standby power supply and does not work. When an abnormality or instability occurs in the power supply link of the 12V battery, the high-voltage isolation backup power supply is connected in parallel to automatically maintain voltage stability and ensure the normal operation of the system.

3. The electric drive inverter with a simplified architecture based on a DSP chip according to claim 2, characterized in that, The chip DSP1 collects the output supply voltages of the power supply chips LDO1 and LDO2, and the chip DSP2 collects the output supply voltage of the power supply chip SBC, so that the chips DSP1 and DSP2 perform cross-checking of the power supply chips.

4. The electric drive inverter with a simplified architecture based on a DSP chip according to claim 3, characterized in that, If the chip DSP2 detects that the voltage of the power supply chip is abnormal and the voltage abnormality does not affect the normal operation of the chip DPS1 function, then the SBC fault is recorded and reported in the chip DSP2. If the voltage abnormality affects the normal operation of the chip DPS1 function, then there is a risk of abnormal operation of DSP1 and the correctness of the control instruction cannot be guaranteed; the chip DSP2 directly controls to turn off the level conversion circuit and uses an external resistor to enable the system to enter the predetermined lower arm ASC state functional safety state; simultaneously, the chip DSP2 directly controls the IGBT isolation drive chip to enter the preset safety state through the emergency shutdown ASC circuit to ensure that the system is in the functional safety requirement state.

5. The electric drive inverter with a simplified architecture based on a DSP chip according to claim 3, wherein, If the chip DSP1 detects that the power supplies of the power supply chips LDO1 and LDO2 are abnormal, if the voltage abnormalities of both do not affect the normal operation of the chip DPS2 function, then the DSP2 power supply fault is recorded and reported in the chip DSP1. If the voltage abnormalities of both affect the normal operation of the chip DPS2 function, then there is a risk of abnormal operation of the chip DSP2 and the correctness of the data cross-checking of the chip DSP1 cannot be guaranteed; the chip DSP1 maintains normal functions, and shields the cross-checking signal and the fault response signal of the chip DSP2, and the chip DSP1 internally reports the fault flag of the DSP2 and makes a fault record.

6. The electric drive inverter with a simplified architecture based on a DSP chip according to claim 3, characterized in that, If a fault occurs in the resolver system, causing the chip DSP1 to be unable to parse the motor signal, the chip DSP2 will monitor the abnormal signal parsing of the chip DSP1 and record the fault, and calculate the resolver result by itself and deliver the calculation result to the chip DSP1 to enable the chip DSP1 to enter the reduced power operation state.

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