Digital clock data recovery device
Through the digital clock data recovery device, the phase difference compensation unit, a digital loop filter and a digital control oscillator are used to achieve rapid locking time and circuit size reduction under no reference clock. It is suitable for a variety of communication protocols, and solves the problem of long locking time in high-speed data transmission.
Patent Information
- Application Number
- CN202510022212.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-11-28
- Filing Date
- 2025-01-07
- Publication Date
- 2025-07-08
AI Technical Summary
In the prior art, in high-speed data transmission, there is a problem of long locking time and limited circuit size during clock data recovery, especially in the absence of a reference clock, it is difficult to effectively shorten the locking time.
The digital clock data recovery device is adopted, including a phase difference compensation unit, a digital loop filter and a digital control oscillator. Through embedded signal operation, the clock and data recovery is achieved using a time-digital converter and a phase detector. It is suitable for a variety of protocols, and the frequency division ratio is adjusted through the frequency divider to adapt to different communication protocols.
It realizes fast locking time without reference clock, shortens locking time, while reducing circuit size and scalability, and is suitable for a variety of communication protocols, reducing circuit complexity and cost.
Smart Images
Figure CN120281312A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a digital clock data recovery device. Background Art
[0002] With the recent development of communication technologies, the demand for high-speed data transmission has also increased. For this purpose, a serial communication method for high-speed data transmission has been adopted. The serial communication method can be used in various communication processes such as communication between independent devices, communication between components included in a system, and data movement inside an integrated circuit.
[0003] The following clock data recovery circuit can be used in various devices that transmit and receive data in a serial communication manner. The clock data recovery circuit generates a recovered clock from serial data by detecting the phase of a clock embedded in the serial data, and generates recovered data from the serial data using the recovered clock.
[0004] In such a communication method, it is necessary to recover a clock from data and align the phase of the recovered clock. In order to recover a clock and data from a data signal, first, the clock is recovered, and then the recovered clock is used to recover the data. For this purpose, the frequency and phase of the clock can be fixed.
[0005] In such a data recovery process, it is desirable to reduce the time required to fix the frequency and phase, that is, to reduce the lock-in time, but it may impose limitations on the size of the circuit.
[0006] Therefore, there is a need for a solution that can reduce the lock-in time while effectively configuring the circuit size and structure. Summary of the Invention
[0007] Problems to be Solved
[0008] An object of the present disclosure is to provide a digital clock data recovery device and method that can operate through an embedded signal without a reference clock.
[0009] An object of the present disclosure is to provide a digital clock data recovery device and method that can be used under various protocols.
[0010] An object of the present disclosure is to provide a digital clock data recovery device and method that can shorten the lock-in time.
[0011] Means for Solving the Problems
[0012] A digital clock data recovery device according to an embodiment of the present disclosure is a digital clock data recovery device that recovers a clock and data from a data signal, and may include: a phase difference compensation unit that selectively outputs a high-order value and a low-order value among phase differences of a first input signal and a second input signal according to a condition based on a range of phase difference values; a digital loop filter that inputs an output of the phase difference compensation unit; and a digitally controlled oscillator that transmits a feedback signal to the phase difference compensation unit according to an output value of the digital loop filter.
[0013] A digital clock data recovery device according to an embodiment of the present disclosure is a digital clock data recovery device that recovers a clock and data from a data signal, and may include: a time-to-digital converter (TDC) that compares a phase difference between a reference signal and a data signal and outputs a first bit value; a digital loop filter that inputs an output value of the time-to-digital converter; a digitally controlled oscillator that oscillates a signal according to an output value of the digital loop filter; and a phase detector that accumulates a number of phase differences between the data signal and an output of the digitally controlled oscillator and outputs a second bit value.
[0014] Advantages of the Invention
[0015] According to an embodiment of the present disclosure, a clock data recovery device can be implemented as a complete digital circuit. The clock data recovery device does not require a reference clock and can operate with only one embedded clock signal. Thus, the clock data recovery device implemented as a digital circuit has the advantage of a short lock-in time. In addition, there is greater scalability in terms of process variations.
[0016] As described above, by respectively arranging frequency dividers capable of changing a frequency division ratio between an input path and a feedback path, it can be applied to multiple protocols.
[0017] On the other hand, in order to improve resolution, although a total of 9-bit data can be used, for example, since the time-to-digital converter can be implemented only with high bits (for example, 6 bits), the size of the circuit can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 is a block diagram showing a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0019] Figure 2 is a timing diagram showing the operation of a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0020] Figure 3 is a sequence diagram showing the operation of a clock data recovery device according to an embodiment of the present disclosure.
[0021] Figure 4 is a block diagram of a digitally controlled oscillator of a clock data recovery device showing an exemplary embodiment according to the present disclosure.
[0022] Figure 5 is a block diagram of a time-to-digital converter of a clock data recovery device showing an exemplary embodiment according to the present disclosure.
[0023] Figure 6 is a block diagram of a phase detector of a clock data recovery device showing an exemplary embodiment according to the present disclosure.
[0024] Figure 7 and Figure 8 is a timing diagram for explaining the operation of the phase detector.
[0025] Figure 9 is a block diagram of a frequency divider of a clock data recovery device showing an exemplary embodiment according to the present disclosure.
[0026] Figures 10 to 12 is a timing diagram of the frequency divider. DETAILED DESCRIPTION
[0027] Hereinafter, embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings. Regardless of the reference signs, the same or similar components will be given the same reference numerals, and repeated descriptions thereof will be omitted. The suffixes "module" and "section" of the components used in the following description are given or mixed only for the convenience of writing the specification, and do not have a meaning or function of distinguishing from each other.
[0028] In addition, when describing the embodiments disclosed in the present specification, if a detailed description of the related prior art may obscure the gist of the embodiments disclosed in the present specification, the detailed description will be omitted. In addition, it should be noted that the drawings are only used to help understand the embodiments disclosed in the present specification, and the technical idea disclosed in the present specification should not be construed as being limited by the drawings.
[0029] Furthermore, for convenience of explanation, each drawing is described, but the case where those skilled in the art implement other embodiments by combining at least two or more drawings also falls within the scope of the present invention.
[0030] In addition, when it is mentioned that a component such as a layer, a region, or a substrate is "on" another component, it can be understood that the component is directly on the other component, or there may be an intermediate component between the components.
[0031] Terms such as "first" and "second" are used to distinguish one component from another component, and they do not mean that the components are limited by the above terms.
[0032] Unless there is an obvious exception in the context, singular expressions generally include plural expressions.
[0033] In each step, the identifier is used for convenience of explanation. The identifier does not indicate the order of each step. Unless a specific order is clearly specified in the context, each step can be implemented in an order different from the clearly described order.
[0034] Figure 1 is a block diagram showing a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0035] Referring to Figure 1 , the clock data recovery device 10 may include a phase difference compensation unit 101, a digital loop filter (DLF) 200, and a digitally controlled oscillator (DCO) 300.
[0036] The phase difference compensation unit 101 may output a high-order value (COARSE[5:0]) and a low-order value (FINE[2:0]) for the phase difference between the first input signal (DIN) and the second input signal (CK0) according to conditions based on the range of the phase difference value.
[0037] As an exemplary embodiment, the phase difference compensation unit 101 may include a selectively operating time-to-digital converter (TDC) 100 and a phase detector (PD) 400. Here, the phase detector 400 may also be referred to as a bang-bang phase detector.
[0038] For example, in the case of using 9-bit data, the high-order value may correspond to the high 6-bit value, and the low-order value may correspond to the low 3-bit value. Another example is that the high-order value may be the MSB (Most Significant Bit), and the low-order value may be the LSB (Least Significant Bit). For example, the high-order value may be 3 bits of the MSB, and the low-order value may be 6 bits of the LSB.
[0039] The digital loop filter 200 may input an error signal and generate a digital control code. For example, the output signal of the phase difference compensation unit 101 may be input and a corresponding control code (VCONT) may be output.
[0040] The input signal may be input to the time-to-digital converter 100 and the phase detector 400, and the signals output by each of them may be input to the digital loop filter 200.
[0041] A Digital Controlled Oscillator (DCO) 300 can transmit a feedback signal to a phase difference compensation unit 101 according to an output value (VCONT) of a digital loop filter 200.
[0042] As an example, such a digital controlled oscillator 300 can oscillate four signals with a 90-degree phase difference according to an output value (VCONT) of the digital loop filter 200. As an example, the digital controlled oscillator 300 can oscillate a CK0 signal with zero phase, a CK90 signal with a 90-degree phase difference relative to CK0, a CK180 signal with a 90-degree phase difference relative to CK90, and a CK270 signal with a 90-degree phase difference relative to CK180.
[0043] As an exemplary embodiment, the digital controlled oscillator 300 can use a total of 9 bits to control the oscillation frequency. At this time, the upper 6 bits can use the value obtained by comparison in the time-to-digital converter 100, and the lower 3 bits can use the value obtained by comparison in the phase detector 400.
[0044] As an example, when the phases of the reference signal (Ref) and the feedback signal (Fed) in the time-to-digital converter 100 are consistent within a certain range (course), the phase is locked (LOCK = H), the operation of the time-to-digital converter 100 stops, and subsequently the phase detector 400 can operate.
[0045] If, after the phase is locked (LOCK = H), the phases of the reference signal (Ref) and the feedback signal (Fed) deviate from a certain range (course), the phase is no longer locked (LOCK = L), and the time-to-digital converter 100 will start operating again.
[0046] The phase difference compensation unit 101 may further include a frequency divider 500 that divides the data signal (DIN) and the output signal (CK0) of the digital controlled oscillator 300.
[0047] The frequency divider 500 may include a first frequency divider 510 that divides the data signal (DIN) and a second frequency divider 520 that divides the output signal (CK0) of the digital controlled oscillator.
[0048] Here, as an example, the reference signal (Ref; first input signal) may be a signal obtained by dividing the input data signal (DIN) by the first frequency divider 510. The feedback signal (Fed; second input signal) may be a signal obtained by dividing the output signal (CK0) of the digital controlled oscillator 300 by the second frequency divider 520.
[0049] Thus, the input data signal (DIN) and the output signal (CK0) of the digital controlled oscillator 300 can be respectively input to the time digital converter 100 after being divided by the frequency division unit 500.
[0050] In addition, a serializer (S2P) 600 may be included. The serializer (S2P) 600 is connected to the phase detector 400 and outputs the recovered data. Such a serializer (Seiral to Parallel) 600 can serialize and output the recovered clock and data.
[0051] Thus, according to the present disclosure, the digital clock data recovery device 10 for recovering a clock and data from a data signal may include: a phase difference compensation unit 101 that selectively outputs a high-order value and a low-order value among the phase differences of the first input signal and the second input signal according to a condition based on the range of the phase difference value; a digital loop filter (DLF) 200 that inputs the output of the phase difference compensation unit 101; and a digital controlled oscillator (DCO) 300 that transmits a feedback signal to the phase difference compensation unit 101 according to the output value of the digital loop filter 200.
[0052] As an exemplary embodiment, according to the present disclosure, the digital clock data recovery device 10 for recovering a clock and data from a data signal may include: a time digital converter 100 that compares and outputs the phase difference between a reference signal and a data signal; a digital loop filter 200 that inputs the output value of the time digital converter 100; a digital controlled oscillator 300 that oscillates a signal according to the output value of the digital loop filter 200; and a phase detector 400 that accumulates and outputs the number of times of the phase difference between the data signal and the output of the digital controlled oscillator.
[0053] At this time, the output of the digital controlled oscillator 300 can be input to the time digital converter 100 and the phase detector 400.
[0054] In other words, according to the output value of the digital controlled oscillator 300, the time digital converter 100 can operate under the first condition, and the phase detector 400 can operate under the second condition.
[0055] According to an embodiment, the digital loop filter 200 can receive skew information from the time digital converter 100 and control the phase of the clock so that the clock oscillated from the digital controlled oscillator 300 and the reference clock signal (Ref) are locked.
[0056] When it is detected that the value of the phase error signal is dithering around "0", the digital loop filter 200 may determine that locking has been achieved. For example, the digital loop filter 200 may receive the leading value of the clock phase or the lagging value of the clock phase received from the time-to-digital converter 100, and generate a DCO control code and provide it to the digitally controlled oscillator 300. According to one embodiment, the digitally controlled oscillator 300 may generate a variable-frequency signal based on the digital control code received from the digital loop filter 200.
[0057] According to one embodiment, the digital loop filter 200 may receive a phase error signal from the phase detector 400 and control the phase of the clock so that the data and the clock are locked. When the value of the phase error signal is dithering around "0", the digital loop filter 200 may determine that locking has been achieved. For example, the digital loop filter 200 may receive the leading value of the clock phase or the lagging value of the clock phase received from the phase detector 400, and generate a DCO control code and provide it to the digitally controlled oscillator 300. According to one embodiment, the digitally controlled oscillator 300 may generate a variable-frequency signal based on the digital control code received from the digital loop filter 200.
[0058] Figure 2 is a timing diagram showing the operation of a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0059] The clock data recovery device 10 according to the present disclosure may operate through an embedded clock without a reference clock, and may be implemented entirely as a digital circuit. Thus, no reference clock means that the clock is embedded in the data, and the clock can be extracted and used.
[0060] Initially, when the clock data recovery device 10 operates, the digitally controlled oscillator 300 may operate as a so-called quadrature DCO that outputs the input phase in four ways.
[0061] At this time, the output data signal and the output of the input data signal of the digitally controlled oscillator 300 are divided in frequency and input to the time-to-digital converter (TDC) 100.
[0062] The time-to-digital converter 100, as a phase comparator, may require two inputs. Therefore, the frequency division unit 500 may include a first frequency divider 510 and a second frequency divider 520.
[0063] These two frequency dividers 510 and 520 can be added for use under multiple protocols. Here, the first frequency divider 510 can have a first division ratio (N1), and the second frequency divider 520 can have a second division ratio (N2).
[0064] For the signal input to the frequency division unit 500, one phase can have a time of 4UI. Initially, the clock of the signal can be tuned. As an example, when the signal is first input, the signal can be compared with its least common multiple. During this comparison process, the rising edge of the signal can be compared.
[0065] The output signal of this time-to-digital converter 100 or phase detector 400 can be input to the digital loop filter 200. In the digital loop filter 200, a VCONT signal can be output as an analog signal.
[0066] According to the output signal (VCONT) of the digital loop filter 200, the oscillation frequency of the digitally controlled oscillator 300 can change. As an example, the output signal can be 1.8V.
[0067] Therefore, each step can increase, for example, by 20 mV each time, so that the oscillation frequency can increase.
[0068] In an embodiment of the present disclosure, since the division ratio may be different according to different protocols, two frequency dividers 510 and 520 can be included to make the clock signal and data signal consistent.
[0069] Here, the first division ratio (N1) and the second division ratio (N2) can be determined according to the spec. As an example, the frequency division unit 500 can be a programmable frequency divider. This will be further described with reference to the drawings.
[0070] Figure 3 It is a sequence diagram showing the operation of the clock data recovery device according to an embodiment of the present disclosure.
[0071] Hereinafter, with reference to Figures 1 to 3 , the operation of the clock data recovery device 10 according to an embodiment of the present disclosure will be described step by step.
[0072] First, the input data signal (DIN) can be branched and input to the time-to-digital converter 100 or phase detector 400 through the frequency division unit 500. As described above, the output of the digitally controlled oscillator 300 can be input to the time-to-digital converter 100 under the first condition and input to the phase detector 400 under the second condition.
[0073] At this time, under the first condition, the data signal (reference signal; Ref) that has passed through the first frequency divider 510 and the output signal (feedback signal; Feb) of the digital control oscillator 300 that has passed through the second frequency divider 520 can be input to the time-to-digital converter 100.
[0074] The time-to-digital converter 100 can output a signal (S10) corresponding to the phase difference between the data signal (reference signal; Ref) and the output signal (feedback signal; Feb).
[0075] Subsequently, the digital loop filter 200 can receive the signal (digital bit) from the time-to-digital converter 100 and convert it into a digital value that the digital control oscillator 300 can recognize. The digital value (VCONT) thus converted can be input to the digital control oscillator 300 (S20).
[0076] Next, the digital control oscillator 300 can oscillate four signals with a 90-degree phase difference according to the output value (VCONT) of the digital loop filter 200. For example, the digital control oscillator 300 can oscillate a CK0 signal with zero phase, a CK90 signal with a 90-degree phase difference relative to CK0, a CK180 signal with a 90-degree phase difference relative to CK90, and a CK270 signal with a 90-degree phase difference relative to CK180.
[0077] Thus, the output (CK0) oscillated by the digital control oscillator 300 can be input to the time-to-digital converter 100 after being divided by the second frequency divider 520 of the frequency division unit 500 (S30).
[0078] At this time, if the phase difference between the reference signal (Ref) and the feedback signal (Feb) is within a certain condition range, the time-to-digital converter 100 can achieve locking.
[0079] As an example, the time-to-digital converter 100 can adjust the time difference (phase difference) between the two input signals (Ref, Feb) to within a certain condition range. For example, the time-to-digital converter 100 can adjust the time difference (phase difference) between the two input signals (Ref, Feb) to a range within about 10%.
[0080] The time-to-digital converter 100 can output the high-order value data (Coarse) in the phase difference value between the first input signal (DIN) and the second input signal (CK0). For example, when using 9-bit data, the data corresponding to the high 6 bits ([5:0]) can be compared in the time-to-digital converter 100.
[0081] It is possible to determine whether the time difference (phase difference) between two inputs (Ref, Feb) (i.e., the first input signal (DIN) and the second input signal (CK0)) is within a certain condition range (S40).
[0082] Thus, if the time difference (phase difference) between two inputs (Ref, Feb) (i.e., the first input signal (DIN) and the second input signal (CK0)) is within a certain condition range (yes: LOCK = H), a lock signal (LOCK = H) can be issued and the time-to-digital converter 100 stops operating.
[0083] Locking can be achieved by an independent lock detector. As an example, if the phase difference between two input signals (Ref, Feb) is within a certain condition range, the lock detector can detect that locking has been completed.
[0084] Conversely, if the time difference (phase difference) between two inputs (Ref, Feb) (i.e., the first input signal (DIN) and the second input signal (CK0)) is not within a certain condition range (no; LOCK = L), the time-to-digital converter 100 can perform the above actions. That is, the time-to-digital converter 100 can output a signal corresponding to the phase difference between the data signal (reference signal; Ref) and the output signal (feedback signal; Feb) (S10).
[0085] Thus, if the time difference (phase difference) between two inputs (Ref, Feb) (i.e., the first input signal (DIN) and the second input signal (CK0)) is within a certain condition range (yes; LOCK = H), the time-to-digital converter 100 can stop operating, or its output value can be fixed to a specific value. In addition, the phase detector 400 can compare the phases between the first input signal (DIN) and the second input signals (CK0 to CK270) (S50).
[0086] As an example, the phase detector 400 can compare the phases between the first input signal (DIN) and the second input signals (CK0 to CK270), accumulate the number of phase differences, and output them.
[0087] The phase detector 400 can compare the phases between the first input signal (DIN) and the second input signals (CK0 to CK270), compare the lower bit values, and output them.
[0088] As an example, in the case of using 9-bit data, the phase detector 400 can output 3-bit ([2:0]) data.
[0089] Figure 2The increase and decrease states of the output signal (VCONT) of the digital loop filter 200 in the above process are shown.
[0090] In this way, the time-to-digital converter 100 can compare only the clock training mode without performing data comparison. The actual data can be compared in the phase detector 400. As an example, the phase detector 400 can detect the phase of the data after locking.
[0091] Through the above process, the finally recovered data can be serialized and output (S60) by a serializer (Serial to Parallel) 600.
[0092] In the frequency division unit 500, the division ratios N1(2) and N2(5) can be set to the least common multiple so that the time-to-digital converter 100 can compare two signals at the same time.
[0093] According to an embodiment of the present disclosure, since it is implemented digitally, all protocols can be used. For example, for the same digital structure, the speeds can be consistent.
[0094] In addition, according to an embodiment of the present disclosure, since an embedded clock signal without a reference clock is used, when this embodiment is implemented as an integrated circuit (IC), the number of output pins can be reduced.
[0095] According to an embodiment of the present disclosure, since the signal locking is achieved through the time-to-digital converter 100 and the phase detector 400, the locking can be completed in a short time.
[0096] As an example, in 9-bit data, the high-order values (6 MSBs (large significant digits)) are determined by the time-to-digital converter 100, and the remaining low-order values (3 LSBs (small significant digits)) of the data are determined by the phase detector 400.
[0097] According to the conventional technology, since the phase noise is determined according to the resolution of the time-to-digital converter, it is required to improve the resolution of the time-to-digital converter, resulting in the problem of an increase in the size of the time-to-digital converter circuit. On the other hand, if the resolution of the time-to-digital converter is low, the phase error between the clock and the divider output increases, resulting in the problem of a decline in the phase noise characteristics. If a phase detector is used instead of the time-to-digital converter, although the time-to-digital converter circuit can be reduced, there may be a problem of a longer locking time.
[0098] However, according to an embodiment of the present disclosure, a clock data recovery device can be implemented as a complete digital circuit that does not require a reference clock and can operate with only one embedded clock signal. In this way, the clock data recovery device implemented as a digital circuit has the advantage of short lock-in time. In addition, there is greater scalability in terms of process variations.
[0099] As described above, by separately configuring a frequency divider that can change the frequency division ratio between the input path and the feedback path, it can be applied to multiple protocols.
[0100] On the other hand, in order to improve the resolution, although a total of 9-bit data can be used, for example, since the time-to-digital converter 100 can be implemented only with high bits (e.g., 6 bits), the size of the circuit can be reduced.
[0101] Figure 4 It is a block diagram showing a digital control oscillator of a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0102] Referring to Figure 4 , the digital controlled oscillator (DCO) 300 includes a plurality of cells (Cell 1, Cell 2, and Cell 3).
[0103] The coarse code or fine code adjusts the current value inside the inverter unit. The delay of the inverter unit shortens as the drive current increases and lengthens as the drive current decreases. At this time, if the delay of the inverter unit shortens, a high-speed oscillation frequency is generated, and if the delay lengthens, a low-speed frequency is generated.
[0104] According to this embodiment, the digital control oscillator 300 may include a first unit (Cell 1 and Cell 2) corresponding to a high-order value and a second unit (Cell 3) corresponding to a low-order value. At this time, the number of the first units (Cell 1 and Cell 2) may be more than the number of the second units (Cell 3).
[0105] In this way, since there are 2 cells (the first unit) receiving the coarse code and 1 cell (the second unit) receiving the fine code, the amount of change in the oscillation frequency caused by the coarse code is greater than the amount of change in the frequency caused by the fine code.
[0106] The CK0 frequency of the digital control oscillator 300 can vary continuously. As an example, if the voltage increases, the frequency also increases accordingly. That is, the voltage can act in direct proportion to the frequency. When the frequency is low, the voltage can be increased. In such a process, the voltage can be increased to make the two output voltages the same. This cyclic operation can be referred to as a PLL (phase looplock) process.
[0107] Figure 5 It is a block diagram showing a time-to-digital converter of a clock data recovery device according to an exemplary embodiment of the present disclosure.
[0108] According to one embodiment, the time-to-digital converter 100 may receive a reference clock signal (Ref) and a clock signal divided from the digital control oscillator 300. The time-to-digital converter 100 may detect a time difference by comparing the reception time points of the reference clock signal (Ref) and the divided clock signal.
[0109] For example, the time-to-digital converter 100 may generate offset information (skew info) for indicating the time difference. For example, the time-to-digital converter 100 may receive the reference clock signal (Ref) at a first time point, and may receive the clock signal divided from the digital control oscillator 300 at a second time point later than the first time point. At this time, the time-to-digital converter 100 may determine how many clocks have elapsed between the first time point and the second time point based on the reference clock signal, and generate the offset information.
[0110] This time-to-digital converter (TDC) 100 compares the positions of the rising edges of the START signal (Ref) and the STOP signal (Feb).
[0111] If the START signal (Ref) is earlier than the STOP signal (Feb), the CLK (= STOP) of the DFF captures High, so it is in the Q = H state.
[0112] Conversely, if the START signal (Ref) lags behind the STOP signal (Feb), it is in the Q = L state.
[0113] However, a buffer delay can be added only in the path of the START signal (Ref). Therefore, for example, if the START signal (Ref) is initially 500 ps earlier than the STOP signal (Feb), and assuming the buffer delay is 200 ps, then Q[0] = H, Q[1] = H, Q[2] = H, Q[3] = L...
[0114] At this time, the number of Hs of the Q value can be used to know numerically how much the START signal (Ref) leads the STOP signal (Feb).
[0115] Figure 6 is a block diagram showing a phase detector of a clock data recovery device according to an exemplary embodiment of the present disclosure. Figure 7 and Figure 8 is a timing diagram for explaining the operation of the phase detector.
[0116] Referring to Figure 6 , according to one embodiment, the phase detector 400 may receive signals from a comparison sampler (not shown) to determine whether the data and the clock are consistent or whether the clock leads or lags the data. The phase detector 400 may determine the locking or leading or lagging of the clock based on the change in the output value of the comparison sampler (not shown) received within a predefined interval (unit interval, UI).
[0117] The phase detector 400 may include a first XOR gate and a second XOR gate. The output of the first XOR gate may be a signal indicating that the clock leads the data. The output of the second XOR gate may be a signal indicating that the clock lags the data. The first XOR gate and the second XOR gate may generate an output indicating the leading of the clock or the leading of the data by comparing the data at the falling edge (DN) of the clock with the rising edges (UP) at both ends of the falling edge.
[0118] In other words, the phase detector 400 compares the phases of the input signal (DIN) and the oscillation signal (CK0). If the rising edge of the input signal (DIN) is earlier than CK0, the UP signal is set to “H” (at this time DN = “L”), and if the rising edge of the input signal (DIN) is later than CK0, the DN signal is set to “H” (at this time UP = “H”).
[0119] At this time, the counter compares the number of UPs and DNs. If the number of UPs is more than that of DNs, the value of Fine[2:0] increases, and if the number of UPs is less than that of DNs, the count value of Fine[2:0] decreases.
[0120] Figure 7 shows the principle of generating the UP / DN signal in the phase detector. Referring to Figure 7 , shows the process of generating each DN and UP.
[0121] Figure 8 shows the signals input to the parallelizer. Referring to Figure 8, showing the input signal (DIN) and the oscillation signals (CK90, CK270), as well as the relative phases of DATA0 and DATA1 generated by the phase detector 400. In addition, the relative phases of the final data (DATA0 and DATA1) generated by the phase detector 400 are also shown.
[0122] Figure 9 is a block diagram showing a frequency division unit of a clock data recovery device according to an exemplary embodiment of the present disclosure. Figures 10 to 12 is a timing diagram of the frequency division unit.
[0123] According to an embodiment of the present disclosure, two frequency dividers 510 and 520 may be added to the frequency division unit 500 to enable use under multiple protocols. Here, the first frequency divider 510 may have a first division ratio (N1), and the second frequency divider 520 may have a second division ratio (N2).
[0124] The signal input to the frequency division unit 500 may have a time with a phase of 4UI. Initially, the clock of the signal may be tuned. For example, when the signal first enters, the signal may be compared with the least common multiple. During this comparison process, the rising edge of the signal may be compared.
[0125] In an embodiment of the present disclosure, since the division ratios are different according to different protocols, in order to make the clock signal consistent with the data signal, the frequency division unit 500 may include two frequency dividers 510 and 520.
[0126] Here, the first division ratio (N1) and the second division ratio (N2) may be determined according to the specification (spec). For example, the frequency division unit 500 may be a programmable frequency divider.
[0127] Figure 10 is a timing diagram when the period of the Embedded-clock is 5UI. At this time, the first division ratio (N1) and the second division ratio (N2) may be 4 and 5 respectively.
[0128] Figure 11 is a timing diagram when the period of the Embedded-clock is 6UI. At this time, the first division ratio (N1) and the second division ratio (N2) may be 2 and 3 respectively.
[0129] Figure 12 is a timing diagram when the period of the Embedded-clock is 20UI. At this time, the first division ratio (N1) and the second division ratio (N2) may be 1 and 5 respectively.
[0130] The above-mentioned first division ratio (N1) and second division ratio (N2) may be externally input when the signal is determined.
[0131] According to an embodiment of the present disclosure, the above method can be implemented by recording the program in a form of code readable by a processor on a medium. Examples of the processor-readable medium include ROM, RAM, CD-ROM, magnetic tape, floppy disk, optical data storage device, etc., and also include content implemented in the form of a carrier wave (e.g., transmitted through the Internet).
[0132] The display device as described above is not limited to the configurations and methods of the above embodiments, and all or part of the content of each embodiment can be selectively combined to form, so that the above embodiments can be implemented through various deformations.
Claims
1. A digital clock data recovery device that recovers a clock and data from a data signal, the digital clock data recovery device comprising: A phase difference compensation unit that selectively outputs a high-order value and a low-order value among the phase differences of a first input signal and a second input signal according to a condition based on a range of phase difference values; A digital loop filter that inputs the output of the phase difference compensation unit; and A digital control oscillator that transmits a feedback signal to the phase difference compensation unit according to the output value of the digital loop filter.
2. The digital clock data recovery device according to claim 1, wherein The digital clock data recovery device further comprises a frequency divider that divides the data signal and the output signal of the digital control oscillator.
3. The digital clock data recovery device according to claim 2, wherein The frequency divider comprises: A first frequency divider that divides the data signal; and A second frequency divider that divides the output signal of the digital control oscillator.
4. The digital clock data recovery device according to claim 3, wherein The first input signal and the second input signal are respectively input through the first frequency divider and the second frequency divider.
5. The digital clock data recovery device according to claim 1, wherein The magnitude of the high-order value is greater than the magnitude of the low-order value.
6. The digital clock data recovery device according to claim 1, wherein The digital control oscillator comprises: A first unit corresponding to the high-order value; and A second unit corresponding to the low-order value.
7. The digital clock data recovery device according to claim 6, wherein The number of the first units is greater than the number of the second units.
8. The digital clock data recovery device according to claim 1, wherein The phase difference compensation unit comprises: A time-to-digital converter that operates under a first condition, inputs the first input signal and the second input signal, and outputs a high-order value among the phase differences of the first input signal and the second input signal; and A phase detector that operates under a second condition, inputs the first input signal and the second input signal, and outputs a low-order value among the phase differences of the first input signal and the second input signal.
9. The digital clock data recovery device according to claim 8, wherein The digital clock data recovery device further comprises a parallelizer that is connected to the phase detector to output the recovered data.
10. A digital clock data recovery device that recovers a clock and data from a data signal, wherein, The digital clock data recovery device comprises: A time-to-digital converter that compares the phase difference between a reference signal and a data signal and outputs a first-order value; A digital loop filter that inputs the output value of the time-to-digital converter; A digital control oscillator that oscillates a signal according to the output value of the digital loop filter; A phase detector that accumulates the number of phase differences between the data signal and the output of the digital control oscillator and outputs a second-order value.
11. The digital clock data recovery device according to claim 10, wherein The first bit value is a high-order value, and the second bit value is a low-order value.
12. The digital clock data recovery device according to claim 10, wherein the digital clock data recovery device further includes a frequency divider that divides the data signal and the output signal of the digital control oscillator.
13. The digital clock data recovery device according to claim 12, wherein the frequency divider includes: a first frequency divider that divides the data signal; and a second frequency divider that divides the signal of the digital control oscillator.
14. The digital clock data recovery device according to claim 10, wherein the digital clock data recovery device further includes a parallelizer that is connected to the phase detector to output the recovered data.
15. The digital clock data recovery device according to claim 14, wherein the phase detector accumulates the number of phase differences between the data signal and the output of the digital control oscillator and outputs the result.