Manufacturing method of semiconductor device
By forming an isolated dielectric film with a tooth-like structure in the 3D NAND memory, the problem of increasing the thickness of the isolation dielectric film in the miniaturization of the memory cell is solved, the production cost and etching difficulty are reduced, and the performance and efficiency of the memory are improved.
Patent Information
- Application Number
- CN202410024756.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-08
- Publication Date
- 2025-07-08
AI Technical Summary
In the existing 3D NAND memory, as the memory cells are miniaturized, it is difficult to simultaneously reduce the parasitic capacitance and increase the storage density, and the increase in the thickness of the isolation dielectric film leads to increased production costs and etching difficulties.
By alternately stacking the dielectric layer and the conductor layer, etching forms grooves and transverse recesses, deposition of the isolation dielectric film, forming a tooth-like structure, ensuring effective isolation of the contact electrode and the word line conductor layer, and reducing the thickness of the isolation dielectric film, the film thickness is controlled by atomic layer deposition or chemical vapor deposition method.
Effective isolation distance is achieved, production costs and etching difficulty are reduced, while improving memory performance and production efficiency.
Smart Images
Figure CN120282452A_ABST
Abstract
Description
Technical Field
[0001] The present invention generally relates to the field of memory manufacturing, and more particularly, to a method for manufacturing a 3D NAND memory. Background Art
[0002] Memory is commonly used in integrated circuits to store data. Memory generally includes volatile memory and non-volatile memory. An example of non-volatile memory is flash memory, such as floating gate 3D NAND memory.
[0003] The size of the memory cell is continuously reduced to increase the net die of the storage device. As the size of the memory cell is miniaturized, it is necessary to reduce the parasitic capacitance Cb and increase the capacitance. However, due to the structural limitations of the memory cell, it is difficult to increase the net die. The density of the memory cell can be increased and the parasitic capacitance can be reduced by vertically stacking the memory cells. 3D NAND flash memory solves the limitations brought by 2D or planar NAND flash memory by vertically stacking multiple layers of data storage cells. This technology can support higher storage capacity in a smaller space, thereby bringing great cost savings, reduced power consumption, and significant performance improvement to fully meet the requirements of many consumer mobile devices and the most demanding enterprise deployments.
[0004] For 3D NAND memory technology, it is common to use a structure in which OPOP (i.e., polysilicon (poly) and oxide (oxide), or ONON (i.e., nitride (nitride) and oxide) are sequentially stacked, for example, silicon oxide / polysilicon / silicon oxide / polysilicon structure, or silicon oxide / silicon nitride / silicon oxide / silicon nitride structure), and the number of stacked layers will be increasing. Summary of the Invention
[0005] The present invention provides a method for manufacturing a semiconductor device, the method comprising: alternately stacking a plurality of dielectric layers and a plurality of conductor layers to form a stack; performing a through-tier etch on the stack along the stacking direction of the stack, the etch stopping at the adjacent dielectric layer above the target conductor layer to form a groove; etching the conductor layer located within the sidewall of the groove to form a lateral recess; depositing an isolation dielectric film on the upper surface of the stack, the inner wall of the groove, and the surface of the lateral recess; etching (punch) the isolation dielectric film at the bottom of the groove and the adjacent dielectric layer above the target conductor layer along the stacking direction of the stack to expose the target conductor layer; depositing metal into the groove to form a contact electrode coupled to the target conductor layer.
[0006] In some preferred embodiments, the semiconductor device is a 3D NAND memory.
[0007] In some preferred embodiments, the conductor layer is a word line conductor layer.
[0008] In some preferred embodiments, the word line conductor layer is polysilicon or nitride.
[0009] In some preferred embodiments, the stack is etched using dry etching along the stacking direction of the stack.
[0010] In some preferred embodiments, the height of the lateral recess is 20 - 60 nm, and the depth is 50 - 100 nm.
[0011] In some preferred embodiments, the conductor layer located within the sidewall of the groove is etched using wet etching or vapor etching.
[0012] In some preferred embodiments, the thickness of the isolation dielectric film is 10 - 50 nm.
[0013] In some preferred embodiments, the material of the isolation dielectric film is silicon oxide, silicon nitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or a combination thereof.
[0014] In some preferred embodiments, the isolation dielectric film is deposited using atomic layer deposition or chemical vapor deposition.
[0015] Using the memory manufacturing method of the present invention, a serrated isolation dielectric film is formed, which not only ensures an effective isolation distance between the contact electrode and the word line conductor, but also reduces the thickness of the isolation dielectric film on the sidewall and bottom of the groove, thereby reducing the production cost during the deposition process of the isolation dielectric film; at the same time, since the isolation dielectric film at the bottom of the groove is thinner, the difficulty of the subsequent dielectric etching process is significantly reduced, and the overall production cost of the 3D NAND memory is reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The drawings are merely exemplary and do not limit the embodiments. In the drawings, the same reference numerals represent the same parts in each figure and embodiment of the present invention, where:
[0017] Figure 1A -E shows the process method of forming a memory cell according to the method of the first embodiment of the present invention;
[0018] Figure 2A -F shows the process method of forming a memory cell according to the method of the second embodiment of the present invention;
[0019] Figure 3 is a TEM image of the cross-section of a semiconductor device obtained by the method of the second embodiment of the present invention.
[0020] Description of Reference Numerals
[0021] 100 and 100' stack; 101 and 101' dielectric layer; 102 and 102' word line conductor layer; 102c and 102c' target word line conductor layer; 111 and 111' groove; 112 and 112' lateral recess; 201 and 201' isolation dielectric film; 301 and 301' contact electrode
[0022] It should be understood that, for the sake of simplicity and / or clarity of illustration, the elements shown in the drawings are not necessarily drawn to scale. For example, for the sake of clarity, the sizes of some elements may be exaggerated relative to other elements to clearly illustrate certain features of the described examples or implementations. In addition, in order to make the concept of the present invention easier to understand, elements known in the art are omitted in the drawings. The dimensions of the drawings do not represent the exact dimensions and / or dimensional ratios of the various elements depicted herein. DETAILED DESCRIPTION
[0023] In the following description, several specific details are set forth. However, the embodiments described herein can be implemented without certain specific details. In specific embodiments, in order to avoid unclear understanding of the specification, well-known structures and technologies are not shown in detail.
[0024] When presenting a specific example with two or more layers in a multi-layer structure in a figure or description, the relative positioning relationship of these layers or the order in which the layers are arranged as shown reflects the specific implementation of the example described or shown, and different relative positioning relationships or orders of arranged layers are possible.
[0025] The present invention provides a method for manufacturing a semiconductor device. It should be understood that in order not to overwhelm the technical concept of the present invention, many descriptions of well-known structures and / or process steps are omitted. The embodiments described below are exemplary and are only used to explain the present invention, and should not be understood as limiting the present invention. If no specific technology or conditions are specified in the embodiments, the technology or conditions described in the literature in the field or the product manual shall be followed.
[0026] In the first embodiment, the dielectric layer 101' and the word line conductor layer 102' are stacked to form a stacked body 100'. Figure 1A As shown. In this article, the conductor layer is usually a word line conductor layer (WL conductor). The stack 100' is subjected to a through-layer etching process to form a groove 111', such as Figure 1B An isolation dielectric film 201' with a thickness of h0' is deposited on the interface between the upper surface of the stack 100' and the inner wall of the groove 111' to isolate the word line contact from other word line conductor layers. Figure 1CAs shown. The isolation dielectric film 201' mainly serves to ensure that the stacked memory cells can withstand subsequent etching processes (punch process), while achieving good isolation between word lines to withstand the voltage difference formed between subsequent word lines and contact electrodes, and can reduce the capacitance between the word line contacts and the surrounding multi-layer stacked structures. Therefore, the isolation dielectric film needs to have a sufficient thickness, and its thickness is generally not less than 100 nm. Next, an etching process is used to etch the isolation dielectric film 201' in the groove 111' and the dielectric layer 101c' adjacent above the target word line conductor layer 102c' to expose the target word line conductor layer 102c', as Figure 1D shown. Finally, metal is deposited into the groove to form the contact electrode 301' and is coupled to the exposed target word line conductor layer 102c', as Figure 1E shown in the structure of.
[0027] It is known that the isolation dielectric film is generally generated through a deposition process. Therefore, as the deposited thickness increases, the production cost increases. Considering that the etching process has relatively high selectivity requirements for the materials between the isolation dielectric film and different layers of the multi-layer stack, when the isolation dielectric film thickens, it brings pressure to the etching process.
[0028] In some embodiments, the semiconductor device is a 3D NAND memory.
[0029] In the second embodiment, the dielectric layer 101 and the word line conductor layer 102 are stacked to form a stack 100. Figure 2A The figure shows a schematic structural diagram of a stack 100 formed by alternately stacking a plurality of dielectric layers 101 and a plurality of word line conductor layers 102. In this article, the conductor layer is usually a word line conductor layer (WL conductor). Figure 2A As shown, the stack 100 includes a stacked structure formed by alternately laminating dielectric layers 101a, 101b, 101c, 101d and word line conductor (WL conductor) layers 102a, 102b, 102c. Although not clearly shown in the figure, as understood by those skilled in the art, a plurality of memory cells and associated circuit elements can be formed in the word line conductor layers 102a, 102b, 102c, such as silicon-based word line segments, floating gates, control gates, non-silicon metal word line segments, etc. However, it should be understood that although Figure 2A shows 4 dielectric layers and 3 word line conductor layers, this is only for illustration, and there can be more or fewer dielectric layers and word line conductor layers in an actual memory.
[0030] In some embodiments, the thickness of the dielectric layer 101 may be 10 to 50 nm, and the thickness of each dielectric layer 101 may be the same or different from each other. A thickness of the dielectric layer 101 within a suitable range can ensure effective isolation between the word line conductors and prevent current breakdown. However, when the dielectric layer is thick, the resulting final memory structure is too thick, which also increases the process difficulty of etching. In some embodiments, the thickness of the word line conductor layer 102 may be 20 to 60 nm, and the thickness of each word line conductor layer 102 may be the same or different from each other. When the thickness of the word line conductor layer 102 is too large, the etching difficulty increases; while when the thickness of the word line conductor layer 102 is too small, the height and volume of the corresponding storage unit are too small, resulting in insufficient performance of a single storage unit.
[0031] In some embodiments, the material of the dielectric layer 101 may include silicon oxide, silicon nitride, high-k materials, or a combination thereof. High-k materials may have a higher dielectric constant than silicon oxide. Silicon oxide (SiO2) may have a dielectric constant of about 3.9, and the dielectric layer 101 may include high-k materials having a dielectric constant of about 4 or greater. High-k materials may have a dielectric constant of about 20 or greater. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). In some embodiments, the dielectric layer 101 may be formed of a composite layer including two or more layers of the above high-k materials. In some preferred embodiments, the material of the dielectric layer 101 may be silicon dioxide.
[0032] In some embodiments, the material of the word line conductor layer 102 may include semiconductor materials. The word line conductor layer 102 may include titanium nitride, tungsten, single-crystalline silicon, polycrystalline silicon, or a combination thereof. The word line conductor layer 102 may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or greater. In some preferred embodiments, the material of the word line conductor layer 102 may be polycrystalline silicon.
[0033] Next, with reference to Figure 2B -F, a process method for forming a storage unit according to the method of the present invention will be described.
[0034] In forming as Figure 2AAfter the structure of the stack 100 shown, along the stacking direction of the stack 100, the stack is etched (through - tier etch), and the etching stops at the dielectric layer 101c above the target word - line conductor layer 102c, forming a groove 111, as Figure 2B shown. The selection of the target word - line conductor layer 102c is illustrative only. For the actual manufacturing process of the memory, the specific etching depth can be determined according to the memory design structure and stopped at the corresponding word - line conductor layer. The etching method can generally be dry etching commonly used by those skilled in the art. Since this method has a high selectivity and high anisotropy, the required groove 111 can be formed by controlling the etching conditions.
[0035] Then, as Figure 2C shown, the word - line conductor layers 102a and 102b located inside the sidewalls of the groove 111 are etched to form a lateral recess 112. The etching method usually selected is wet etching or vapor etching. By using the high selectivity and isotropic property of wet etching or vapor etching, the etching can penetrate deeply into the word - line conductor layer horizontally. And the etching process can be controlled by adjusting the etching conditions and etching time, etc., so as to obtain a lateral recess 112 with a relatively uniform depth. In some embodiments, the etching solution can be, for example, a 10% concentration of tetramethylammonium hydroxide (TMAH) solution, and the etching time can be, for example, 60s. In some embodiments, the height (h r ) of the lateral recess 112 can be 20 - 60 nm, and the depth (d) can be 50 - 100 nm. When the depth of the groove is too shallow, it cannot ensure an effective isolation distance between the contact electrode 301 and the word - line conductor layer 102, thus it cannot effectively prevent a short - circuit between the contact electrode 301 and the word - line conductor layer 102 during the subsequent process. When the depth of the groove is too deep, it increases the difficulty of the etching process flow. In addition, those skilled in the art can understand that the depths of the formed lateral recesses 112 are basically the same.
[0036] Next, by depositing on the upper surface of the stack 100, the inner wall of the groove 111, and the surface of the lateral recess 112, a toothed isolation dielectric film 201 with a certain thickness is formed, as Figure 2D shown. Through the deposition, the lateral recess 112 is completely filled, and a uniform isolation dielectric film 201 with a thickness of 10 - 50 nm can be formed on the sidewalls and bottom of the groove 111. The thickness of the isolation dielectric film 201 is h0, and the depth of the lateral recess 112 is d. Therefore, the effective isolation distance between the word - line conductor layer 102 and the contact electrode 301 is h e and then h e= h0 + d. Since in the subsequent etching process, in addition to etching the isolation dielectric layer 201 at the bottom of the groove 111, it is inevitable that the isolation dielectric layer 201 within the sidewall of the groove 111 will also be etched. When the thickness (h0) of the isolation dielectric film 201 is relatively thin, for example, when h0 < 20 nm, the isolation dielectric layer 201 within the sidewall becomes thinner or even is completely consumed, unable to ensure a sufficient effective isolation distance (h e ), which will cause a short circuit between the word line conductor layer 102 and the contact electrode 301, and the capacitance between the contact electrode 301 and the surrounding multi-layer stacked structure is too high. When the thickness of the isolation dielectric film 201 is too thick, for example, when h0 > 50 nm, it increases the cost of depositing the isolation dielectric film 201 and the difficulty of the subsequent etching process, increasing the manufacturing cost of the storage device. According to the technical solution of the present invention, the effective isolation distance (h e ) between the contact electrode 301 and the word line conductor layer 102 can be 80 - 150 nm. The deposition method can be selected as atomic layer deposition or chemical vapor deposition. Compared with other methods, the above methods are more likely to obtain a more uniform isolation dielectric film 201 material, and the thickness of the film can be controlled by deposition conditions and deposition time.
[0037] In some embodiments, the material of the isolation dielectric film 201 can be a commonly used dielectric material in semiconductors, such as silicon oxide, silicon nitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or a combination thereof.
[0038] After forming the isolation dielectric film 201, along the stacking direction of the stack 100, the isolation dielectric film 201 at the bottom of the groove 111 and the dielectric layer 101c above the target word line conductor layer 102c are etched, so that the target word line conductor layer 102c is exposed, as Figure 2E shown. The etching method is selected as an etching method commonly used by those skilled in the art. For example, a dry etching with a high selectivity can be used. In some embodiments, a dry etching process with a high bias voltage in a carbon fluoride environment is selected. This etching method has good selectivity with respect to the isolation dielectric film 201, the dielectric layer 101, and the word line conductor layer 102.
[0039] Finally, a metal is deposited into the groove 111 to form the contact electrode 301, which is coupled to the target word line conductor layer 102c to form a structure as Figure 2F shown. The TEM image of the physical structure of the semiconductor device obtained by the method of the present invention is as Figure 3As shown. As is well known to those skilled in the art, when metal deposition is carried out inside the groove 111, metal deposition also occurs on the upper surface of the stack 100. Therefore, an operation of removing the deposited metal layer on the upper surface of the stack 100 is also included, and this operation can be achieved through conventional means such as CMP. In some embodiments, the material of the contact electrode 301 can be silicon material, copper material, aluminum material, tungsten material, etc. Silicon material has a high melting point, good thermal stability and mechanical strength, and is also easy to process and cut. Copper material has the advantages of high conductivity, high reliability, low resistivity, etc. The introduction of copper material can improve the speed and power of semiconductor devices, and also helps to reduce the chip size and power consumption. Aluminum material has poor conductivity, but has good corrosion resistance and stability, and the melting point of aluminum material is low, which is easy to process and weld. Tungsten material has good high-temperature resistance, corrosion resistance and stability, and can withstand high-power and high-frequency current and electromagnetic wave radiation.
[0040] Using the manufacturing method of the present invention, the isolation dielectric film 201 with a tooth-like structure is formed. The effective isolation distance between the contact electrode 301 and the word line conductor layer 102 is ensured at the thicker part of the tooth-like structure, avoiding short circuit between the contact electrode 301 and the word line conductor layer 102 due to the thinning of the isolation dielectric film 201 after etching. The thinner part of the tooth-like structure reduces the film thickness of the isolation dielectric film 201 on the sidewall and bottom of the groove 111, which not only reduces the production cost of the deposition process, but also reduces the difficulty of the subsequent etching process at the bottom of the groove 111, and reduces the overall production cost of the semiconductor device.
[0041] At the same time, the method for forming the storage unit of the 3D NAND memory of the present invention makes small changes to the entire process flow, so it is easy to implement, and thus the cost increase is very small.
[0042] In addition, it should be understood that although the above embodiments are described in the context of floating gate 3D NAND memories, they can also be used in the manufacturing processes of other 3D memories under appropriate circumstances.
[0043] In addition, ordinal adjectives such as "first", "second", "third", etc. may be used herein to refer to elements. Unless explicitly stated, this is only used to distinguish different elements and does not imply that the elements mentioned must be in a given order in terms of time, space, or otherwise.
[0044] In addition, it should be understood that although the present invention is described with respect to specific embodiments, those skilled in the art can modify one or more of its features after reading the specification without departing from the spirit and scope of the present invention. Therefore, this specification is not intended to limit the present invention. On the contrary, the scope of the present invention is defined only by the appended claims and their equivalents.
Claims
1. A method for manufacturing a semiconductor device, the method comprising: alternately stacking a plurality of dielectric layers and a plurality of conductor layers to form a stack; etching the stack along the stacking direction of the stack, and stopping the etching at an adjacent dielectric layer above a target conductor layer among the plurality of conductor layers to form a groove; etching the conductor layer located within the sidewall of the groove to form a lateral recess; depositing an isolation dielectric film on the upper surface of the stack, the inner wall of the groove, and the surface of the lateral recess; etching the isolation dielectric film at the bottom of the groove and the adjacent dielectric layer above the target conductor layer along the stacking direction of the stack to expose the target conductor layer; depositing a metal into the groove to form a contact electrode coupled to the target conductor layer.
2. The method according to claim 1, wherein The semiconductor device is a 3D NAND memory.
3. The method according to claim 2, wherein The conductor layer is a word line conductor layer.
4. The method according to claim 3, wherein The word line conductor layer is polysilicon or nitride.
5. The method according to claim 1, wherein, Etching the stack along the stacking direction of the stack includes: etching the stack using dry etching.
6. The method according to claim 1, wherein, The height of the lateral recess is 20 - 60 nm, and the depth is 50 - 100 nm.
7. The method according to claim 1, wherein Etching the conductor layer located within the sidewall of the groove includes: etching the conductor layer located within the sidewall of the groove using wet etching or vapor etching.
8. The method according to claim 1, wherein The thickness of the isolation dielectric film is 10 - 50 nm.
9. The method according to claim 1, wherein, The material of the isolation dielectric film is silicon oxide, silicon nitride, aluminum oxide, metal oxide, metal oxynitride, metal silicate, high-k material, or a combination thereof.
10. The method according to claim 1, wherein, Depositing the isolation dielectric film includes: depositing the isolation dielectric film using atomic layer deposition or chemical vapor deposition.