Manufacturing method of semiconductor device

Abstract

The invention belongs to the technical field of semiconductor devices, and particularly discloses a manufacturing method of a semiconductor device, which comprises the following steps: forming a first insulating layer on an n-type semiconductor layer, and forming a first groove in the n-type semiconductor layer; forming a second insulating layer in the first groove; isotropically etching the first insulating layer to reduce the width of the first insulating layer; forming a second groove in the n-type semiconductor layer; forming an n-type charge storage region in the n-type semiconductor layer; forming a third insulating layer in the second groove; forming a first conductive layer and performing back etching, forming a shielding grid electrode in the first groove, and forming a grid electrode in the second groove; carrying out inclined ion implantation, and forming an n-type source region in the n-type semiconductor layer; and forming a second dielectric layer above the grid electrode and the shielding grid electrode, removing the first insulating layer, and performing ion implantation to form a p-type body region in the n-type semiconductor layer.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a manufacturing method of a semiconductor device. Background Art

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a device composed of a MOS transistor and a bipolar transistor. Its input terminal is a MOS transistor, and its output terminal is a PNP transistor. It combines the advantages of these two devices, having both the advantages of a MOS transistor with low drive power and fast switching speed, and the advantages of a bipolar transistor with low saturation voltage drop and large capacity. It has been increasingly widely used in modern power electronics technology, especially occupying the dominant position in the application of large and medium-power transistors with higher frequencies. In the manufacturing process of semiconductor devices in the prior art, multiple photolithography processes are required, and the cost of photolithography processes is high, making it difficult to reduce the manufacturing cost of semiconductor devices. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a manufacturing method of a semiconductor device to reduce the manufacturing cost of the semiconductor device.

[0004] To achieve the above object of the present invention, the present invention provides a manufacturing method of a semiconductor device, including:

[0005] S1: Form a first insulating layer on the provided n-type semiconductor layer, etch the first insulating layer and the n-type semiconductor layer, and form a first trench in the n-type semiconductor layer;

[0006] S2: Cover the inner surface of the first trench to form a second insulating layer;

[0007] S3: Perform isotropic etching on the first insulating layer to reduce the width of the first insulating layer, and then etch the n-type semiconductor layer to form a second trench in the n-type semiconductor layer;

[0008] S4: Perform ion implantation to form an n-type charge storage region below the second trench in the n-type semiconductor layer;

[0009] S5: Cover the inner surface of the second trench to form a third insulating layer;

[0010] S6: Form a first conductive layer and perform back etching. The upper surface of the remaining first conductive layer after etching is not higher than the upper surface of the second insulating layer. The remaining first conductive layer after etching forms a shielding gate in the first trench and a gate in the second trench;

[0011] S7: Perform inclined ion implantation to form an n-type source region within the n-type semiconductor layer;

[0012] S8: Form a second dielectric layer above the gate and the shielding gate, then remove the first insulating layer, and thereafter perform ion implantation to form a p-type body region within the n-type semiconductor layer.

[0013] Optionally, the material of the first insulating layer is different from the material of the second insulating layer.

[0014] Optionally, the material of the first insulating layer is silicon nitride, and the material of the second insulating layer is silicon oxide.

[0015] Optionally, the material of the first insulating layer is the same as the material of the second insulating layer.

[0016] Optionally, the materials of both the first insulating layer and the second insulating layer are silicon oxide.

[0017] Optionally, S2 includes: covering the inner surface of the first trench to form a second insulating layer, and thereafter forming a first dielectric layer within the first trench; S5 includes: removing the first dielectric layer, and covering the inner surface of the second trench to form a third insulating layer.

[0018] Optionally, the material of the first dielectric layer is photoresist.

[0019] Optionally, the material of the third insulating layer is silicon oxide.

[0020] Optionally, the material of the second dielectric layer is different from the material of the first insulating layer.

[0021] For the manufacturing method of the semiconductor device provided by the present invention, first, the n-type semiconductor layer is exposed by isotropically etching the first insulating layer, and the n-type semiconductor layer can be etched self-alignedly to form a second trench, avoiding the photolithography process; second, the shielding gate and the gate are manufactured and formed in the same process step, simplifying the manufacturing process; third, the n-type source region is formed by an inclined ion implantation process, which can also avoid the photolithography process. Thus, the present invention reduces the number of photolithography process times during the manufacturing process of the semiconductor device, effectively reducing the manufacturing cost of the semiconductor device. Brief Description of the Drawings

[0022] To more clearly illustrate the technical solutions of the exemplary embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments.

[0023] Figures 1 to 9 It is a schematic cross-sectional structure diagram of the main structure in the manufacturing process of an embodiment of the manufacturing method of the semiconductor device provided by the present invention. Detailed Description of the Embodiments

[0024] The technical solution of the present invention will be completely described below in a specific manner in combination with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. It should be understood that terms such as "having", "comprising", and "including" used in the present invention do not exclude the presence or addition of one or more other elements or combinations thereof. At the same time, for the sake of clearly illustrating the specific implementation manners of the present invention, the schematic diagrams listed in the accompanying drawings of the specification have enlarged the thicknesses of the layers and regions described in the present invention, and the sizes of the listed figures do not represent actual sizes.

[0025] Figures 1 to 9 It is a schematic cross-sectional structure diagram of the main structure in the manufacturing process of an embodiment of the manufacturing method of the semiconductor device provided by the present invention.

[0026] First, as Figure 1 shown, a first insulating layer 41 is formed on the provided n-type semiconductor layer 20. The first insulating layer 41 is usually silicon oxide or silicon nitride. The position of the first trench is defined by a lithography process, and then the first insulating layer 41 and the n-type semiconductor layer 20 are etched to form a plurality of first trenches 51 arranged in sequence in the n-type semiconductor layer 20. The material of the n-type semiconductor layer 20 is usually silicon. The number of the first trenches 51 is determined by specific device design. In the embodiment of the present invention, only two first trenches 51 are exemplarily shown.

[0027] Next, as Figure 2 shown, a second insulating layer 21 is formed to cover the inner surface of the first trench. Then, a first dielectric layer 22 is formed in the first trench, and the upper surface and side surfaces of the first insulating layer 41 are exposed. The material of the second insulating layer 21 is usually silicon oxide, and it is formed by a thermal oxidation or deposition process. The material of the second insulating layer 21 and the material of the first insulating layer 41 may be the same or different. In this embodiment, taking the case where the material of the second insulating layer 21 and the material of the first insulating layer 41 are the same as an example, at this time, a first dielectric layer 22 needs to be formed in the first trench to protect the second insulating layer 21, so that when the first insulating layer 41 is isotropically etched subsequently, the second insulating layer 21 is protected from being etched away. At this time, the material of the first dielectric layer 22 is different from the materials of the first insulating layer 41 and the second insulating layer 21. The material of the first dielectric layer 22 is, for example, photoresist. The first trench is filled with photoresist by a spin coating process, and then the photoresist outside the first trench is removed.

[0028] It should be noted that if the material of the second insulating layer 21 and the material of the first insulating layer 41 are different, the first dielectric layer 22 may not be formed. For example, the material of the first insulating layer 41 may be silicon nitride, and the material of the second insulating layer 21 may be silicon oxide.

[0029] Next, as Figure 3 shown, isotropic etching is performed on the first insulating layer 41 to reduce the width of the first insulating layer 41, exposing a part of the surface of the n-type semiconductor layer 20 on both sides of the first trench. At this time, the thickness of the first insulating layer 41 will also be etched and reduced. At this time, a part of the second insulating layer 21 will also be etched off, as Figure 3 shown. It should be noted that the reason why a part of the second insulating layer 21 is also etched off is that the material of the second insulating layer 21 is the same as that of the first insulating layer 41. Therefore, when isotropic etching is performed on the first insulating layer 41, a part of the second insulating layer 21 will also be etched off. When the material of the second insulating layer 21 is different from that of the first insulating layer 41, the second insulating layer 21 may not be etched.

[0030] Next, as Figure 4 shown, the n-type semiconductor layer 20 is etched to form a second trench 52 in the n-type semiconductor layer 20. It can be understood that etching the n-type semiconductor layer 20 here specifically refers to etching the n-type semiconductor layer 20 exposed after etching the first insulating layer 41, or etching the n-type semiconductor layer 20 between the first insulating layer 41 and the second insulating layer 21. When etching the n-type semiconductor layer 20, the first insulating layer 41, the second insulating layer 21, and the first dielectric layer 22 act as masks, so that the second trench 52 is located on both sides of the first trench. The second trench 52 serves as a gate trench, and its bottom is higher than the bottom of the first trench. In this etching process, the second trench 52 is formed by self-aligned etching, reducing a photolithography process step.

[0031] Next, as Figure 5 shown, ion implantation is performed to form an n-type charge storage region 23 in the n-type semiconductor layer 20 below the second trench 52.

[0032] Next, as Figure 6 shown, the first dielectric layer is removed, and then a third insulating layer 24 is formed to cover the inner surface of the second trench 52. The third insulating layer 24 serves as a gate dielectric layer, usually silicon oxide formed by a thermal oxidation process.

[0033] Next, as Figure 7As shown, a first conductive layer is formed. The first conductive layer should fill the first trench and the second trench, and then the formed first conductive layer is etched back. The upper surface of the remaining first conductive layer after etching is not higher than the upper surface of the second insulating layer 21. Thus, the remaining first conductive layer after etching forms a shielding gate 26 in the first trench and a gate 25 in the second trench. That is, after etching, the first conductive layer in the first trench forms the shielding gate 26, and the first conductive layer in the second trench forms the gate 25. Since the upper surface of the remaining first conductive layer after etching is not higher than the upper surface of the second insulating layer 21, the shielding gate 26 and the gate 25 are separated by the second insulating layer 21. The shielding gate 26 and the gate 25 are fabricated in the same process step, simplifying the manufacturing process of the semiconductor device.

[0034] Next, as Figure 8 shown, an inclined ion implantation is performed to form an n-type source region 28 in the n-type semiconductor layer 20. The n-type source region 28 is directly formed by the inclined ion implantation, reducing one photolithography process step. At the same time, by etching back the first conductive layer, the upper surface of the gate 25 is lower than the upper surface of the n-type semiconductor layer 20, which can leave enough implantation space for the inclined ion implantation, making it easier to form the n-type source region 28.

[0035] Next, as Figure 9 shown, a second dielectric layer 51 is formed above the gate 25 and the shielding gate 26, and then the first insulating layer is removed. After that, an ion implantation is performed to form a p-type body region 27 in the n-type semiconductor layer 20. The material of the second dielectric layer 51 should be different from that of the first insulating layer. For example, the material of the second dielectric layer 51 is photoresist, or when the material of the first insulating layer is silicon oxide, the material of the second dielectric layer 51 is silicon nitride.

[0036] Finally, a semiconductor device can be formed by conventional processes. For example, it includes: forming an interlayer insulating layer, as well as source metal and gate metal on the surface of the n-type semiconductor layer; forming an n-type field stop region and a p-type collector region at the bottom of the n-type semiconductor layer; forming collector metal on the bottom surface of the n-type semiconductor layer. These processes are all conventional manufacturing processes in the industry and will not be specifically introduced in the embodiments of the present invention.

[0037] The above specific embodiments and examples are specific supports for the technical idea of the present invention, and the protection scope of the present invention cannot be limited thereby. Any equivalent change or equivalent modification made on the basis of this technical solution according to the technical idea proposed by the present invention still belongs to the protection scope of the technical solution of the present invention.

Claims

1. A method of manufacturing a semiconductor device, characterized in that, Including: S1: Form a first insulating layer on the provided n-type semiconductor layer, etch the first insulating layer and the n-type semiconductor layer, and form a first trench in the n-type semiconductor layer; S2: Cover the inner surface of the first trench to form a second insulating layer; S3: Isotropically etch the first insulating layer to reduce the width of the first insulating layer, and then etch the n-type semiconductor layer to form a second trench in the n-type semiconductor layer; S4: Perform ion implantation to form an n-type charge storage region in the n-type semiconductor layer below the second trench; S5: Cover the inner surface of the second trench to form a third insulating layer; S6: Form a first conductive layer and perform back etching. The upper surface of the remaining first conductive layer after etching is not higher than the upper surface of the second insulating layer. The remaining first conductive layer after etching forms a shielding gate in the first trench and a gate in the second trench; S7: Perform inclined ion implantation to form an n-type source region in the n-type semiconductor layer; S8: Form a second dielectric layer above the gate and the shielding gate, then remove the first insulating layer, and then perform ion implantation to form a p-type body region in the n-type semiconductor layer.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The materials of the first insulating layer and the second insulating layer are different.

3. The manufacturing method of the semiconductor device according to claim 2, wherein, The material of the first insulating layer is silicon nitride, and the material of the second insulating layer is silicon oxide.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The materials of the first insulating layer and the second insulating layer are the same.

5. The manufacturing method of the semiconductor device according to claim 4, characterized in that, The materials of both the first insulating layer and the second insulating layer are silicon oxide.

6. The manufacturing method of the semiconductor device according to claim 4, characterized in that, S2 includes: Cover the inner surface of the first trench to form a second insulating layer, and then form a first dielectric layer in the first trench; S5 includes: Remove the first dielectric layer and cover the inner surface of the second trench to form a third insulating layer.

7. The manufacturing method of the semiconductor device according to claim 6, characterized in that, The material of the first dielectric layer is photoresist.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The material of the third insulating layer is silicon oxide.

9. The manufacturing method of the semiconductor device according to claim 1, wherein, The material of the second dielectric layer is different from the material of the first insulating layer.

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