Manufacturing method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure, which comprises the following steps of: growing a first semiconductor layer on a substrate, etching a groove in one side, far away from the substrate, of the first semiconductor layer, partially penetrating through the first semiconductor layer, growing a sacrificial layer on the first semiconductor layer, etching the sacrificial layer, and repeating the growth and the etching of the sacrificial layer for multiple times, and carrying out secondary epitaxy on a third semiconductor layer in the groove until the ion concentration of the surface of the first semiconductor layer exposed by the groove is lower than a preset value. Through the method of etching the sacrificial layer after growing the sacrificial layer for multiple times, on one hand, the ion concentration of the first conduction type on the surface of the first semiconductor layer exposed by the groove can be reduced, so that the third semiconductor layer of the second conduction type can be grown in the groove, and the lattice quality of the third semiconductor layer is improved; on the other hand, the impurity ion concentration in the growth cavity of the third semiconductor layer can be reduced, the quality of the third semiconductor layer is further improved, and the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and particularly to a manufacturing method of a semiconductor structure. Background Art

[0002] Currently, the mainstream commercial applications of gallium nitride devices are mainly lateral devices prepared by heteroepitaxy on substrates such as silicon, silicon carbide, and sapphire. However, due to reliability and dynamic problems faced by lateral devices based on heteroepitaxial substrates, they are greatly limited in high-voltage and high-power power electronics applications. The most important disadvantage of lateral devices is that the breakdown voltage of the device is proportional to the distance between the electrodes, resulting in a larger device size required in high-voltage operating scenarios, increasing the overall complexity and process preparation cost of high-voltage and high-power devices.

[0003] Vertical structure devices can increase the distance in the vertical direction by increasing the thickness of the epitaxial layer to improve the device withstand voltage level without increasing the device size, thereby achieving high-speed and high-current output. However, there are unreliable problems in the PN junctions of vertical structure devices. The unreliable PN junctions are easily broken down, resulting in leakage. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a manufacturing method of a semiconductor structure to improve the reliability of the PN junctions of vertical structure devices.

[0005] According to one aspect of the present disclosure, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, characterized by including the following steps:

[0006] S1. Provide a substrate of a first conductivity type;

[0007] S2. Grow a first semiconductor layer of a first conductivity type on the substrate, and the substrate has a doping concentration higher than that of the first semiconductor layer;

[0008] S3. Etch a trench on a side of the first semiconductor layer away from the substrate, and the trench partially penetrates the first semiconductor layer;

[0009] S4. Grow a sacrificial layer on the first semiconductor layer;

[0010] S5. Etch the sacrificial layer;

[0011] S6. Secondarily epitaxially grow a third semiconductor layer of a second conductivity type in the trench;

[0012] Wherein, before entering step S6, steps S4 and S5 are repeated N times until the ion concentration on the surface of the first semiconductor layer exposed by the trench is lower than a preset value.

[0013] As an alternative embodiment, the method for etching the trench in step S3 is in-situ etching.

[0014] As an alternative embodiment, the in-situ etching is dry etching.

[0015] As an alternative embodiment, the gas environment for etching includes one or a combination of more of Cl2, H2, HCl, and TBCl.

[0016] As an alternative embodiment, after the in-situ etching to form the trench in step S3, it further includes:

[0017] Etching the trench a second time to etch and form a plurality of V-grooves or hexagonal prisms arranged at intervals on the bottom surface of the trench.

[0018] As an alternative embodiment, the material of the sacrificial layer includes one or a combination of more of AlN, InN, InGaN, InAlN, InAlGaN, and GaN.

[0019] As an alternative embodiment, the sacrificial layer is an unintentionally doped layer.

[0020] As an alternative embodiment, the sacrificial layer is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer.

[0021] As an alternative embodiment, the sacrificial layer conformally grows on the first semiconductor layer, or, the surface of the sacrificial layer on the side away from the substrate is a plane.

[0022] As an alternative embodiment, the method for etching the sacrificial layer in step S5 is in-situ etching.

[0023] As an alternative embodiment, the ion doping concentration of the first semiconductor layer is greater than 1E17 / cm 3 .

[0024] As an alternative embodiment, the preset value is 1E15 / cm 3 .

[0025] As an alternative embodiment, the method for secondary epitaxy of the third semiconductor layer is in-situ doped selective epitaxy.

[0026] As an alternative embodiment, after step S2, it further includes:

[0027] S21. Forming a second semiconductor layer of a first conductivity type on the first semiconductor layer, and the second semiconductor layer has a doping concentration higher than that of the first semiconductor layer.

[0028] As an alternative embodiment, the method for forming the second semiconductor layer is epitaxial growth or ion implantation.

[0029] As an alternative embodiment, step S3 further includes etching a trench on a side of the second semiconductor layer away from the substrate, the trench penetrating through the second semiconductor layer and partially penetrating the first semiconductor layer.

[0030] As an alternative embodiment, step S6 further includes:

[0031] S61. Secondarily epitaxially growing a third semiconductor layer of a second conductivity type in the trench, the thickness of the third semiconductor layer being greater than the depth of the trench.

[0032] S62. Using chemical mechanical polishing to remove the excess third semiconductor layer on the surface of the second semiconductor layer and planarize the surface of the second semiconductor layer.

[0033] As an alternative embodiment, after step S6, it further includes:

[0034] S7. Forming a source electrode, a drain electrode, and a gate electrode, the source electrode being located on a surface of the first semiconductor layer away from the substrate, the drain electrode being located on a surface of the substrate away from the first semiconductor layer, and the gate electrode being located on a surface of the third semiconductor layer away from the substrate.

[0035] The present disclosure provides a method for manufacturing a semiconductor structure. The present disclosure grows a first semiconductor layer on a substrate, etches a trench on a side of the first semiconductor layer away from the substrate, the trench partially penetrating the first semiconductor layer, grows a sacrificial layer on the first semiconductor layer and then etches the sacrificial layer, repeats the growth and etching of the sacrificial layer multiple times until the ion concentration on the surface of the first semiconductor layer exposed by the trench is lower than a preset value, and secondarily epitaxially grows a third semiconductor layer in the trench.

[0036] By the method of growing and etching the sacrificial layer multiple times, on the one hand, the ion concentration of the first conductivity type on the surface of the first semiconductor layer exposed by the trench can be reduced, which is beneficial to growing the third semiconductor layer of the second conductivity type in the trench and improving the lattice quality of the third semiconductor layer. On the other hand, the impurity ion concentration in the growth cavity of the third semiconductor layer can be reduced, further improving the quality of the third semiconductor layer, thereby improving the reliability of the semiconductor structure.

[0037] The third semiconductor layer of the present disclosure is formed by the method of in-situ doping selective epitaxy, which avoids the lattice damage to the first semiconductor layer caused by the ion implantation method and avoids the inaccuracy of the width of the third semiconductor layer caused by the diffusion effect of the ion implantation method, thereby improving the width accuracy of the channel between the third semiconductor layers and improving the reliability of the semiconductor structure. Description of the Drawings

[0038] Figure 1The figure shows a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0039] Figures 2 to 12 As shown Figure 1 The figure shows a schematic diagram of an intermediate structure corresponding to the shown process.

[0040] Figure 13 The figure shows a schematic diagram of the structure of a semiconductor structure provided by an embodiment of the present disclosure. Detailed implementation manners

[0041] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present disclosure without creative efforts shall fall within the protection scope of the present disclosure.

[0042] To improve the reliability of the PN junction of a vertical structure device, the present disclosure provides a method for manufacturing a semiconductor structure. A first semiconductor layer is grown on a substrate, trenches are etched on a side of the first semiconductor layer away from the substrate, and the trenches partially penetrate the first semiconductor layer. After a sacrificial layer is grown on the first semiconductor layer, the sacrificial layer is etched, and the growth and etching of the sacrificial layer are repeated multiple times until the ion concentration on the surface of the first semiconductor layer exposed by the trenches is lower than a preset value. A third semiconductor layer is secondarily epitaxially grown in the trenches. By the method of growing the sacrificial layer and then etching the sacrificial layer multiple times, on the one hand, the ion concentration of the first conductivity type on the surface of the first semiconductor layer exposed by the trenches can be reduced, which is beneficial to growing a third semiconductor layer of the second conductivity type in the trenches and improving the lattice quality of the third semiconductor layer. On the other hand, the impurity ion concentration in the growth cavity of the third semiconductor layer can be reduced, further improving the quality of the third semiconductor layer, thereby improving the reliability of the semiconductor structure.

[0043] Next, in combination with Figures 1 to 13 A method for manufacturing a semiconductor structure mentioned in the present disclosure is further illustrated by way of example.

[0044] Figure 1 The figure shows a flowchart of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure; Figures 2 to 12 As shown Figure 1 The figure shows a schematic diagram of an intermediate structure corresponding to the shown process. As Figure 1 shown, a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure includes the following steps:

[0045] Step S1: Provide a substrate of the first conductivity type.

[0046] Specifically, as Figure 2As shown, a substrate 10 of a first conductivity type is provided. The material of the substrate 10 includes any one or a combination of Si, Al2O3, GaN, SiC, or AlN. The present disclosure does not make specific limitations.

[0047] Step S2: Grow a first semiconductor layer of a first conductivity type on the substrate. The substrate has a doping concentration higher than that of the first semiconductor layer.

[0048] Specifically, as Figure 3 shown, grow a first semiconductor layer 20 of a first conductivity type on the substrate 10. The substrate 10 has a doping concentration higher than that of the first semiconductor layer 20. The substrate 10 having a higher doping concentration is beneficial to reducing the contact resistance with the electrodes prepared subsequently.

[0049] Step S3: Etch trenches on the side of the first semiconductor layer away from the substrate. The trenches partially penetrate the first semiconductor layer.

[0050] Specifically, as Figure 4 shown, etch trenches 31 on the side of the first semiconductor layer 20 away from the substrate 10. The trenches 31 partially penetrate the first semiconductor layer 20. The depth of the trenches 31 is 0.1 - 2 μm, and the spacing between two adjacent trenches 31 is 0.1 - 1 μm. By controlling the spacing between two adjacent trenches 31, the channel width of the semiconductor structure can be controlled. The width of the trenches 31 can remain unchanged, gradually increase, or gradually decrease in the direction away from the substrate 10. By controlling the width of the trenches 31, the width of the third semiconductor layer 40 grown in the trenches 31 subsequently can be controlled. The method of etching the trenches 31 is in-situ etching. The in-situ etching method is dry etching, and the etching gas environment includes one or a combination of Cl2, H2, HCl, and TBCl. The in-situ etching method does not introduce impurities, can reduce the interface state density, and is beneficial to reducing the current collapse effect of the device prepared subsequently and reducing the leakage current. Optionally, after the trenches 31 are formed by in-situ etching, the trenches 31 are etched twice to etch and form a plurality of V-shaped pits (as Figure 5 shown) or hexagonal prisms (as Figure 6 shown) arranged at intervals on the bottom surface of the trenches 31 to form a situation with crystal planes, such as (1 - 100) crystal plane or (11 - 20) crystal plane, which can further improve the crystal quality of the material of the third semiconductor layer grown in the trenches 31. Optionally, as Figure 7 shown, the trenches 31 can be etched twice to form a bottom rounded corner structure. The bottom rounded corner structure of the trenches 31 reduces the electric field strength at the bottom of the trenches 31, thereby increasing the breakdown voltage.

[0051] Step S4: Grow a sacrificial layer on the first semiconductor layer.

[0052] Specifically, grow a sacrificial layer 50 on the first semiconductor layer 20. As Figure 8As shown, the sacrificial layer 50 conformally grows on the first semiconductor layer 20; as Figure 9 shown, the surface of the sacrificial layer 50 on the side away from the substrate 10 is a plane. The material of the sacrificial layer 50 includes one or a combination of more of AlN, InN, InGaN, InAlN, InAlGaN, and GaN. The sacrificial layer 50 is an unintentionally doped layer. Ions on the surface of the first semiconductor layer 20 exposed by the trench 31 will diffuse into the sacrificial layer 50, and impurity elements in the epitaxial cavity can also diffuse into the sacrificial layer 50, thereby reducing the ion concentration on the surface of the first semiconductor layer 20 exposed by the trench 31 and the impurity elements in the epitaxial cavity. Optionally, the sacrificial layer 50 is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer. Further, the carbon doping, iron doping, or iron-carbon co-doping of the sacrificial layer 50 is a graded doping. Doping iron or carbon in the sacrificial layer 50 can form deep-level traps, thereby providing recombination centers, which can capture holes or electrons, thereby reducing the ion concentration on the surface of the first semiconductor layer 20 exposed by the trench 31 and at the same time reducing the impurity element concentration in the epitaxial cavity.

[0053] Step S5: Etch the sacrificial layer.

[0054] Specifically, etch the sacrificial layer 50 to form an intermediate structure as shown in Figure 4 shown. The method for etching the sacrificial layer 50 is in-situ etching. The in-situ etching method will not introduce impurities, can reduce the interface state density, and is beneficial to reducing the current collapse effect of the subsequently prepared device and reducing the leakage current.

[0055] Repeat steps S4 and S5 N times until the ion concentration on the surface of the first semiconductor layer 20 exposed by the trench 31 is lower than a preset value. The ion doping concentration of the first semiconductor layer 20 is greater than 1E17 / cm 3 , and the preset value is 1E15 / cm 3 , that is, by the method of growing the sacrificial layer 50 multiple times and then etching the sacrificial layer 50, the ion concentration on the surface of the first semiconductor layer 20 exposed by the trench 31 can be reduced by at least two orders of magnitude. The method of growing the sacrificial layer 50 multiple times and then etching the sacrificial layer 50 can, on the one hand, reduce the ion concentration of the first conductivity type on the surface of the first semiconductor layer 20 exposed by the trench 31, which is beneficial to subsequently growing the third semiconductor layer 40 of the second conductivity type in the trench 31 and improving the lattice quality of the third semiconductor layer 40. On the other hand, it can reduce the impurity ion concentration in the growth cavity of the third semiconductor layer 40, further improve the quality of the third semiconductor layer 40, and thus improve the reliability of the semiconductor structure.

[0056] Step S6: Secondarily epitaxially grow the third semiconductor layer of the second conductivity type in the trench.

[0057] Specifically, as shown in Figure 10As shown, a third semiconductor layer 40 of a second conductivity type is epitaxially grown for a second time in the trench 31. The method for epitaxially growing the third semiconductor layer 40 for the second time is in-situ doped selective epitaxy, which avoids the lattice damage to the first semiconductor layer 20 caused by the ion implantation method and the inaccuracy of the width of the third semiconductor layer 40 caused by the diffusion effect of the ion implantation method, thereby improving the width accuracy of the channel between the third semiconductor layers 40 and improving the reliability of the semiconductor structure.

[0058] In one embodiment, along the direction from the substrate 10 to the third semiconductor layer 40, the doping concentration of the third semiconductor layer 40 changes in a periodic manner, gradually increases, gradually decreases, first increases and then decreases, or first decreases and then increases. The doping concentration of the third semiconductor layer 40 is controlled by the in-situ doped selective epitaxy process to locally modulate the carrier concentration in the first semiconductor layer 20, that is, to modulate the carrier concentration in the channel. The function of the locally modulated carrier concentration is as follows: in the off state, the change in the doping concentration of multiple sub-layers of the third semiconductor layer 40 can increase the depletion layer width and reduce the peak electric field, thereby increasing the breakdown voltage; in the on state, this structure has the characteristic of reducing the on-resistance, enabling the semiconductor structure to have a lower voltage drop under the condition of high current density when it is turned on.

[0059] In one embodiment, step S6 further includes: step S61: epitaxially grow a third semiconductor layer of a second conductivity type for a second time in the trench, and the thickness of the third semiconductor layer is greater than the depth of the trench. Step S62: use chemical mechanical polishing to remove the excess third semiconductor layer on the surface of the second semiconductor layer and planarize the surface of the second semiconductor layer.

[0060] Specifically, as Figure 11 shown, a third semiconductor layer 40 of a second conductivity type is epitaxially grown for a second time in the trench 31. The thickness of the third semiconductor layer 40 is greater than the depth of the trench 31. Use chemical mechanical polishing to remove the excess third semiconductor layer 40 on the surface of the second semiconductor layer 30 and planarize the surface of the second semiconductor layer 30 to form an intermediate structure as Figure 10 shown. Chemical mechanical polishing (CMP, Chemical Mechanical Polishing) can remove the excess third semiconductor layer 40 on the surface of the second semiconductor layer 30 and obtain a flat surface without scratches and impurity contamination. It is not necessary to grow while strictly controlling the thickness of the third semiconductor layer 40, and the surface quality of the semiconductor structure after chemical mechanical polishing is good.

[0061] Step S7: form a source electrode, a drain electrode, and a gate electrode. The source electrode is located on the surface of the first semiconductor layer away from the substrate, the drain electrode is located on the surface of the substrate away from the first semiconductor layer, and the gate electrode is located on the surface of the third semiconductor layer away from the substrate.

[0062] Specifically, a source electrode 61, a drain electrode 62, and a gate electrode 63 are formed. The source electrode 61 is located on the surface of the first semiconductor layer 20 away from the substrate 10, the drain electrode 62 is located on the surface of the substrate 10 away from the first semiconductor layer 20, and the gate electrode 63 is located on the surface of the third semiconductor layer 40 away from the substrate 10, forming a semiconductor structure as shown in Figure 12 the figure.

[0063] Figure 13 The following is a schematic structural diagram of a semiconductor structure provided by an embodiment of the present disclosure. In one embodiment, after step S2, step S21 is further included: forming a second semiconductor layer of a first conductivity type on the first semiconductor layer, and the second semiconductor layer has a doping concentration higher than that of the first semiconductor layer. Specifically, a second semiconductor layer 30 of a first conductivity type is formed on the first semiconductor layer 20, and the second semiconductor layer 30 has a doping concentration higher than that of the first semiconductor layer 20. Step S3 further includes etching a trench 31 on the side of the second semiconductor layer 30 away from the substrate 10. The trench 31 penetrates through the second semiconductor layer 30 and partially penetrates the first semiconductor layer 20. After manufacturing the source electrode 61, the drain electrode 62, and the gate electrode 63, a semiconductor structure as shown in Figure 13 the figure is formed. The method for forming the second semiconductor layer 30 is epitaxial growth or ion implantation, that is, the second semiconductor layer 30 can be epitaxially grown on the first semiconductor layer 20 or ions of the first conductivity type can be ion implanted on the surface of the first semiconductor layer 20 to form the second semiconductor layer 30. The second semiconductor layer 30 having a relatively high doping concentration is beneficial to reducing the contact resistance with the electrodes prepared subsequently. Optionally, after the second semiconductor layer 30 is formed on the first semiconductor layer 20, the method for etching the trench 31 is two-step etching. First, the second semiconductor layer 30 is dry-etched, and then the first semiconductor layer 20 is in-situ etched to form the trench 31. The two-step etching method can further improve the crystal quality of the surface of the trench 31, thereby improving the crystal quality of the third semiconductor layer 40 grown in the trench 31.

[0064] The present disclosure provides a manufacturing method of a semiconductor structure. In the present disclosure, a first semiconductor layer is grown on a substrate, a trench is etched on the side of the first semiconductor layer away from the substrate, the trench partially penetrates the first semiconductor layer, a sacrificial layer is grown on the first semiconductor layer and then the sacrificial layer is etched, and the growth and etching of the sacrificial layer are repeated multiple times until the ion concentration on the surface of the first semiconductor layer exposed by the trench is lower than a preset value, and a third semiconductor layer is secondarily epitaxially grown in the trench.

[0065] The present disclosure uses a method of growing a sacrificial layer multiple times and then etching the sacrificial layer. On the one hand, it can reduce the ion concentration of the first conductivity type on the surface of the first semiconductor layer exposed in the trench, which is beneficial to growing the third semiconductor layer of the second conductivity type in the trench and improving the lattice quality of the third semiconductor layer. On the other hand, it can reduce the impurity ion concentration in the growth cavity of the third semiconductor layer, further improving the quality of the third semiconductor layer, thereby improving the reliability of the semiconductor structure.

[0066] The third semiconductor layer of the present disclosure is formed by in-situ doping selective epitaxy, which avoids the lattice damage to the first semiconductor layer caused by the ion implantation method and avoids the inaccurate width of the third semiconductor layer caused by the diffusion effect of the ion implantation method, thereby improving the width accuracy of the channel between the third semiconductor layers and improving the reliability of the semiconductor structure.

[0067] It should be understood that the term "including" and its variants used in the present disclosure are open-ended, that is, "including but not limited to". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment". In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0068] The above are only the preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, It includes the following steps: S1. Provide a substrate (10) of the first conductivity type; S2. Grow a first semiconductor layer (20) of the first conductivity type on the substrate (10), and the substrate (10) has a doping concentration higher than that of the first semiconductor layer (20); S3. Etch a trench (31) on the side of the first semiconductor layer (20) away from the substrate (10), and the trench (31) partially penetrates the first semiconductor layer (20); S4. Grow a sacrificial layer (50) on the first semiconductor layer (20); S5. Etch the sacrificial layer (50); S6. Secondarily epitaxially grow a third semiconductor layer (40) of the second conductivity type in the trench (31); Wherein, before entering step S6, steps S4 and S5 are repeated N times until the ion concentration on the surface of the first semiconductor layer (20) exposed by the trench (31) is lower than a preset value.

2. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The method of etching the trench (31) in step S3 is in-situ etching.

3. The manufacturing method of the semiconductor structure according to claim 2, characterized in that, The in-situ etching is dry etching.

4. The manufacturing method of the semiconductor structure according to claim 2, wherein The gas environment of the etching includes one or a combination of more of Cl2, H2, HCl, and TBCl.

5. The manufacturing method of the semiconductor structure according to claim 2, wherein, After in-situ etching to form the trench (31) in step S3, it further includes: Secondarily etching the trench (31) to etch and form a plurality of V-grooves or hexagonal prisms arranged at intervals on the bottom surface of the trench (31).

6. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The material of the sacrificial layer (50) includes one or a combination of more of AlN, InN, InGaN, InAlN, InAlGaN, and GaN.

7. The manufacturing method of the semiconductor structure according to claim 6, characterized in that, The sacrificial layer (50) is an unintentionally doped layer.

8. The manufacturing method of the semiconductor structure according to claim 6, wherein The sacrificial layer (50) is a carbon-doped layer, an iron-doped layer, or an iron-carbon co-doped layer.

9. The manufacturing method of the semiconductor structure according to claim 1, wherein, The sacrificial layer (50) grows conformally on the first semiconductor layer (20), or the surface of the sacrificial layer (50) on the side away from the substrate (10) is a plane.

10. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The method of etching the sacrificial layer (50) in step S5 is in-situ etching.

11. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The ion doping concentration of the first semiconductor layer (20) is greater than 1E17 / cm 3 .

12. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The preset value is 1E15 / cm 3 .

13. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, The method of secondarily epitaxially growing the third semiconductor layer (40) is in-situ doped selective epitaxy.

14. The manufacturing method of the semiconductor structure according to claim 1, characterized in that, After step S2, it further includes: S21. Form a second semiconductor layer (30) of the first conductivity type on the first semiconductor layer (20), and the second semiconductor layer (30) has a doping concentration higher than that of the first semiconductor layer (20).

15. The manufacturing method of the semiconductor structure according to claim 14, characterized in that, The method of forming the second semiconductor layer (30) is epitaxial growth or ion implantation.

16. The manufacturing method of the semiconductor structure according to claim 14, characterized in that, Step S3 further includes etching a trench (31) on the side of the second semiconductor layer (30) away from the substrate (10), and the trench (31) penetrates the second semiconductor layer (30) and partially penetrates the first semiconductor layer (20).

17. The manufacturing method of the semiconductor structure according to claim 1, wherein, Step S6 further includes: S61. Secondarily epitaxially grow a third semiconductor layer (40) of the second conductivity type in the trench (31), and the thickness of the third semiconductor layer (40) is greater than the depth of the trench (31). S62. Use chemical mechanical polishing to remove the excess third semiconductor layer (40) on the surface of the second semiconductor layer (30) and planarize the surface of the second semiconductor layer (30).

18. The manufacturing method of the semiconductor structure according to claim 1, wherein After the step S6, the method further includes: S7. Forming a source electrode (61), a drain electrode (62) and a gate electrode (63), where the source electrode (61) is located on the surface of the first semiconductor layer (20) away from the substrate (10), the drain electrode (62) is located on the surface of the substrate (10) away from the first semiconductor layer (20), and the gate electrode (63) is located on the surface of the third semiconductor layer (40) away from the substrate (10).

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