Groove type MOS device and forming method thereof
By gradually forming the substrate material layer and shallow doping region around the gate structure on the initial substrate, the process complexity and reliability problems of trench MOS devices are solved, and higher product consistency and simplified design optimization are achieved.
Patent Information
- Application Number
- CN202510419650.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-08
AI Technical Summary
The process complexity, poor reliability and difficult design optimization of trench MOS devices.
After forming the gate structure on the initial substrate, the first and second substrate material layers are gradually formed, and shallow doping regions and source and drain regions are formed around it, avoiding deep etching and subsequent filling processes, and the substrate material layer is formed by epitaxial growth or chemical vapor deposition processes.
It reduces process complexity, improves product reliability and consistency, solves the problem of ion implantation depth limitation, and simplifies the difficulty of design optimization.
Smart Images
Figure CN120282478A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and particularly to a trench MOS device and a method for forming the same. Background Art
[0002] A trench MOSFET (Trench MOSFET) is a power semiconductor device that optimizes performance through a vertical trench structure and is widely used in high-performance scenarios. Especially in silicon carbide (SiC) and silicon (Si) materials, it has its unique advantages and disadvantages, which affect their selection and use in different applications. The advantages of trench MOSFETs include: reducing on-resistance, increasing current density, increasing device density, improving thermal performance, and optimizing switching performance. Specifically, the trench structure increases the channel area controlled by the gate, reduces the channel resistance, and thus reduces the resistance in the on state; by increasing the vertical area of the gate, a lower specific on-resistance (Ronsp) can be designed, allowing for a smaller chip size and higher current density; the trench design allows more cells to be arranged on the same chip area, improving the integration density; due to the reduction of on-resistance, the thermal management of the device during high-power operation is improved, enhancing the reliability of long-term operation. By reducing parasitic effects such as the JFET effect, trench MOSFETs can achieve faster switching speeds and better switching characteristics. However, trench MOSFETs also have many disadvantages, such as process complexity, reliability challenges, consistency issues, and difficulty in design optimization. Specifically, manufacturing trench MOSFETs requires more complex process steps, such as deep trench etching and precise gate oxide layer formation; the trench structure may introduce higher peak electric fields and requires careful design to avoid gate oxide layer damage and device reliability issues; due to the manufacturing of trenches, the consistency of cells may be inferior to that of planar structures, which may affect the uniformity and consistency of mass production; in order to overcome the electric field concentration brought by the trench structure and protect the gate oxide layer, complex device layouts and design optimizations are required, which increases the R & D time and cost, etc. Summary of the Invention
[0003] The purpose of the present invention is to provide a trench MOS device and a method for forming the same, so as to solve at least one of the problems of complex process, poor reliability, and great difficulty in design optimization of trench MOS devices.
[0004] To solve the above technical problems, the present invention provides a method for forming a trench MOS device, including:
[0005] Providing an initial substrate;
[0006] Forming a gate structure, the gate structure being located on the initial substrate;
[0007] Form a first substrate material layer, which is located on the initial substrate around the gate structure, and the height of the top surface of the first substrate material layer is lower than the height of the top surface of the gate structure;
[0008] Form a lightly doped region, which is located within the first substrate material layer around the gate structure;
[0009] Form a second substrate material layer, which is located on the first substrate material layer around the gate structure, and the top surface of the second substrate material layer is flush with the top surface of the gate structure;
[0010] Form a source region and a drain region, which are located within the second substrate material layer on both sides of the gate structure, and the source region and the drain region are respectively located on the lightly doped region, and the initial substrate, the first substrate material layer and the second substrate material layer together constitute the substrate of the device to form a trench-type MOS device.
[0011] Optionally, before forming the gate structure, form a gate oxide layer, which is located between the gate structure and the initial substrate.
[0012] Optionally, after forming the gate structure and before forming the first substrate material layer, form sidewalls of the gate structure, which are located on both sides of the gate structure.
[0013] Optionally, the materials of the initial substrate, the first substrate material layer and the second substrate material layer are all the same.
[0014] Optionally, the materials of the initial substrate, the first substrate material layer and the second substrate material layer are silicon carbide or silicon.
[0015] Optionally, the doping ion types of the source region and the drain region are the same as those of the lightly doped region.
[0016] Optionally, the doping concentration of the ions in the source region and the drain region is greater than that of the ions in the lightly doped region.
[0017] Optionally, the first substrate material layer and the second substrate material layer are formed by an epitaxial growth process or a chemical vapor deposition process.
[0018] Optionally, the lightly doped region, the source region and the drain region are formed by an ion implantation process.
[0019] Based on the same inventive concept, the present invention also provides a trench-type MOS device, which is prepared by using the formation method of the trench-type MOS device described in any one of the above, and includes:
[0020] A substrate, which includes an initial substrate, a first substrate material layer, and a second substrate material layer from bottom to top;
[0021] A gate structure, which is located on the initial substrate and surrounded by the first substrate material layer and the second substrate material layer, and the top surface of the second substrate material layer is flush with the top surface of the gate structure;
[0022] A lightly doped region, which is located in the first substrate material layer around the gate structure;
[0023] A source region and a drain region, which are located in the second substrate material layer on both sides of the gate structure, and the source region and the drain region are respectively located on the lightly doped region.
[0024] In the method for forming a trench-type MOS device provided by the present invention, an initial substrate is provided; first, a gate structure is formed, and the gate structure is located on the initial substrate; then, a first substrate material layer is formed, and the first substrate material layer is located on the initial substrate around the gate structure, and the height of the top surface of the first substrate material layer is lower than the height of the top surface of the gate structure; a lightly doped region is formed, and the lightly doped region is located in the first substrate material layer around the gate structure; and a second substrate material layer is formed, and the second substrate material layer is located on the first substrate material layer around the gate structure, and the top surface of the second substrate material layer is flush with the top surface of the gate structure; a source region and a drain region are formed, and the source region and the drain region are located in the second substrate material layer on both sides of the gate structure, and the source region and the drain region are respectively located on the lightly doped region, and the initial substrate, the first substrate material layer, and the second substrate material layer together constitute the substrate of the device to form a trench-type MOS device. In the present invention, the method for forming a trench-type MOS device is to first form a gate structure on the initial substrate, and then form the first substrate material layer and the second substrate material layer around the gate structure. The initial substrate, the first substrate material layer, and the second substrate material layer together constitute the substrate, that is, directly grow and prepare a trench-type MOS device on the initial substrate, without etching a trench and then filling the gate structure, reducing the process complexity; at the same time, avoiding the process problems of the trench-type MOS device that require deep etching and then filling the gate structure, improving the product reliability, uniformity, and consistency; and forming the first substrate material layer and the second substrate material layer around the gate structure in a segmented manner, and forming a lightly doped region in the first substrate material layer, solving the limitation of the ion implantation depth in the ion implantation process, that is, reducing the difficulty of process design optimization. Description of the Drawings
[0025] Those of ordinary skill in the art will understand that the provided drawings are for better understanding of the present invention and do not constitute any limitation to the scope of the present invention. Among them:
[0026] Figure 1 is a flowchart of a method for forming a trench MOS device according to an embodiment of the present invention.
[0027] Figures 2 to 7 is a schematic structural diagram corresponding to the steps of a method for forming a trench MOS device according to an embodiment of the present invention.
[0028] In the drawings:
[0029] 10 - Substrate; 10a - Initial substrate; 10b - First substrate material layer; 10c - Second substrate material layer; 11 - Gate oxide layer; 12 - Gate structure; 13 - Sidewall; 14 - Lightly doped region; 15a - Source region; 15b - Drain region. Detailed implementation manners
[0030] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the drawings and specific embodiments. It should be noted that the drawings are all in very simplified forms and are not drawn to scale, and are only used to facilitate and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures. In particular, the focus that each drawing needs to show is different, and sometimes different scales are used.
[0031] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. In addition, as used in the present invention, an element being disposed on another element generally only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element in any orientation, unless the content clearly indicates otherwise. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.
[0032] Figure 1It is a flowchart of a method for forming a trench-type MOS device according to an embodiment of the present invention. As Figure 1 shown, this embodiment provides a method for forming a trench-type MOS device, including:
[0033] Step S10: Provide an initial substrate;
[0034] Step S20: Form a gate structure, and the gate structure is located on the initial substrate;
[0035] Step S30: Form a first substrate material layer, and the first substrate material layer is located on the initial substrate around the gate structure, and the height of the top surface of the first substrate material layer is lower than the height of the top surface of the gate structure;
[0036] Step S40: Form a lightly doped region, and the lightly doped region is located in the first substrate material layer around the gate structure;
[0037] Step S50: Form a second substrate material layer, and the second substrate material layer is located on the first substrate material layer around the gate structure, and the top surface of the second substrate material layer is flush with the top surface of the gate structure;
[0038] Step S60: Form a source region and a drain region, and the source region and the drain region are located in the second substrate material layer on both sides of the gate structure, and the source region and the drain region are respectively located on the lightly doped region, and the initial substrate, the first substrate material layer, and the second substrate material layer together form the substrate of the device to form a trench-type MOS device.
[0039] Figures 2 to 7 It is a schematic structural diagram corresponding to the steps of the method for forming a trench-type MOS device according to an embodiment of the present invention. To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the following combines the accompanying Figures 2 to 7 description of the present invention will make a detailed description of specific embodiments of the present invention.
[0040] As Figure 2As shown, an initial substrate 10a is provided. The initial substrate 10a can provide an operating platform for subsequent processes. It can be any substrate well-known to those skilled in the art for carrying semiconductor integrated circuit components, which can be a die or a wafer processed by an epitaxial growth process. Specifically, the substrate is, for example, a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a silicon carbide (SiC) substrate, or a silicon (Si) substrate. The doping type of the initial substrate 10a is the first doping type, and the first doping type is, for example, P-type doping. In other embodiments, the doping type of the initial substrate 10a can also be the second doping type, and the second doping type is, for example, N-type doping. The doping type of the initial substrate 10a depends on the type of the trench MOS device, and this embodiment does not limit this. A gate oxide layer 11 and a gate structure 12 are formed in sequence. The gate oxide layer 11 is located between the gate structure 12 and the initial substrate 10a. The gate oxide layer 11 and the gate structure 12 are located on the initial substrate 10a, and the gate oxide layer 11 covers part of the initial substrate 10a and the gate structure 12 completely covers the gate oxide layer 11. The material of the gate oxide layer 11 is silicon oxide, which can be formed by chemical vapor deposition or thermal oxidation processes. The material of the gate structure 12 is polysilicon, which can be formed by chemical vapor deposition process.
[0041] As Figure 3 shown, after forming the gate structure 12, sidewalls 13 of the gate structure are formed. The sidewalls 13 of the gate structure are located on both sides of the gate structure 12. The sidewalls 13 cover the sidewalls on both sides of the gate structure 12. The material of the sidewalls 13 is, for example, one of silicon oxide, silicon nitride, or an ONO stack, and can be formed by chemical vapor deposition process.
[0042] As Figure 4 shown, a first substrate material layer 10b is formed. The first substrate material layer 10b is located on the initial substrate 10a around the gate structure 12, and the top surface height of the first substrate material layer 10b is lower than the top surface height of the gate structure 12. The height of the first substrate material layer 10b depends on the position of the lightly doped region in the trench MOS device. The first substrate material layer 10b covers the initial substrate 10. The material of the first substrate material layer 10b is the same as that of the initial substrate 10a. The material of the first substrate material layer 10b is, for example, silicon carbide (SiC) or silicon (Si), and is formed by epitaxial growth process or chemical vapor deposition process. The doping type of the first substrate material layer 10b is the same as that of the initial substrate 10a. The doping type of the first substrate material layer 10b is the first doping type, and the first doping type is, for example, P-type doping.
[0043] As Figure 5 shown, a lightly doped region 14 is formed. The lightly doped region 14 is located in the first substrate material layer 10b around the gate structure 12. The lightly doped region 14 is formed by an ion implantation process. The doping type of the lightly doped region 14 is opposite to that of the first substrate material layer 10b. The doping type of the lightly doped region 14 is the second doping type, and the second doping type is, for example, N-type doping. Forming the height of the first substrate material layer 10b according to the position of the lightly doped region in the trench-type MOS device avoids the problems of insufficient ion implantation depth due to the overly deep position of the lightly doped region 14 or excessive damage to the substrate surface. That is, in this embodiment, the substrate around the gate structure 12 is formed in a segmented manner, solving the limitation of the ion implantation depth in the ion implantation process.
[0044] As Figure 6 shown, a second substrate material layer 10c is formed. The second substrate material layer 10c is located on the first substrate material layer 10b around the gate structure 12, and the top surface of the second substrate material layer 10c is flush with the top surface of the gate structure 12; the second substrate material layer 10c covers the first substrate material layer 10b. The materials of the second substrate material layer 10c, the initial substrate 10a, and the first substrate material layer 10b are the same. The material of the second substrate material layer 10c is, for example, silicon carbide (SiC) or silicon (Si), and is formed by an epitaxial growth process or a chemical vapor deposition process. The doping type of the second substrate material layer 10c is the same as that of the initial substrate 10a and the first substrate material layer 10b. The doping type of the second substrate material layer 10c is the first doping type, and the first doping type is, for example, P-type doping.
[0045] As Figure 7As shown, a source region 15a and a drain region 15b are formed. The source region 15a and the drain region 15b are located in the second substrate material layer 10c on both sides of the gate structure 12, and the source region 15a and the drain region 15b are respectively located on the lightly doped region 14. The source region 15a and the drain region 15b have the same type of doping ions as the lightly doped region 14, and the doping type of the source region 15a and the drain region 15b is the second doping type. Moreover, the doping concentration of the ions in the source region 15a and the drain region 15b is greater than that of the ions in the lightly doped region 14, and the doping type of the source region 15a and the drain region 15b is, for example, N+ type doping. The lightly doped region 14 is used to prevent the doping ions in the source region 15a and the drain region 15b from diffusing downward into the substrate. The initial substrate 10a, the first substrate material layer 10b, and the second substrate material layer 10c together constitute the substrate 10. That is, the trench MOS device in this embodiment is directly grown and fabricated on the initial substrate 10a without etching a trench and then filling the gate structure, reducing the process complexity; at the same time, avoiding the process problems of the trench MOS device that require deep etching and then filling the gate structure, improving the product reliability, uniformity, and consistency; and forming the first substrate material layer and the second substrate material layer around the gate structure in a segmented manner, solving the limitation of the ion implantation depth in the ion implantation process, that is, reducing the difficulty of process design optimization.
[0046] As Figure 7 shown, this embodiment further provides a trench MOS device, which is fabricated by using the formation method of the trench MOS device described in any one of the above, and includes:
[0047] A substrate 10, where the substrate 10 includes an initial substrate 10a, a first substrate material layer 10b, and a second substrate material layer 10c from bottom to top;
[0048] A gate structure 12, where the gate structure 12 is located on the initial substrate 10a and is surrounded by the first substrate material layer 10b and the second substrate material layer 10c, and the top surface of the second substrate material layer 10c is flush with the top surface of the gate structure 12;
[0049] A lightly doped region 14, where the lightly doped region 14 is located in the first substrate material layer 10b around the gate structure 12;
[0050] A source region 15a and a drain region 15b, where the source region 15a and the drain region 15b are respectively located in the second substrate material layer 10c on both sides of the gate structure 12, and both the source region 15a and the drain region 15b are located on the lightly doped region 14.
[0051] In summary, in the method for forming a trench-type MOS device provided by the embodiments of the present invention, an initial substrate is provided; a gate structure is first formed, and the gate structure is located on the initial substrate; then a first substrate material layer is formed, and the first substrate material layer is located on the initial substrate around the gate structure, and the height of the top surface of the first substrate material layer is lower than the height of the top surface of the gate structure; a lightly doped region is formed, and the lightly doped region is located in the first substrate material layer around the gate structure; and a second substrate material layer is formed, and the second substrate material layer is located on the first substrate material layer around the gate structure, and the top surface of the second substrate material layer is flush with the top surface of the gate structure; a source region and a drain region are formed, and the source region and the drain region are located in the second substrate material layer on both sides of the gate structure, and the source region and the drain region are respectively located on the lightly doped region, and the initial substrate, the first substrate material layer, and the second substrate material layer together form the substrate of the device to form a trench-type MOS device. In the method for forming a trench-type MOS device in the present invention, a gate structure is first formed on the initial substrate, and then a first substrate material layer and a second substrate material layer around the gate structure are formed. The initial substrate, the first substrate material layer, and the second substrate material layer together form the substrate, that is, the trench-type MOS device is directly grown and prepared on the initial substrate, without etching a trench and then filling the gate structure, reducing the process complexity; at the same time, it avoids the process problems of the trench-type MOS device that require deep etching and then filling the gate structure, improving the product reliability, uniformity, and consistency; and the first substrate material layer and the second substrate material layer around the gate structure are formed in a segmented manner, and a lightly doped region is formed in the first substrate material layer, solving the limitation of the ion implantation depth in the ion implantation process, that is, reducing the difficulty of process design optimization.
[0052] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the above-disclosed technical content, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.
Claims
1. A method for forming a trench MOS device, characterized in that, Comprising: Providing an initial substrate; Forming a gate structure, the gate structure being located on the initial substrate; Forming a first substrate material layer, the first substrate material layer being located on the initial substrate around the gate structure, and the height of the top surface of the first substrate material layer being lower than the height of the top surface of the gate structure; Forming a lightly doped region, the lightly doped region being located within the first substrate material layer around the gate structure; Forming a second substrate material layer, the second substrate material layer being located on the first substrate material layer around the gate structure, and the top surface of the second substrate material layer being flush with the top surface of the gate structure; Forming a source region and a drain region, the source region and the drain region being located within the second substrate material layer on both sides of the gate structure, and the source region and the drain region being respectively located on the lightly doped region, and the initial substrate, the first substrate material layer and the second substrate material layer together constitute the substrate of the device to form a trench-type MOS device.
2. The forming method of the trench MOS device according to claim 1, characterized in that, Before forming the gate structure, forming a gate oxide layer, the gate oxide layer being located between the gate structure and the initial substrate.
3. The method for forming a trench MOS device according to claim 1, wherein After forming the gate structure and before forming the first substrate material layer, forming sidewalls of the gate structure, the sidewalls being located on both sides of the gate structure.
4. The method for forming a trench MOS device according to claim 1, wherein The materials of the initial substrate, the first substrate material layer and the second substrate material layer are the same.
5. The method for forming a trench MOS device according to claim 4, wherein The materials of the initial substrate, the first substrate material layer and the second substrate material layer are silicon carbide or silicon.
6. The method for forming a trench MOS device according to claim 1, wherein The doping ion types of the source region and the drain region are the same as those of the lightly doped region.
7. The method for forming a trench MOS device according to claim 6, characterized in that, The doping concentration of the ions in the source region and the drain region is greater than that of the ions in the lightly doped region.
8. The forming method of the trench MOS device according to claim 1, characterized in that, The first substrate material layer and the second substrate material layer are formed by an epitaxial growth process or a chemical vapor deposition process.
9. The method for forming a trench MOS device according to claim 1, characterized in that, The lightly doped region, the source region and the drain region are formed by an ion implantation process.
10. A trench MOS device, characterized in that, Prepared by using the formation method of the trench-type MOS device according to any one of claims 1 to 9, comprising: A substrate, the substrate comprising an initial substrate, a first substrate material layer and a second substrate material layer from bottom to top; A gate structure, the gate structure being located on the initial substrate and surrounded by the first substrate material layer and the second substrate material layer, and the top surface of the second substrate material layer being flush with the top surface of the gate structure; A lightly doped region, the lightly doped region being located within the first substrate material layer around the gate structure; A source region and a drain region, the source region and the drain region being located within the second substrate material layer on both sides of the gate structure, and the source region and the drain region being respectively located on the lightly doped region.