Groove type silicon carbide MOSFET device and preparation method thereof

Abstract

The invention discloses a trench-type silicon carbide MOSFET device and a preparation method thereof, and belongs to the field of semiconductors, the device introduces a P-type deep doped region and a Schottky trench, so that when the device is in a reverse voltage withstanding state, the Schottky trench is formed in the P-type deep doped region, and the Schottky trench is formed in the Schottky trench; a P-type buried layer, an N-type first silicon carbide epitaxial layer, a P-type deep doped region and an N-type second silicon carbide epitaxial layer are used as gate oxide protection structures, and the transverse and longitudinal gate oxide protection structures are used up together to protect a gate oxide layer and reduce the electric field intensity at the corner of a gate; when avalanche breakdown occurs in the device, avalanche current flows through a P-type deep doping region and then flows into a source electrode through source electrode metal in a Schottky groove, and the avalanche current almost does not flow through a first P-type body region, then enters an N + type source region and finally enters the source electrode metal, so that the risk of starting a parasitic triode is reduced; source electrode metal at the bottom of the Schottky groove and the N-type second silicon carbide epitaxial layer form Schottky contact, so that the device is integrated with a Schottky structure, and the reverse recovery performance of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductors, and particularly relates to a trench-type silicon carbide MOSFET device and a manufacturing method thereof. Background Art

[0002] As a wide-bandgap semiconductor material, silicon carbide has advantages such as a high critical breakdown electric field strength, a high saturated electron mobility, and a high thermal conductivity, and has great material advantages in the field of power electronic devices. Compared with a planar VDMOS (Vertical Double-diffused Metal-Oxide-Semiconductor) device, in a trench-type silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), the conductive channel is in the vertical direction, eliminating the parasitic junction field-effect transistor (JFET) resistance of the planar VDMOS, reducing the cell size, and increasing the cell density, thereby significantly increasing the current density and greatly reducing the on-resistance of the device.

[0003] Compared with the planar structure, the cell density per unit area of the trench-type silicon carbide is relatively high, resulting in a reduced avalanche capability of the device. Especially, the problem of the parasitic triode conduction in the cell region of the silicon carbide device is more obvious under a small inductance. Currently, an asymmetric trench MOSFET device and a double-trench MOSFET device are generally adopted. In the asymmetric trench MOSFET device, one side of the gate trench is used for conduction, and the other side is used to fabricate a P+ shielding region. However, when the asymmetric trench MOSFET device is turned on, a depletion region is formed between the P+ shielding region and the N-type epitaxial layer, greatly narrowing the conduction path of the electron current and increasing the on-resistance of the MOSFET device. In the double-trench MOSFET device, a gate trench and a source trench are introduced. However, there is still a relatively high gate oxide electric field strength at the center of the gate trench, providing insufficient electric field protection for the gate oxide. Especially, the gate oxide at the corner is easily broken down by the electric field. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a trench-type silicon carbide MOSFET device and a manufacturing method thereof. The technical problems to be solved by the present invention are realized through the following technical solutions: In a first aspect, an embodiment of the present invention provides a trench-type silicon carbide MOSFET device, where the trench-type silicon carbide MOSFET device includes: A silicon carbide substrate; An N-type first silicon carbide epitaxial layer located on the upper surface of the silicon carbide substrate; A P-type buried layer located within the N-type first silicon carbide epitaxial layers at both ends of the device; An N-type second silicon carbide epitaxial layer located on the P-type buried layer and the remaining N-type first silicon carbide epitaxial layer; Two gate trenches respectively penetrating through the N-type second silicon carbide epitaxial layers near both ends of the device until within the corresponding P-type buried layers; a gate oxide layer is provided on the inner wall of each gate trench, and P-type polysilicon is provided on the gate oxide layer and within the gate trenches; Two N+-type source regions located within the N-type second silicon carbide epitaxial layer between the two gate trenches and respectively in contact with the gate oxide layer within one of the gate trenches; Two first P-type body regions respectively located within the N-type second silicon carbide epitaxial layer below one of the N+-type source regions and in contact with the corresponding N+-type source region; Two second P-type body regions located within the N-type second silicon carbide epitaxial layer between the two N+-type source regions and respectively in contact with the adjacent N+-type source regions; Two P-type deep doping regions respectively located within the N-type second silicon carbide epitaxial layer below one of the second P-type body regions, in contact with the corresponding second P-type body region, and in contact with the adjacent first P-type body region; at this time, the second P-type body region and the first P-type body region are in a connected structure and are diagonally distributed, and the depth of the P-type deep doping region within the N-type second silicon carbide epitaxial layer is greater than the depth of the first P-type body region within the N-type second silicon carbide epitaxial layer; Interlayer insulating dielectrics respectively located on the N-type second silicon carbide epitaxial layers at both ends of the device, the gate trenches, and part of the N+-type source regions; A Schottky trench located within the N-type second silicon carbide epitaxial layer between the two P-type deep doping regions; the depth of the Schottky trench within the N-type second silicon carbide epitaxial layer is less than the depth of the P-type deep doping region within the N-type second silicon carbide epitaxial layer and greater than the depth of the first P-type body region within the N-type second silicon carbide epitaxial layer; Source metal located within the Schottky trench, on all the interlayer insulating dielectrics, on all the second P-type body regions, and on the remaining all N+-type source regions; Drain metal located on the lower surface of the silicon carbide substrate.

[0005] In a second aspect, an embodiment of the present invention provides a method for manufacturing a trench-type silicon carbide MOSFET device, and the manufacturing method includes: Obtain a silicon carbide substrate; Deposit an N-type first silicon carbide epitaxial layer on the upper surface of the silicon carbide substrate; An N-type first silicon carbide epitaxial layer at both ends of the device is subjected to ion implantation to form a P-type buried layer; An N-type second silicon carbide epitaxial layer is deposited on the P-type buried layer and the N-type first silicon carbide epitaxial layer; Ion implantation is performed on the N-type second silicon carbide epitaxial layer to form two first P-type body regions; Ion implantation is performed on a part of each first P-type body region to form a corresponding N+-type source region; Ion implantation is performed on another part of each first P-type body region to form a second P-type body region and a P-type deep doping region from top to bottom; at this time, the second P-type body region and the first P-type body region are in a connected structure and are diagonally distributed, and the depth of the P-type deep doping region in the N-type second silicon carbide epitaxial layer is greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer; The N-type second silicon carbide epitaxial layer near both ends of the device is etched until it reaches the corresponding P-type buried layer to form two gate trenches. A gate oxide layer is grown in each gate trench, and P-type polysilicon is deposited on the gate oxide layer and in the gate trenches; Interlayer insulating dielectrics are respectively formed on the N-type second silicon carbide epitaxial layer, the gate trenches, and a part of the N+-type source regions at both ends of the device; The N-type second silicon carbide epitaxial layer in the middle region is etched to form Schottky trenches; the depth of the Schottky trenches in the N-type second silicon carbide epitaxial layer is less than the depth of the P-type deep doping region in the N-type second silicon carbide epitaxial layer and greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer; Source metal is deposited in the Schottky trenches, on all interlayer insulating dielectrics, on all second P-type body regions, and on the remaining all N+-type source regions; Drain metal is deposited on the lower surface of the silicon carbide substrate.

[0006] Advantages of the present invention: The trench-type silicon carbide MOSFET device proposed by the present invention starts from the device structure and innovatively introduces a P-type deep doping region and a Schottky trench. At the same time, it is designed that the depth of the Schottky trench in the N-type second silicon carbide epitaxial layer is less than the depth of the P-type deep doping region in the N-type second silicon carbide epitaxial layer and greater than the depth of the first P-type body region in the N-type second silicon carbide epitaxial layer, so that: when the device is in the reverse voltage withstand state, the P-type buried layer, the N-type first silicon carbide epitaxial layer, the P-type deep doping region and the N-type second silicon carbide epitaxial layer can be used as a gate oxide protection structure, and the lateral and longitudinal gate oxide protection structures are depleted together to protect the gate oxide layer in the gate trench and reduce the electric field strength at the gate corner; when the device undergoes avalanche breakdown, after flowing through the P-type deep doping region, it flows into the source through the source metal inside the Schottky trench, and the avalanche current hardly flows through the first P-type body region and then enters the N+-type source region and finally enters the source metal, thereby reducing the risk of parasitic triode turn-on; the source metal at the bottom of the Schottky trench forms a Schottky contact with the N-type second silicon carbide epitaxial layer, so that the device integrates a Schottky structure and can improve the reverse recovery performance of the device.

[0007] The present invention will be further described in detail below with reference to the drawings and embodiments. Description of the Drawings

[0008] Figure 1 is a schematic structural diagram of a trench-type silicon carbide MOSFET device provided by an embodiment of the present invention; Figure 2 is a schematic cross-sectional structure diagram of gate trenches located in different regions of a chip provided by an embodiment of the present invention; Figure 3 is a top view plane structure of a discontinuous P-type deep doping region provided by an embodiment of the present invention, and schematic cross-sectional structures corresponding to cuts in different directions; Figures 4(a) to 4(b) is a schematic diagram of a simulation structure and electric field strength of a gate oxide layer in a gate trench in the reverse voltage withstand state in an edge region provided by an embodiment of the present invention; Figures 5(a) to 5(b) is a schematic diagram of avalanche current paths of a traditional trench structure and the trench structure proposed by the present invention; Figure 6 is provided by an embodiment of the present invention Figure 1 schematic flow diagram of the manufacturing method of the trench-type silicon carbide MOSFET device shown; Figures 7(a) to 7(r) is provided by an embodiment of the present invention Figure 1 schematic structural diagrams corresponding to each step in the manufacturing process of the trench-type silicon carbide MOSFET device shown.

[0009] Description of the Reference Numerals: 01 - Silicon carbide substrate; 02 - N-type first silicon carbide epitaxial layer; 03 - P-type buried layer; 04 - N-type second silicon carbide epitaxial layer; 051 - First P-type body region; 052 - Second P-type body region; 06 - P-type deep doping region; 07 - N+-type source region; 08 - Gate trench; 09 - Gate oxide layer; 10 - P-type polysilicon; 11 - Interlayer insulating dielectric; 12 - Schottky trench; 13 - Source metal; 14 - Drain metal. Detailed implementation manners

[0010] The following further describes the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0011] In the first aspect, please refer to Figure 1 , an embodiment of the present invention provides a trench-type silicon carbide MOSFET device, and the trench-type silicon carbide MOSFET device includes: Silicon carbide substrate 01; N-type first silicon carbide epitaxial layer 02, located on the upper surface of the silicon carbide substrate 01; P-type buried layer 03, located in the N-type first silicon carbide epitaxial layers 02 at both ends; N-type second silicon carbide epitaxial layer 04, located on the P-type buried layer 03 and the remaining N-type first silicon carbide epitaxial layer 02; Two gate trenches 08, respectively penetrating the N-type second silicon carbide epitaxial layer 04 near both ends of the device until reaching the corresponding P-type buried layer 03; a gate oxide layer 09 is provided on the inner wall of each gate trench 08, and P-type polysilicon 10 is provided on the gate oxide layer 09 and in the gate trench 08; Two N+-type source regions 07, located in the N-type second silicon carbide epitaxial layer 04 between the two gate trenches 08, and respectively in contact with the gate oxide layer 09 in one gate trench 08; Two first P-type body regions 051, respectively located in the N-type second silicon carbide epitaxial layer 04 below one N+-type source region 07, and in contact with the corresponding N+-type source region 07; Two second P-type body regions 052, located in the N-type second silicon carbide epitaxial layer 04 between the two N+-type source regions 07, and respectively in contact with one N+-type source region 07; Two P-type deep doping regions 06, respectively located in the N-type second silicon carbide epitaxial layer 04 below one second P-type body region 052, and in contact with the corresponding second P-type body region 052 and in contact with the adjacent first P-type body region 051; at this time, the second P-type body region 052 and the first P-type body region 051 are in a connected structure and are diagonally distributed; Interlayer insulating dielectric 11, respectively located on the N-type second silicon carbide epitaxial layer 04, gate trench 08, and part of the N+-type source region 07 at both ends of the device; The Schottky trench 12 is located in the N-type second silicon carbide epitaxial layer 04 between two P-type deeply doped regions 06; the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deeply doped region 06 in the N-type second silicon carbide epitaxial layer 04 and greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04; The source metal 13 is located in the Schottky trench 12, on all the interlayer insulating dielectrics 11, on all the second P-type body regions 052, and on all the remaining N+-type source regions 07; The drain metal 14 is located on the lower surface of the silicon carbide substrate 01.

[0012] In the embodiment of the present invention, the silicon carbide substrate 01 is an N+-type silicon carbide substrate, and the specific material can be 4H-SiC; the thickness of the silicon carbide substrate 01 is 200 μm to 350 μm, and the doping concentration is 6e17 cm -3 ~8e17 cm -3 .

[0013] In the embodiment of the present invention, the thickness of the N-type first silicon carbide epitaxial layer 02 is 2 μm to 10 μm, and the doping concentration is 4e15 cm -3 ~8e15 cm -3 .

[0014] In the embodiment of the present invention, the depth of the P-type buried layer 03 in the N-type first silicon carbide epitaxial layer 02 is 0.3 μm to 0.8 μm, and the doping concentration is 5e17 cm -3 ~1e18 cm -3 .

[0015] In the embodiment of the present invention, the thickness of the N-type second silicon carbide epitaxial layer 04 is 1.5 μm to 2 μm, and the doping concentration is 4e15 cm -3 ~8e15 cm -3 .

[0016] In the embodiment of the present invention, the width of the gate trench 08 is 0.8 μm to 1.2 μm; the material of the gate oxide layer 09 provided in the gate trench 08 can be SiO2 (silicon dioxide), SiN (silicon nitride), etc. The bottom of the gate trench 08 is an arc structure, and the P-type buried layer 03 wraps the bottom of the gate trench 08. If the P-type buried layer 03 wraps too little of the gate trench 08, it will result in insufficient protection for the gate oxide layer 09 in the gate trench 08. If the P-type buried layer 03 wraps too much of the gate trench 08, it will increase the on-resistance of the device. The width of the P-type buried layer 03 on both sides of the gate trench 08 is 0.3 μm to 0.6 μm.

[0017] In the embodiment of the present invention, the depth of the N+-type source region 07 in the N-type second silicon carbide epitaxial layer 04 is 0.3 μm to 0.5 μm, the width is 0.6 μm to 1.2 μm, and the doping concentration is 8e18 cm -3 ~2e19 cm -3 .

[0018] In the embodiment of the present invention, the depth corresponding to the deepest part of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04 is 0.5 μm to 1.2 μm, the width of the first P-type body region 051 is 0.5 μm to 1.2 μm, and the doping concentration is 1e16 cm -3 ~5e16 cm -3 .

[0019] In the embodiment of the present invention, the width of the second P-type body region 052 in the N-type second silicon carbide epitaxial layer 04 is 0.6 μm to 0.9 μm. The doping concentration of the second P-type body region 052 in the embodiment of the present invention is greater than that of the first P-type body region 051, and specifically depends on the doping situation in the process.

[0020] In the embodiment of the present invention, the depth of the deepest part of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 is 1.0 μm to 1.5 μm, and the width of the P-type deep doping region 06 is 0.5 μm to 0.8 μm. In the embodiment of the present invention, the doping concentration of the P-type deep doping region 06 decreases sequentially from bottom to top in the vertical direction, and the doping concentration at the bottom of the P-type deep doping region 06 is 5 to 10 times that of the first P-type body region 051, and the doping concentration at the top of the P-type deep doping region 06 is 2.5 to 5 times that of the first P-type body region 051. Preferably, according to the doping situation of the first P-type body region 051, the doping concentration at the bottom of the P-type deep doping region 06 is 5e16 cm -3 ~5e17 cm -3 , and the doping concentration at the top of the P-type deep doping region 06 is 2.5e16 cm -3 ~2.5e17 cm -3 . Here, the vertical direction refers to the vertical direction from the silicon carbide substrate 01 to the source metal 13 as shown in Figure 1 .

[0021] In the embodiment of the present invention, the horizontal distance between the P-type deep doping region 06 and the P-type buried layer 03 is 0.5 μm to 0.9 μm. If the horizontal distance between the P-type deep doping region 06 and the P-type buried layer 03 is too close, it will increase the on-resistance of the device, and if it is too far, it will affect the protection effect on the gate oxide layer 09 in the gate trench 08.

[0022] In the embodiment of the present invention, the material of the interlayer insulating dielectric 11 can be SiO2, SiN, etc., and the thickness is 1.0 μm to 1.2 μm.

[0023] In the embodiment of the present invention, the material of the source metal 13 can be a metal combination of titanium / titanium nitride / aluminum laminated from bottom to top, and the thickness of the source metal 13 on the interlayer insulating dielectric 11 is 3.0 μm to 5.0 μm; the material of the drain metal 14 can be a metal combination of titanium / nickel / silver laminated from inside to outside, and the thickness is 0.1 μm to 0.3 μm.

[0024] Generally, the trench-type silicon carbide MOSFET device is located in the central region of the chip, such as Figure 2 shown, that is Figure 2 the range shown within the dashed box. At this time, the source metal 13 forms ohmic contacts with the second P-type body region 052 and the P-type deep-doped region 06 respectively, and the source metal 13 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04. However, there may also be a trench-type silicon carbide MOSFET device located in the edge region of the chip, that is Figure 2 the range shown outside the dashed box. At this time, the P-type polysilicon 10 at the bottom of the gate trench 08 penetrates the gate oxide layer 09 to form an ohmic contact with the P-type buried layer 03, and at the same time, the source metal 13 penetrates the interlayer insulating dielectric 11 to contact a part of the P-type polysilicon 10 in the groove structure 8. Here, the P-type polysilicon 10 in the edge region forms an ohmic contact with the P-type buried layer 03. Through the contacts around the edge, it can be ensured that the source potential is consistent with the P-type buried layer 03. When the device is in the reverse breakdown voltage state, only when the potentials of the P-type buried layer 03 and the source metal 13 are consistent can the protection effect on the trench gate oxide corner be achieved.

[0025] To increase the proportion of the Schottky region area and reduce the on-resistance of the device, in the embodiment of the present invention, the P-type deep-doped region 06 has a discontinuous structure. As Figure 3 shown, when viewed from the top-down direction, the P-type deep-doped region 06 can be discontinuous and has a periodic discontinuous structure. Please refer to Figure 3 again. Cut the trench-type silicon carbide MOSFET device along the AA direction and the AB direction respectively: When cutting along the AA direction, it passes through the P-type deep-doped region 06. From its cross-sectional structure, it can be seen that the device structure cut along the AA direction is the same as that of the device located in the central region; when cutting along the AB direction, it does not pass through the P-type deep-doped region 06. From its cross-sectional structure, it can be seen that the device structure cut along the AB direction does not have the P-type deep-doped region 06 and the second P-type body region 052, but still needs to satisfy that the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0026] The trench-type silicon carbide MOSFET device provided by the embodiment of the present invention can solve the problem that the traditional trench-type MOSFET device has insufficient electric field protection for the gate oxide layer 09 at the bottom of the trench, especially the gate oxide layer 09 at the corner is prone to be broken down by the electric field, improve the problem of the long reverse recovery time of the silicon carbide body diode and the degradation of the diode performance, and improve the problem of the turn-on of the parasitic triode of the silicon carbide device. Specifically: To solve the above technical problems, the corresponding mechanism is as follows: A: The trench-type MOSFET device proposed by the present invention solves the problem that the traditional trench-type MOSFET device has insufficient electric field protection for the gate oxide layer at the bottom of the gate trench, especially the gate oxide layer at the corner of the gate trench is prone to be broken down by the electric field.

[0027] Mechanism: When the device withstands reverse voltage, the P-type heavily doped region 06 and the P-type buried layer 03 jointly form a depletion region with the N-type first silicon carbide epitaxial layer 02 and the N-type second silicon carbide epitaxial layer 04. A space charge region is formed between the P-type buried layer 03 and the P-type heavily doped region 06 to shield the electric field passing through the gate oxide layer 09, thereby reducing the electric field strength and protecting the gate oxide layer 09 at the corner of the gate trench 08. It can be seen that the trench-type silicon carbide MOSFET device proposed by the embodiment of the present invention has the effect of shielding and protecting the gate oxide layer 09. When the trench-type silicon carbide MOSFET device is in the reverse voltage withstand state, the P-type buried layer 03, the N-type first silicon carbide epitaxial layer 02, the P-type heavily doped region 06 and the N-type second silicon carbide epitaxial layer 04 are specifically used as the gate oxide protection structure. The lateral and longitudinal gate oxide protection structures are jointly depleted to protect the gate oxide layer 09 in the gate trench 08 and reduce the electric field strength at the corner of the gate trench 08. Specifically, as Figures 4(a) to 4(b) shown, Fig. 4(a) is a schematic diagram of the simulation structure of the gate oxide layer in the gate trench along the AC direction in the edge region under the reverse voltage withstand state. In Fig. 4(a), the abscissa represents the structural length of the structure of the present invention corresponding to the edge region along the Figure 2 AC direction from left to right, with the unit of μm, and the ordinate represents the structural depth of the structure of the present invention corresponding to the edge region, with the unit of μm. Fig. 4(b) is a schematic diagram of the electric field strength of the gate oxide layer in the gate trench along the AC direction in the edge region under the reverse voltage withstand state. In Fig. 4(b), the abscissa represents the structural length of the structure of the present invention corresponding to the edge region along the Figure 2 AC direction from left to right, with the unit of μm, and the ordinate represents the electric field strength of the gate oxide layer in the gate trench along the AC direction in the edge region under the reverse voltage withstand state, with the unit of MV / μm. It can be seen from Fig. 4(a) and Fig. 4(b) that for the trench-type silicon carbide MOSFET device cut along the AC direction, the electric field strength of the gate oxide layer 09 at the corner of the gate trench 08 is reduced to less than 1.7 MV / cm, which is much less than the safe electric field strength of less than 3 MV / cm.

[0028] B: The trench MOSFET device proposed by the present invention improves the problem of the turn-on of the parasitic triode in the silicon carbide device.

[0029] Mechanism: By introducing Schottky trenches 12 between the P-type deep-doped regions 06, the depth of the Schottky trenches 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep-doped regions 06 in the N-type second silicon carbide epitaxial layer 04 but greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04. Ohmic contacts are formed between the sidewalls of the Schottky trenches 12 and the P-type deep-doped regions 06, and Schottky contacts are formed between the bottoms of the Schottky trenches 12 and the N-type second silicon carbide epitaxial layer 04. The doping concentration of the P-type deep-doped regions 06 is higher than that of the first P-type body region 051 and the second P-type body region 052. When the device undergoes avalanche breakdown, the avalanche current preferentially flows through the P-type deep-doped regions 06 (this region has a higher doping concentration and a small on-resistance) and then flows into the source metal 13 inside the Schottky trenches 12. The specific avalanche current path is shown by the dashed arrow in Fig. 5(a). That is to say, when the device structure proposed by the present invention undergoes avalanche breakdown, the avalanche current hardly flows through the first P-type body region 051 and the N+-type source region 07, but directly flows through the P-type deep-doped regions 06 and enters the source metal 13, thereby reducing the risk of the turn-on of the parasitic triode (the parasitic triode formed by the N+-type source region 07, the first P-type body region 051, the second P-type body region 052, and the N-type second silicon carbide epitaxial layer 04). The avalanche current path of the traditional structure is shown by the dashed arrow in Fig. 5(b). When avalanche breakdown occurs, part of the avalanche current flows into the source metal 13 after flowing through the P-type body region, and part of the current flows through the N+-type source region 07 and then into the source metal 13. When the avalanche current flows through the P-type body region, the P-type body region will cause a voltage drop, resulting in the conduction of the parasitic triode and then burning out the device.

[0030] C: The trench MOSFET device proposed by the present invention improves the problems of the relatively long reverse recovery time and the degradation of the diode performance of the silicon carbide body diode.

[0031] Mechanism: The source metal 13 at the bottom of the Schottky trenches 12 forms Schottky contacts with the N-type second silicon carbide epitaxial layer 04. The Schottky junction barrier is much lower than that of a normal silicon carbide PN junction. When the silicon carbide device is in the freewheeling stage, the Schottky diode conducts preferentially. When the current continues to increase, the silicon carbide PN junction starts to conduct, and the Schottky diode conducts by single-carrier conduction, and the reverse recovery time of the device is shorter. Since the device structure proposed by the present invention integrates the Schottky structure, the reverse recovery performance of the device is improved.

[0032] In summary, for the trench-type silicon carbide MOSFET device proposed in the embodiments of the present invention, starting from the device structure, a P-type deep doping region 06 and a Schottky trench 12 are innovatively introduced. At the same time, it is designed that the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 and greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04, so that: when the device is in the reverse voltage withstand state, the P-type buried layer 03, the N-type first silicon carbide epitaxial layer 02, the P-type deep doping region 06, and the N-type second silicon carbide epitaxial layer 04 can be used as a gate oxide protection structure, and the lateral and longitudinal gate oxide protection structures are depleted together to protect the gate oxide layer 09 in the gate trench 08 and reduce the electric field strength at the gate corner; when the device undergoes avalanche breakdown, after flowing through the P-type deep doping region 06, it flows into the source through the source metal 13 inside the Schottky trench 12, and the avalanche current hardly flows through the P-type body region (the first P-type body region 051, the second P-type body region 052) and then enters the N+-type source region 07 and finally enters the source metal 13, thereby reducing the risk of parasitic triode turn-on; the source metal 13 at the bottom of the Schottky trench 12 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04, so that the device integrates a Schottky structure and can improve the reverse recovery performance of the device.

[0033] In a second aspect, please refer to Figure 6 , the embodiments of the present invention provide a method for manufacturing a trench-type silicon carbide MOSFET device, and the manufacturing method includes: S10. Obtain a silicon carbide substrate 01.

[0034] In the embodiments of the present invention, a silicon carbide substrate 01 made of N+-type 4H-SiC with a thickness of 200 μm to 350 μm and a doping concentration of 6e17 cm -3 ~8e17 cm -3 is obtained, and the N+-type 4H-silicon carbide substrate 01 is cleaned.

[0035] S20. Deposit an N-type first silicon carbide epitaxial layer 02 on the upper surface of the silicon carbide substrate 01.

[0036] As shown in FIG. 7(a), in the embodiments of the present invention, an N-type first silicon carbide epitaxial layer 02 with a thickness of 2 μm to 10 μm and a doping concentration of 4e15 cm -3 ~8e15 cm -3 is deposited on the upper surface of the silicon carbide substrate 01 by using the MOCVD (Metal-Organic Chemical Vapor Deposition) process.

[0037] S30. Perform ion implantation on the N-type first silicon carbide epitaxial layer 02 at both ends of the device to form a P-type buried layer 03.

[0038] As shown in FIG. 7(b), in the embodiment of the present invention, an oxide layer is deposited on the device surface obtained in S20. The material of the oxide layer can be SiO2. Through photolithography and etching processes, a part of the oxide layer is etched off on the N-type first silicon carbide epitaxial layer 02 to form a P-type buried layer ion implantation window. P-type ions such as aluminum ions are selectively implanted in the P-type buried layer ion implantation window. The energy of the ion implantation is 50 keV to 150 keV, so as to respectively form P-type buried layers 03 with a depth of 0.3 μm to 0.8 μm and a doping concentration of 5e17 cm -3 ~1e18 cm -3 in the N-type first silicon carbide epitaxial layer 02 at both ends of the device, and all the remaining oxide layer is etched off.

[0039] S40. Deposit an N-type second silicon carbide epitaxial layer 04 on the P-type buried layer 03 and the N-type first silicon carbide epitaxial layer 02.

[0040] As shown in FIG. 7(c), in the embodiment of the present invention, an N-type second silicon carbide epitaxial layer 04 with a thickness of 1.5 μm to 2 μm and a doping concentration of 4e15 cm -3 ~8e15 cm -3 is deposited on the P-type buried layer 03 and the N-type first silicon carbide epitaxial layer 02 by using the MOCVD process.

[0041] S50. Perform ion implantation on the N-type second silicon carbide epitaxial layer 04 to form two first P-type body regions 051.

[0042] As shown in FIG. 7(d), in the embodiment of the present invention, an oxide layer is deposited on the device surface obtained in S40. Through photolithography and etching processes, a part of the oxide layer is etched off on the N-type second silicon carbide epitaxial layer 04 to form a first P-type body region ion implantation window. P-type ions such as aluminum ions are selectively implanted in the first P-type body region ion implantation window. The energy of the ion implantation is 50 keV to 150 keV, so as to respectively form first P-type body regions 051 with a depth of 0.5 μm to 1.2 μm, a width of 0.5 μm to 1.2 μm, and a doping concentration of 1e16 cm -3 ~5e16 cm -3 in the N-type second silicon carbide epitaxial layer 04 at both ends of the device, and all the remaining oxide layer is etched off.

[0043] S60. Perform ion implantation on a part of the region in each first P-type body region 051 to form a corresponding N+-type source region 07.

[0044] As shown in FIG. 7(e), in the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S50. Through photolithography and etching processes, a part of the oxide layer is etched away on each first P-type body region 051 to form an N+-type source region ion implantation window. N-type ions such as nitrogen ions are selectively implanted into the N+-type source region ion implantation window, and the energy of the ion implantation is 50 keV to 120 keV, so as to form an N+-type source region 07 with a corresponding depth of 0.3 μm to 0.5 μm, a width of 0.6 μm to 1.2 μm, and a doping concentration of 8e18 cm -3 ~2e19 cm -3 in each first P-type body region 051. The N+-type source region 07 is in contact with the N-type second silicon carbide epitaxial layer 04, and all the remaining oxide layer is etched away.

[0045] S70. Ion implantation is performed on another part of each first P-type body region 051 to form a second P-type body region 052 and a P-type deep doping region 06 from top to bottom; at this time, the second P-type body region 052 and the first P-type body region 051 are in a connected structure and are diagonally distributed.

[0046] As shown in FIG. 7(f), in the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S60. Through photolithography and etching processes, a P-type deep doping region ion implantation window is formed on each first P-type body region 051. P-type ions such as aluminum ions are selectively implanted into the P-type deep doping region ion implantation window, and the energy of the ion implantation is 100 keV to 800 keV, and more preferably the energy of the ion implantation is 500 keV, so as to form a P-type deep doping region 06 in the first P-type body region 051 and the N-type second silicon carbide epitaxial layer 04. A part of the first P-type body region 051 forms a second P-type body region 052 due to the influence of ion implantation. The ion doping concentration of the second P-type body region 052 is greater than that of the first P-type body region 051. The second P-type body region 052 and the first P-type body region 051 are in a connected structure and are diagonally distributed. At the same time, the depth of the deepest part of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 is greater than the depth of the deepest part of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04, and the doping concentration of the formed P-type deep doping region 06 gradually decreases longitudinally from bottom to top, and the doping concentration at the bottom of the P-type deep doping region 06 is 5 to 10 times that of the first P-type body region 051, and the doping concentration at the top of the P-type deep doping region 06 is 2.5 to 5 times that of the first P-type body region 051. Preferably, the depth of the deepest part of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 is 1.0 μm to 1.5 μm, and the width of the P-type deep doping region 06 is 0.5 μm to 0.8 μm; according to the doping situation of the first P-type body region 051, the doping concentration at the bottom of the P-type deep doping region 06 is 5e16 cm -3 ~5e17 cm -3, the doping concentration at the uppermost part of the P-type deep doping region 06 is 2.5e16 cm -3 ~2.5e17 cm -3 . Meanwhile, the horizontal distance between the P-type deep doping region 06 and the P-type buried layer 03 is 0.5 μm to 0.9 μm.

[0047] S80. Etch the N-type second silicon carbide epitaxial layer 04 near both ends of the device until it reaches the corresponding P-type buried layer 03 to form two gate trenches 08. Grow a gate oxide layer 09 in each gate trench 08, and deposit P-type polysilicon 10 on the gate oxide layer 09 and in the gate trench 08.

[0048] In the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S70, and through photolithography and etching processes, two gate trenches 08 are etched on the N-type second silicon carbide epitaxial layer 04 near both ends of the device. Each gate trench 08 penetrates through the N-type second silicon carbide epitaxial layer 04 until it reaches the corresponding P-type buried layer 03; then, as shown in FIG. 7(g), SiO2 is formed as the gate oxide layer 09 in each gate trench 08 by using a high-temperature furnace tube method; finally, as shown in FIG. 7(h), P-type polysilicon 10 is deposited on the gate oxide layer 09 and in the gate trench 08 by using the LPCVD (Low Pressure Chemical Vapor Deposition) process. At this time, the width of the P-type buried layer 03 on both sides of the gate trench 08 is 0.3 μm to 0.6 μm.

[0049] It should be noted here that FIGS. 7(g) and 7(h) are the cases of conventionally designing the device structure proposed by the present invention in the central region of the chip. For the case of designing the device structure proposed by the present invention in the edge region, based on FIG. 7(g), first, as shown in FIG. 7(i), part of the gate oxide layer 09 at the bottom of the two gate trenches 08 is etched off, and then, as shown in FIG. 7(j), P-type polysilicon 10 is deposited on the remaining gate oxide layer 09 and in the gate trench 08 by using the LPCVD process. At this time, the P-type polysilicon 10 at the bottom of the gate trench 08 forms an ohmic contact with the P-type buried layer 03.

[0050] S90. Form an interlayer insulating dielectric 11 on the N-type second silicon carbide epitaxial layer 04, the gate trench 08, and part of the N+-type source region 07 at both ends of the device.

[0051] As shown in Fig. 7(k), in the embodiment of the present invention, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is first used to deposit an interlayer insulating dielectric 11, such as SiO2, with a thickness of 1.0 μm to 1.2 μm, on the surface of the device obtained in S80; then, as shown in Fig. 7(l), through a photolithography process and an etching process, the interlayer insulating dielectric 11 on the middle region including all P-type second body regions, the N-type second silicon carbide epitaxial layer 04, and part of the N+-type source regions 07 is etched off.

[0052] It should be noted here that for the case where the device structure proposed in the present invention is designed in the edge region, based on Fig. 7(j), a PECVD process is first used to deposit and form the interlayer insulating dielectric 11 on the device surface, and then etching is carried out similar to Fig. 7(l), while continuing to etch off part of the interlayer insulating dielectric 11 on the gate trench 08. Finally, for the case where the device structure is designed in the edge region, the device structure formed after S90 is shown in Fig. 7(m).

[0053] S100: Etch the N-type second silicon carbide epitaxial layer 04 in the middle region to form a Schottky trench 12; the depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 and greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0054] As shown in Fig. 7(n), in the embodiment of the present invention, an oxide layer is deposited on the surface of the device obtained in S90, and the N-type second silicon carbide epitaxial layer 04 in the middle region is etched through a photolithography process and an etching process to form a Schottky trench 12. The depth of the Schottky trench 12 in the N-type second silicon carbide epitaxial layer 04 is less than the depth of the P-type deep doping region 06 in the N-type second silicon carbide epitaxial layer 04 and greater than the depth of the first P-type body region 051 in the N-type second silicon carbide epitaxial layer 04.

[0055] It should be noted here that for the case where the device structure proposed in the present invention is designed in the edge region, based on Fig. 7(m), as shown in Fig. 7(o), the N-type second silicon carbide epitaxial layer 04 in the middle region is etched to form a Schottky trench 12.

[0056] S101: Deposit source metal 13 in the Schottky trench 12, on all the interlayer insulating dielectrics 11, on all the second P-type body regions 052, and on the remaining all N+-type source regions 07.

[0057] As shown in Fig. 7(p), in the embodiment of the present invention, an electron beam evaporation process is adopted to deposit the source metal 13 in the Schottky trench 12, on all the interlayer insulating dielectrics 11, on all the second P-type body regions 052, and on all the remaining N+-type source regions 07. The material of the source metal 13 can be a metal combination of titanium / titanium nitride / aluminum laminated from bottom to top. At this time, the source metal 13 forms ohmic contacts with the second P-type body region 052 and the P-type heavily doped region 06 respectively; the source metal 13 forms a Schottky contact with the N-type second silicon carbide epitaxial layer 04.

[0058] Here, it should be noted that for the case where the device structure proposed in the present invention is designed in the edge region, as shown in Fig. 7(q), the source metal 13 is also deposited on some of the groove structures, so that the P-type polysilicon 10 in contact with the P-type buried layer 03 is connected to the source metal 13.

[0059] S102. Deposit the drain metal 14 on the lower surface of the silicon carbide substrate 01.

[0060] As shown in Fig. 7(r), in the embodiment of the present invention, an electron beam evaporation process is adopted to deposit the drain metal 14 with a thickness of 0.1 μm to 0.3 μm on the lower surface of the silicon carbide substrate 01. The material of the drain metal 14 can be a metal combination of titanium / nickel / silver laminated from the inside to the outside.

[0061] For the embodiment of the preparation method of the second aspect, since it is basically similar to the device embodiment of the first aspect, the description is relatively simple. For the relevant parts, refer to the partial description of the device embodiment of the first aspect.

[0062] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0063] Although the present invention has been described in conjunction with the embodiments herein, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases. Certain measures are recited in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0064] The above content is a further detailed description of the present invention in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A trench-type silicon carbide MOSFET device, characterized in that, The trench-type silicon carbide MOSFET device includes: A silicon carbide substrate (01); An N-type first silicon carbide epitaxial layer (02), located on the upper surface of the silicon carbide substrate (01); A P-type buried layer (03), located within the N-type first silicon carbide epitaxial layer (02) at both ends of the device; An N-type second silicon carbide epitaxial layer (04), located on the P-type buried layer (03) and the remaining N-type first silicon carbide epitaxial layer (02); Two gate trenches (08), respectively penetrating the N-type second silicon carbide epitaxial layer (04) near both ends of the device until within the corresponding P-type buried layer (03); a gate oxide layer (09) is provided on the inner wall of each gate trench (08), and P-type polysilicon (10) is provided on the gate oxide layer (09) and within the gate trench (08); Two N+-type source regions (07), located within the N-type second silicon carbide epitaxial layer (04) between the two gate trenches (08), and respectively in contact with the gate oxide layer (09) within one gate trench (08); Two first P-type body regions (051), respectively located within the N-type second silicon carbide epitaxial layer (04) below one N+-type source region (07), and in contact with the corresponding N+-type source region (07); Two second P-type body regions (052), located within the N-type second silicon carbide epitaxial layer (04) between the two N+-type source regions (07), and respectively in contact with the adjacent N+-type source region (07); Two P-type heavily doped regions (06), respectively located within the N-type second silicon carbide epitaxial layer (04) below one second P-type body region (052), and in contact with the corresponding second P-type body region (052) and in contact with the adjacent first P-type body region (051); at this time, the second P-type body region (052) and the first P-type body region (051) are in a connected structure and are diagonally distributed; An interlayer insulating dielectric (11), respectively located on the N-type second silicon carbide epitaxial layer (04) at both ends of the device, the gate trench (08), and part of the N+-type source region (07); A Schottky trench (12), located within the N-type second silicon carbide epitaxial layer (04) between the two P-type heavily doped regions (06); the depth of the Schottky trench (12) within the N-type second silicon carbide epitaxial layer (04) is less than the depth of the P-type heavily doped region (06) within the N-type second silicon carbide epitaxial layer (04), and greater than the depth of the first P-type body region (051) within the N-type second silicon carbide epitaxial layer (04); A source metal (13), located within the Schottky trench (12), on all the interlayer insulating dielectrics (11), on all the second P-type body regions (052), and on the remaining all N+-type source regions (07); A drain metal (14), located on the lower surface of the silicon carbide substrate (01).

2. The trench-type silicon carbide MOSFET device according to claim 1, wherein The P-type heavily doped region (06) is in a discontinuous structure.

3. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, The doping concentration of the P-type deep doping region (06) decreases successively from bottom to top in the longitudinal direction, and the doping concentration at the bottom of the P-type deep doping region (06) is 5 to 10 times the doping concentration of the first P-type body region (051), and the doping concentration at the top of the P-type deep doping region (06) is 2.5 to 5 times the doping concentration of the first P-type body region (051).

4. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, The doping concentration of the first P-type body region (051) is 1e16 cm -3 ~5e16 cm -3 .

5. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, The doping concentration of the second P-type body region (052) is greater than the doping concentration of the first P-type body region (051).

6. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, The depth corresponding to the deepest part of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04) is 1.0 μm to 1.5 μm, and the width of the P-type deep doping region (06) is 0.5 μm to 0.8 μm.

7. The trench-type silicon carbide MOSFET device according to claim 1 or 2, wherein The horizontal distance between the P-type deep doping region (06) and the P-type buried layer (03) is 0.5 μm to 0.9 μm; the width of the P-type buried layer (03) on both sides of the gate trench (08) is 0.3 μm to 0.6 μm.

8. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, The source metal (13) forms ohmic contacts with the second P-type body region (052) and the P-type deep doping region (06) respectively; the source metal (13) forms a Schottky contact with the N-type second silicon carbide epitaxial layer (04).

9. The trench-type silicon carbide MOSFET device according to claim 1 or 2, characterized in that, When the trench-type silicon carbide MOSFET device is in the edge region of the chip, the P-type polysilicon (10) at the bottom of the gate trench (08) penetrates through the gate oxide layer (09) to form an ohmic contact with the P-type buried layer (03); the source metal (13) penetrates through the interlayer insulating dielectric (11) to contact a part of the P-type polysilicon (10) in the gate trench (08).

10. A method for manufacturing a trench-type silicon carbide MOSFET device, characterized in that, The preparation method includes: Obtaining a silicon carbide substrate (01); Depositing an N-type first silicon carbide epitaxial layer (02) on the upper surface of the silicon carbide substrate (01); Performing ion implantation on the N-type first silicon carbide epitaxial layer (02) at both ends of the device to form a P-type buried layer (03); Depositing an N-type second silicon carbide epitaxial layer (04) on the P-type buried layer (03) and the N-type first silicon carbide epitaxial layer (02); Performing ion implantation on the N-type second silicon carbide epitaxial layer (04) to form two first P-type body regions (051); Performing ion implantation on a part of each first P-type body region (051) to form a corresponding N+-type source region (07); Performing ion implantation on another part of each first P-type body region (051) to form a second P-type body region (052) and a P-type deep doping region (06) from top to bottom; at this time, the second P-type body region (052) and the first P-type body region (051) are in a connected structure and are diagonally distributed, and the depth of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04) is greater than the depth of the first P-type body region (051) in the N-type second silicon carbide epitaxial layer (04); Etch the N-type second silicon carbide epitaxial layer (04) near both ends of the device until it reaches the corresponding P-type buried layer (03) to form two gate trenches (08). Grow a gate oxide layer (09) in each gate trench (08), and deposit P-type polysilicon (10) on the gate oxide layer (09) and in the gate trenches (08). Form an interlayer insulating dielectric (11) on the N-type second silicon carbide epitaxial layer (04), gate trenches (08), and partial N+-type source regions (07) at both ends of the device respectively. Etch the N-type second silicon carbide epitaxial layer (04) in the middle region to form a Schottky trench (12); the depth of the Schottky trench (12) in the N-type second silicon carbide epitaxial layer (04) is less than the depth of the P-type deep doping region (06) in the N-type second silicon carbide epitaxial layer (04), and greater than the depth of the first P-type body region (051) in the N-type second silicon carbide epitaxial layer (04). Deposit source metal (13) in the Schottky trench (12), on all interlayer insulating dielectrics (11), on all second P-type body regions (052), and on all remaining N+-type source regions (07). Deposit drain metal (14) on the lower surface of the silicon carbide substrate (01).

Images