Super junction MOSFET device

Abstract

The invention relates to a super junction MOSFET device, and belongs to the field of power semiconductor devices. The device comprises a substrate structure, an active top silicon structure, a semi-surrounded trench gate structure and a deep source trench structure. Wherein the substrate structure and the active top silicon structure mainly form a main body voltage-withstanding structure of the device, the main body voltage-withstanding structure and the half-surrounded trench gate structure are combined to form an MOS forward-conducting electron channel, and one-dimensional voltage withstanding is converted into super-junction two-dimensional charge balance, so that the surface electric field can be reduced, and the voltage withstanding capability of the device can be enhanced; and meanwhile, the main body voltage withstanding structure and the deep source trench structure form a reverse conducting MOS channel diode, so that the turn-on voltage of the device during reverse conducting is reduced, hole injection during reverse conducting is inhibited, the reverse recovery time is shortened, and the reverse loss is reduced.

Description

Technical Field

[0001] The invention belongs to the field of power semiconductor devices and relates to a super junction MOSFET device. Background Art

[0002] As the core representative of the third-generation semiconductor materials, silicon carbide MOSFET devices have become an ideal choice for high-voltage, high-frequency, and high-temperature scenarios due to their excellent physical properties. Compared with traditional silicon-based MOSFETs, SiC MOSFETs have significant advantages in low loss and high efficiency, high temperature resistance, high voltage, and good high-frequency characteristics. In recent years, with the maturity of material preparation and process technology, the cost of SiC MOSFET has dropped by more than 50% compared to the early days, pushing it from the laboratory to large-scale application, with core applications in new energy vehicles, renewable energy, and industrial and power supply fields.

[0003] Superjunction MOSFET has broken through the bottleneck of the traditional VDMOS on-resistance increasing sharply with the increase of withstand voltage through the innovative alternating PN column structure (such as Infineon CoolMOS technology), and achieved low loss characteristics under high voltage. Its core advantages include cost-effective high-voltage solutions and diversified processes, which are manifested in two major technical routes: multiple epitaxy and deep trench etching. The core applications are consumer electronics and industrial power supplies, as well as electric vehicles and energy storage.

[0004] Silicon carbide superjunction MOSFET technology combines the advantages of wide bandgap materials with innovative device structures, and demonstrates irreplaceable performance advantages in high-voltage, high-frequency, and high-temperature scenarios. With the maturity of technology and cost optimization, its application is penetrating from high-end fields to consumer electronics, industrial power supplies and other scenarios, becoming the core force to promote energy conversion efficiency and power density revolution. In the future, with the deepening of industrial chain collaboration and the explosion of market demand, this technology field is expected to usher in a new round of growth, helping to accelerate the global low-carbon process.

[0005] Similar to the conventional Trench MOSFET structure, asymmetric trench ATMOS (Asymmetric Trench Metal-Oxide-Semiconductor) is a relatively new structural design in silicon carbide power devices. It has very low on-resistance and high switching speed. Its characteristics include high input impedance, low driving power, excellent frequency characteristics and good thermal stability. The ATMOS structure is asymmetric in the shape and layout of the trench, which can effectively reduce the turn-on voltage. The structural design of the ATMOS device makes it suitable for power electronics applications in high-power, high-frequency and high-temperature environments. Asymmetric trench ATMOS is different from conventional ATMOS structures (such as Figure 3Compared with the one shown ( , it has many performance advantages, such as lower turn-on voltage, lower on-resistance, and low gate-drain charge density, resulting in low on-state and switching losses and fast switching speed. At the same time, since the channel of the Trench MOSFET is vertical, its channel density can be further increased and the chip size can be reduced. For related content, see the reference: Ta LB, Hobgood HM, Thomas RN. Evidence of the role of boron in undoped GaAs grown by liquid encapsulated Czochralski[J]. Applied Physics Letters, 1982, 41(11): 1091-1093.

[0006] There is also an attempt to fully improve the power density of SiC MOS devices by using the charge balance principle, that is, to reduce the specific on-resistance Rsp. Some literature has proposed SiC MOS with a superjunction structure. It forms the P-columns of the superjunction through multiple epitaxial growths and high-temperature implantation of P-type impurities, and a Trench gate is formed between them. Due to the Trench gate between the P-columns in this structure design, it is difficult to reduce the cell size, so it is also difficult to greatly reduce Rsp. At the same time, for SiC materials, multiple epitaxial growths and implantations will cause a rapid increase in cost, and at the same time, the defect density will also increase rapidly, making it difficult to improve the yield and reliability of the chips. For related content, see the reference: HARADA S, KOBAYASHI Y, KYOGOKU S, et al. First demonstration of dynamic characteristics for SiC superjunction MOSFET realized using multi-epitaxial growth method[C] / / IEEE. 2018 IEEE International Electron Devices Meeting. San Francisco: IEEE, 2018: 8.2.1-8.2.4.

[0007] In summary, the following problems exist in the current prior art:

[0008] 1. Since the ATMOS requires high-energy ion implantation due to its asymmetric shielding structure, it will damage the surface of the wafer during the process.

[0009] 2. The drift region of the ATMOS is one-dimensional depletion, which limits the relationship between the on-resistance and the breakdown voltage.

[0010] 3. In the existing SiC superjunction MOSFET, the method of using trench injection to protect the P+ region will increase the chip surface area and introduce the P+ region to the source electrode additionally.

[0011] 4. The superjunction MOSFET has a natural reverse recovery characteristic problem. Summary of the Invention

[0012] In view of this, the purpose of the present invention is to provide a superjunction MOSFET device, which realizes the relationship between the modulation breakdown voltage and the on-resistance, can make the doping of the drift region larger under the same breakdown voltage, slow down the JFET effect, improve the electrode lead-out of the P+ protection region, and optimize the device structure.

[0013] To achieve the above object, on the one hand, the present invention provides a silicon carbide-based superjunction MOSFET device, which includes: an N-type substrate; an N- drift region formed on the surface of the N-type substrate; a current spreading layer formed on the surface of the N- drift region; a P-type base region formed on the surface of the current spreading layer; a first N+ source region formed on the P-type base region; a drain contact and an embedded source contact formed at the bottom and top of the device respectively. In addition, the device further includes a semi-surrounding trench gate structure and a deep source trench structure.

[0014] Among them, the semi-surrounding trench gate structure penetrates through the P-type base region and the current spreading layer, divides the P-type base region and the current spreading layer into two parts, and the semi-surrounding trench gate structure is embedded in the N- drift region; the deep source trench structure is located on the surface of the current spreading layer and is separated from the semi-surrounding trench gate structure by the P-type base region; the semi-surrounding trench gate structure and the N- drift region form a superjunction to enhance the breakdown voltage of the device; the deep source trench structure provides a MOS channel diode to reduce the turn-on voltage of the device in reverse conduction and suppress the hole injection when the device conducts in reverse; an ohmic contact is formed between a part of the P-type base region below the first N+ source region and the embedded source contact to reduce the on-resistance.

[0015] Furthermore, the semi-surrounding trench gate structure includes a gate oxide layer, a gate contact, a P+ region at the bottom of the gate oxide layer, a P-pillar, and a P+ source region.

[0016] Wherein, the P-pillar penetrates through the current spreading layer and is embedded in the N-drift region, and forms a superjunction structure with the N-drift region; the gate oxide layer is located above the P-pillar and separates the P-type base region into two parts; the P+ region at the bottom of the gate oxide layer is located between the gate oxide layer and the P-pillar; the P+ source region is located on the surface of a part of the P-type base region, and the first N+ source region is located on the surface of the other part of the P-type base region; the P+ source region forms an ohmic contact with the embedded source electrode, enabling the P+ region at the bottom of the gate oxide layer and the P-pillar to be connected to zero potential.

[0017] Furthermore, the deep source trench structure includes a source oxide layer, a polysilicon source electrode, a semi-surrounding P+ region, and a second N+ source region.

[0018] Wherein, the semi-surrounding P+ region is located on the surface of the current spreading layer and is adjacent to a part of the P-type base region; the semi-surrounding P+ region wraps the source oxide layer in a semi-surrounding manner; the side of the source oxide layer not wrapped by the semi-surrounding P+ region is adjacent to the other part of the P-type base region; the polysilicon source electrode is located in the source oxide layer and is directly connected to the embedded source electrode in contact; the second N+ source region is located between the P-type base region and the source oxide layer and forms an ohmic contact with the embedded source electrode to collect electron current during the reverse conduction of the device.

[0019] Furthermore, in this silicon carbide MOSFET device, except for the metal electrodes, oxide layers, and polysilicon, other parts are all made of silicon carbide material.

[0020] On the other hand, the present invention provides a silicon-based superjunction MOSFET device, which includes: an N-type substrate; an N-drift region formed on the surface of the N-type substrate; a current spreading layer formed on the surface of the N-drift region; a P-type base region formed on the surface of the current spreading layer; a first N+ source region formed in the P-type base region; a drain contact and an embedded source contact respectively formed at the bottom and top of the device. In addition, the device further includes a semi-surrounding trench gate structure, a deep source trench structure, and an N-type buffer layer located between the N-type substrate and the N-drift region.

[0021] Among them, the semi-surrounding trench gate structure penetrates through the P-type base region and the current spreading layer, divides the P-type base region and the current spreading layer into two parts, and the semi-surrounding trench gate structure is embedded in the N-drift region; the deep source trench structure is located on the surface of the current spreading layer and is separated from the semi-surrounding trench gate structure by the P-type base region; the semi-surrounding trench gate structure and the N-drift region form a super junction to enhance the device breakdown voltage; the deep source trench structure provides a MOS channel diode to reduce the turn-on voltage of the device during reverse conduction and suppress the hole injection during device reverse conduction; a body contact is formed between a part of the P-type base region below the first N+ source region and the embedded source contact to suppress the parasitic diode, and the influence of the MOS channel diode on the device reverse recovery characteristic can be modulated by changing the length of the body contact, so that the two act together to increase the device stability.

[0022] Further, the semi-surrounding trench gate structure includes a gate oxide layer, a gate contact, a P-pillar, and a P+ source region.

[0023] Among them, the P-pillar penetrates through the current spreading layer and is embedded in the N-drift region, and forms a super junction structure with the N-drift region; the gate oxide layer is located above the P-pillar and separates the P-type base region into two parts; the P+ source region is located on the surface of a part of the P-type base region, and the first N+ source region is located on the surface of the other part of the P-type base region; the P+ source region and the embedded source contact form an ohmic contact to connect the P-pillar to zero potential.

[0024] Further, the deep source trench structure includes a source oxide layer, a polysilicon source electrode, a P+ region, and a second N+ source region.

[0025] Among them, the source oxide layer is located on the surface of the current spreading layer, and both sides of the source oxide layer are adjacent to the P-type base region; the polysilicon source electrode is located in the source oxide layer and is directly connected to the embedded source contact; the second N+ source region is located on one side of the source oxide layer and is between the P-type base region and the source oxide layer, and the second N+ source region and the embedded source contact form an ohmic contact to collect the electron current during device reverse conduction; the P+ region is located on the other side of the source oxide layer and is between the P-type base region and the source oxide layer.

[0026] Further, in this device, except for metal electrodes, oxide layers, and polysilicon, other parts are all made of silicon materials.

[0027] The beneficial effects of the present invention are as follows:

[0028] (1) In the silicon carbide superjunction MOSFET device provided by the present invention, an asymmetric shielding structure, i.e., the P+ protection region under the gate oxide layer and the source oxide layer, is formed by adopting the method of trench etching plus angled implantation, so as to protect the oxide layer under high electric fields and prevent the oxide layer from being broken down. In addition, the P+ protection region at the bottom of the gate oxide layer is connected to the source through the superjunction structure, and the semi-surrounding P+ protection region under the source oxide layer is directly connected to the source, thereby realizing the electrical connection between the P+ protection region and the source inside the device, improving the electrode lead-out method of the P+ protection region, and avoiding additional increase in chip area.

[0029] The superjunction structure is jointly formed by the P-pillar in the semi-surrounding trench gate structure and the N-drift region. On the one hand, it can serve as an electron channel for the forward conduction of the MOSFET. On the other hand, it can convert the one-dimensional breakdown voltage into the two-dimensional charge balance of the superjunction, reduce the surface electric field, and enhance the breakdown voltage ability of the device.

[0030] The MOS channel diode is introduced through the deep source trench structure. The MOS channel diode is connected to the two electrodes through the second N+ source region and the N-drift region. When the device conducts in the reverse direction, the MOS channel diode can reduce the turn-on voltage of the reverse conduction; at the same time, since the second N+ source region forms an ohmic contact with the source, it can collect the electron current during the reverse conduction. Based on the higher mobility of electrons compared to holes, on the one hand, it can suppress the injection of non-equilibrium minority carriers and reduce the influence of the superjunction structure on the reverse recovery characteristics of the device. On the other hand, electrons can be extracted from the device interior as soon as possible, thereby reducing the reverse recovery time and reverse loss.

[0031] (2) In the silicon-based superjunction MOSFET device provided by the present invention, similarly, the superjunction structure is jointly formed by the P-pillar in the semi-surrounding trench gate structure and the N-drift region, converting the one-dimensional breakdown voltage into the two-dimensional charge balance of the superjunction, reducing the surface electric field, and enhancing the breakdown voltage ability of the device; the MOS channel diode is introduced through the deep source trench structure, reducing the turn-on voltage of the device in reverse conduction, realizing the suppression of the injection of non-equilibrium minority carriers, reducing the influence of the superjunction structure on the reverse recovery characteristics of the device, and at the same time reducing the reverse recovery time and reverse loss.

[0032] In addition, by making the P-type base region form a body contact with the source to suppress the parasitic diode, and the influence of the built-in MOS channel diode on the reverse recovery characteristics can be modulated by changing the length of the body contact, so that the two act together to increase the stability of the device. Additionally, by growing a high-concentration N-type buffer layer under the N-drift region, a concentration difference is formed in combination with the extremely low-doped region at the bottom of the N-drift region, thereby delaying the recovery stage time of the reverse recovery and increasing the softness factor, thus reducing the oscillation caused by the built-in MOS channel diode.

[0033] Other advantages, objects, and features of the present invention will be set forth in part in the following description, and in part will be obvious to those skilled in the art from a study of the following, or may be learned by practice of the invention. The objects and other advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings. Among them:

[0035] Figure 1 Schematic diagram of the MOSFET device structure provided in Embodiment 1 of the present invention;

[0036] Figure 2 Schematic diagram of the MOSFET device structure provided in Embodiment 2 of the present invention;

[0037] Figure 3 Schematic diagram of a typical conventional ATMOS device structure.

[0038] Reference numerals: 1 - N-type substrate; 2 - N-drift region; 3 - P-pillar; 4 - polysilicon source electrode; 5 - semi-surrounding P+ region; 6 - P-type base region; 7 - first N+ source region; 8 - gate oxide layer; 9 - gate contact; 10 - P+ region at the bottom of the gate oxide layer; 11 - P+ source region on the right side of the gate; 12 - embedded source contact; 13 - second N+ source region; 14 - source oxide layer; 15 - current spreading layer; 16 - drain contact; 17 - N-type buffer layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0039] The following illustrates the embodiments of the present invention through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention schematically. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0040] Among them, the drawings are only for illustrative purposes and show only schematic diagrams, not physical diagrams, and should not be construed as a limitation on the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged, or reduced, and do not represent the dimensions of actual products; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0041] In the accompanying drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the accompanying drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the accompanying drawings are only for illustrative purposes and should not be construed as limiting the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0042] To solve the problems existing in the prior art, the present invention proposes a superjunction MOSFET device. Combining the superjunction MOSFET structure, it makes better use of the semi-surrounding structure of ATMOS and penetrates into the drift region, thereby further modulating the relationship between the breakdown voltage and the on-resistance. Under the same breakdown voltage, a larger doping in the drift region can be achieved, and the JFET effect can be mitigated. Since the introduction of the superjunction structure will increase the overlapping area of the body diode PN junction and increase the number of non-equilibrium minority carriers in the on-state, affecting the reverse recovery characteristics, an internal MOS channel diode is introduced to suppress the injection of non-equilibrium minority carriers. Only the electron channel conducts, and electrons have a higher mobility and can be quickly extracted from the device interior. In addition, the deep source trench of this device takes advantage of the characteristics that the trench and the superjunction structure are directly connected to the source, and improves the electrode lead-out of the P+ protection region.

[0043] Embodiment 1

[0044] As Figure 1 shown, it is a silicon carbide superjunction MOSFET device provided in this embodiment. The device includes a substrate structure, an active top silicon structure, a semi-surrounding trench gate structure, and a deep source trench structure. Among them, the substrate structure and the active top silicon structure are in contact with each other up and down to form the main body breakdown voltage structure of the device. The main body breakdown voltage structure is combined with the semi-surrounding trench gate structure to form an electron channel for MOS forward conduction, and converts the one-dimensional breakdown voltage into the two-dimensional charge balance of the superjunction, which can reduce the surface electric field. In addition, the use of the superjunction structure can also enhance the breakdown voltage of the device; at the same time, the main body breakdown voltage structure and the deep source trench structure form a reverse-conducting MOS channel diode, which reduces the turn-on voltage when the device conducts in the reverse direction, suppresses the hole injection when conducting in the reverse direction, reduces the reverse recovery time, and thus reduces the reverse loss.

[0045] The substrate structure described above includes a high-concentration N-type substrate 1 and a drain contact 16; the active top-layer silicon structure includes an N-drift region 2, a current spreading layer 15, a P-type base region 6, and a first N+ source region 7; the semi-surrounding trench gate structure includes a gate oxide layer 8, a gate contact 9, a P+ region 10 at the bottom of the gate oxide layer, a P-pillar 3, and a P+ source region 11 on the right side of the gate; the deep source trench structure includes a polysilicon source electrode 4, a source oxide layer 14, a semi-surrounding P+ region 5, and a second N+ source region 13.

[0046] The substrate structure and the active top-layer silicon structure are in vertical contact to form the device body breakdown voltage structure and serve as the structural support of the device. Among them, the high-concentration N-type substrate 1 is placed on top of the drain contact 16; the N-drift region 2 is placed above the N-type substrate 1 and is in vertical contact with the current spreading layer 15, playing a major role in breakdown voltage; the P-type base region 6 is located above the current spreading layer 15. A PN junction is formed between the P-type base region 6 and the current spreading layer 15 due to different doping types. The central position is separated by the semi-surrounding trench gate structure. The top of the left-side P-type base region 6 after separation contacts the first N+ source region 7, forming an ohmic contact with the embedded source contact 12 to reduce the on-resistance.

[0047] The semi-surrounding trench gate structure mainly uses the superjunction structure to enhance the device breakdown voltage. From top to bottom, it includes the gate oxide layer 8 under the source coverage, the gate contact 9 is wrapped in the gate oxide layer 8, the P+ region 10 at the bottom of the gate oxide layer to protect the oxide layer, and the P-pillar 3 that penetrates the current spreading layer 15 and the N-drift region 2. In addition, there is a P+ source region 11 on the top of the right-side P-type base region 6. The P+ source region 11 on the right side of the gate forms an ohmic contact with the embedded source contact 12, making the P+ region 10 at the bottom of the gate oxide layer and the P-pillar 3 access the zero potential. Among them, the P-pillar 3 and the N-drift region 2 together constitute the superjunction structure of the device to achieve enhanced device breakdown voltage.

[0048] The deep source trench structure provides a MOS channel diode. This structure includes a source oxide layer 14 that surrounds the polysilicon source electrode 4. The top of the source oxide layer 14 and the polysilicon source electrode 4 are both directly connected to the embedded source contact 12. There is a semi-surrounding P+ region 5 at the bottom and half of the side of the source oxide layer 14 to protect the source oxide layer 14 under high electric fields; for the source oxide layer 14 on the right side of the device, its upper left corner is directly in contact with the second N+ source region 13. The top of the second N+ source region 13 forms an ohmic contact with the embedded source contact 12 to collect the electron current during reverse conduction. This MOS channel diode is connected to the electrode through the second N+ source region 13 and the N-type substrate 1.

[0049] It should be noted that for the description of the deep source trench structure, although in Figure 1In [the device], the source oxide layer 14 and the polysilicon source electrode 4 seemingly distribute on both sides of the device. However, after cell arrangement, the source oxide layer 14 is actually a trench, and the polysilicon source electrode 4 is formed in the trench.

[0050] In addition, in this silicon carbide MOSFET device, except for the metal electrodes, oxide layers, and polysilicon related to electrode contact, the rest is SiC semiconductor material.

[0051] Embodiment 2

[0052] As Figure 2 shown is the MOSFET device provided in this embodiment. Compared with the device in Embodiment 1, the silicon carbide material is replaced with silicon material in the device provided in this embodiment.

[0053] Based on the material replacement, in the MOSFET device provided in this embodiment, the P+ region 10 at the bottom of the gate oxide layer can be cancelled, and the semi-surrounding P+ region 5 can be improved so that it only needs to be implanted within the normal range, reducing the process difficulty.

[0054] In addition, the first N+ source region 7 at the top and the P+ source region 11 on the right side of the gate can reduce the implantation energy and dose, so that the P-type base region 6 and the embedded source contact 12 directly form a body contact to suppress the parasitic diode, and the influence of the built-in MOS channel diode on the reverse recovery characteristics can be modulated by changing the length of the body contact, making the two work together to increase the stability of the device.

[0055] Since the device structure provided in this embodiment introduces non-equilibrium minority carriers during reverse conduction, the main process can adopt the multi-layer epitaxial method to grow the superjunction structure, generating a high-concentration N-type buffer layer 17 between the N-type substrate 1 and the N- drift region 2, combining with the extremely low-doped region at the bottom of the N- drift region 2 to form a concentration difference, delaying the recovery stage time of reverse recovery, increasing the softness factor, and thus reducing the oscillation.

[0056] The MOSFET device provided in this embodiment solves the problem of poor reverse recovery caused by introducing the superjunction structure in the MOS device by introducing the built-in MOS channel diode, and also solves the problems of instability and large oscillation caused by introducing the built-in MOS channel diode by improving the source contact depth and adding a buffer layer.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the purpose and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A superjunction MOSFET device, the device comprising: N-type substrate; N-drift region formed on the surface of the N-type substrate; Current spreading layer formed on the surface of the N-drift region; P-type base region formed on the surface of the current spreading layer; First N+ source region formed in the P-type base region; drain contact and embedded source contact formed at the bottom and top of the device respectively; It is characterized in that the device further includes a semi-surrounding trench gate structure and a deep source trench structure; the semi-surrounding trench gate structure penetrates through the P-type base region and the current spreading layer, divides the P-type base region and the current spreading layer into two parts, and is embedded in the N-drift region; the deep source trench structure is located on the surface of the current spreading layer and is separated from the semi-surrounding trench gate structure by the P-type base region; the semi-surrounding trench gate structure and the N-drift region form a superjunction to enhance the breakdown voltage of the device; the deep source trench structure provides a MOS channel diode to reduce the turn-on voltage of the reverse conduction of the device and suppress the hole injection during the reverse conduction of the device; An ohmic contact is formed between a part of the P-type base region below the first N+ source region and the embedded source contact to reduce the on-resistance.

2. The superjunction MOSFET device according to claim 1, characterized in that, The semi-surrounding trench gate structure includes a gate oxide layer, a gate contact, a P+ region at the bottom of the gate oxide layer, a P-pillar, and a P+ source region; the P-pillar penetrates through the current spreading layer and is embedded in the N-drift region, and forms a superjunction structure with the N-drift region; the gate oxide layer is located above the P-pillar and separates the P-type base region into two parts; the P+ region at the bottom of the gate oxide layer is located between the gate oxide layer and the P-pillar; the P+ source region is located on the surface of a part of the P-type base region, and the first N+ source region is located on the surface of another part of the P-type base region; The P+ source region and the embedded source contact form an ohmic contact to make the P+ region at the bottom of the gate oxide layer and the P-pillar access zero potential.

3. The superjunction MOSFET device according to claim 1, wherein The deep source trench structure includes a source oxide layer, a polysilicon source electrode, a semi-surrounding P+ region, and a second N+ source region; the semi-surrounding P+ region is located on the surface of the current spreading layer and is adjacent to a part of the P-type base region; the semi-surrounding P+ region wraps the source oxide layer in a semi-surrounding manner; the side of the source oxide layer not wrapped by the semi-surrounding P+ region is adjacent to another part of the P-type base region; the polysilicon source electrode is located in the source oxide layer and is directly connected to the embedded source contact; the second N+ source region is located between the P-type base region and the source oxide layer and forms an ohmic contact with the embedded source contact to collect electron current during the reverse conduction of the device.

4. The superjunction MOSFET device according to any one of claims 1 to 3, characterized in that, In this device, except for metal electrodes, oxide layers, and polysilicon, other parts are made of silicon carbide materials.

5. A super junction MOSFET device, the device comprising: N-type substrate; N-drift region formed on the surface of the N-type substrate; Current spreading layer formed on the surface of the N-drift region; P-type base region formed on the surface of the current spreading layer; First N+ source region formed in the P-type base region; drain contact and embedded source contact formed at the bottom and top of the device respectively; It is characterized in that the device further includes a semi-surrounding trench gate structure, a deep source trench structure, and an N-type buffer layer located between the N-type substrate and the N-drift region; the semi-surrounding trench gate structure penetrates through the P-type base region and the current spreading layer, divides the P-type base region and the current spreading layer into two parts, and is embedded in the N-drift region; the deep source trench structure is located on the surface of the current spreading layer and is separated from the semi-surrounding trench gate structure by the P-type base region; the semi-surrounding trench gate structure and the N-drift region form a superjunction to enhance the breakdown voltage of the device; the deep source trench structure provides a MOS channel diode to reduce the turn-on voltage of the reverse conduction of the device and suppress the hole injection during the reverse conduction of the device. A body contact is formed between a part of the P-type base region under the first N+ source region and the embedded source contact to suppress the parasitic diode, and the MOS channel diode is modulated by changing the length of the body contact.

6. The superjunction MOSFET device according to claim 5, characterized in that, The semi-surrounding trench gate structure includes a gate oxide layer, a gate contact, a P-pillar, and a P+ source region; the P-pillar penetrates through the current spreading layer and is embedded in the N-drift region, and forms a superjunction structure with the N-drift region; the gate oxide layer is located above the P-pillar and separates the P-type base region into two parts; the P+ source region is located on the surface of a part of the P-type base region, and the first N+ source region is located on the surface of the other part of the P-type base region; the P+ source region and the embedded source contact form an ohmic contact to connect the P-pillar to zero potential.

7. The superjunction MOSFET device according to claim 5, wherein The deep source trench structure includes a source oxide layer, a polysilicon source electrode, a P+ region, and a second N+ source region; the source oxide layer is located on the surface of the current spreading layer, and both sides of the source oxide layer are adjacent to the P-type base region; the polysilicon source electrode is located in the source oxide layer and is directly connected to the embedded source contact; the second N+ source region is located on one side of the source oxide layer and is between the P-type base region and the source oxide layer, and the second N+ source region and the embedded source contact form an ohmic contact to collect the electron current during the reverse conduction of the device; the P+ region is located on the other side of the source oxide layer and is between the P-type base region and the source oxide layer.

8. The superjunction MOSFET device according to any one of claims 5 to 7, characterized in that, In this device, except for the metal electrodes, oxide layers, and polysilicon, other parts are made of silicon materials.

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