SiC super junction and preparation method and application thereof

Abstract

The invention relates to a SiC super junction and a preparation method and application thereof. The SiC super junction comprises a SiC substrate, an N-type 4H-SiC buffer layer and an N-type 4H-SiC epitaxial layer provided with a groove which are arranged in sequence. The trench is filled with a P-type GaN epitaxial layer, and the thickness of the P-type GaN epitaxial layer is the same as the depth of the trench; the MOSFET device prepared by the SiC super junction shows relatively low specific on-resistance and relatively high breakdown voltage, the specific on-resistance is preferably lower than 0.94 m omega.mm < 2 >, the breakdown voltage is preferably higher than 1745V, no cavity is generated in a groove, and the application requirement of the device in an extreme environment is met; and the preparation process is simple, the cost is low, and large-scale production can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly to a SiC superjunction and its preparation method and application. Background Art

[0002] As a typical representative of the third-generation semiconductor materials, silicon carbide (SiC) has superior characteristics such as high breakdown electric field, high thermal conductivity, high electron saturation velocity, and strong radiation resistance compared with the first two generations of semiconductor materials, and is more suitable for manufacturing high-temperature, high-frequency, and radiation-resistant power devices. As an important SiC power device, the SiC power-metal oxide semiconductor field-effect transistor (MOSFET) is widely used in power electronic systems due to its advantages such as a simple gate drive circuit, high operating frequency, high power density, and high conversion efficiency. In recent years, remarkable progress has been made in the research of 4H-SiC MOSFET at home and abroad. Among them, one of the important directions for the optimization and progress of SiC device MOSFET is to continuously reduce the specific on-resistance of the device.

[0003] The superjunction technology is a technology that realizes charge compensation by adopting an alternating structure of P-type doped regions and N-type doped regions and serves as a breakdown voltage layer to simultaneously obtain a low specific on-resistance and a high breakdown voltage capability. Obviously, it is the most effective means to reduce the specific on-resistance of the drift region. Currently, the main method for obtaining SiC superjunctions is the trench etching-epitaxial backfilling technology, and its basic process flow is as follows: grow an N-type thick epitaxial layer on an N+-type silicon substrate, then etch deep trenches on the thick epitaxial layer, then add a mask on the top of the trench mesa, and finally fill the trenches with a P-type epitaxial layer, and then use chemical mechanical polishing to flatten the surface.

[0004] For example, CN 116564986A discloses a method for filling trenches. First, a silicon seed layer is formed on the trench surface by an epitaxial deposition process using a pure silicon source, and then a second epitaxial layer is formed by a low-pressure epitaxial deposition process. The improvement degree of this method for trench defects still has a large room for improvement, the device performance has not been significantly improved, and the filling method is complex and the cost is high.

[0005] CN 113078050B discloses a C-plane SiC epitaxial structure and a method for filling epitaxial trenches. The post-treatment process of the filling method still uses a polishing method, and the growth temperature of the epitaxial layer inside and outside the trenches is relatively high, which has a great influence on the trench morphology and surface quality of the C-plane SiC epitaxial structure. Moreover, under low-pressure growth conditions, the filling is not firm, thus affecting the consistency and reliability of the device.

[0006] Therefore, to solve the defects of trench morphology change, poor device surface quality or voids in filling caused by over-etching in the existing technology, there is an urgent need in the art to provide a new method for preparing SiC superjunction to successfully prepare an SiC superjunction with low specific on-resistance and high breakdown voltage resistance, thereby promoting the further development of the semiconductor device manufacturing field. Summary of the Invention

[0007] To solve the above technical problems, the present invention provides an SiC superjunction, a preparation method and an application thereof, which can avoid the problem that the trench morphology is etched due to high growth temperature during filling, effectively solve the phenomenon of voids generated due to the growth of the channel layer, and avoid using the chemical mechanical polishing surface flattening method, reducing the process flow and the preparation cost.

[0008] To achieve this purpose, the present invention adopts the following technical solutions:

[0009] In a first aspect, the present invention provides an SiC superjunction, which includes an SiC substrate, an N-type 4H-SiC buffer layer arranged in sequence, and an N-type 4H-SiC epitaxial layer provided with trenches; a P-type GaN epitaxial layer is filled in the trenches, and the thickness of the P-type GaN epitaxial layer is the same as the depth of the trenches.

[0010] The SiC superjunction of the present invention adopts the trench etching-epitaxial filling technology, combines the design of the N-type 4H-SiC buffer layer, the N-type 4H-SiC epitaxial layer provided with trenches and the P-type GaN epitaxial layer filled in the trenches to jointly optimize the structure of the SiC superjunction, thereby optimizing the electric field distribution, reducing the on-resistance, improving the breakdown voltage resistance, significantly enhancing the performance of the device. At the same time, the thickness of the P-type GaN epitaxial layer is designed to be the same as the depth of the trenches to optimize the shape and size of the trenches, reduce the leakage current, optimize the charge balance, and ensure the compatibility of subsequent processes.

[0011] The present invention selects to fill the P-type GaN epitaxial layer in the trenches. Compared with the traditional structure of filling the P-type SiC epitaxial layer in the trenches, on the one hand, due to the lower growth temperature of the P-type GaN epitaxial layer, it is ensured that the trench morphology will not change due to high temperature during the filling process, and voids will not be generated, which affects the consistency and reliability of the device; on the other hand, it is also beneficial to the post-treatment steps. The P-type GaN epitaxial layer exceeding the N-type 4H-SiC epitaxial layer after filling is easy to be etched and removed, avoiding the generation of voids during the growth of the channel layer after trench filling, and it can be removed without using chemical mechanical polishing, ensuring the surface quality of the SiC superjunction. Therefore, the present invention selects to fill the P-type GaN epitaxial layer in the trenches to avoid the generation of voids in the trenches, improve the performance of the SiC superjunction device, simplify the preparation process, and reduce the preparation cost.

[0012] It should be noted that the growth of 4H-SiC requires strict step flow for growth, and the growth temperature needs to be above 1600 °C. Voids are likely to be generated during growth in the trench; however, GaN has three growth modes: layer growth mode, island growth mode, and layer growth first and then island growth mode. Therefore, there are multiple growth modes for growing GaN in the trench, thus avoiding the generation of voids in the trench.

[0013] Preferably, the thickness of the SiC substrate is 300 - 500 μm, for example, it can be 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc.

[0014] Preferably, the thickness of the N-type 4H-SiC buffer layer is 0.5 - 1 μm, for example, it can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm, etc.

[0015] The present invention further preferably sets the thickness of the N-type 4H-SiC buffer layer to be 0.5 - 1 μm, which is beneficial to the stability of defects; if the thickness of the N-type 4H-SiC buffer layer is too thin, the number of triangular defects will increase; if the thickness of the N-type 4H-SiC buffer layer is too thick, the number of falling objects will increase.

[0016] Preferably, the thickness of the N-type 4H-SiC epitaxial layer is 5 - 11 μm, for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, etc.

[0017] The thickness of the N-type 4H-SiC epitaxial layer provided with trenches in the present invention refers to its maximum thickness, that is, the thickness from its uppermost edge to its lowermost edge, rather than the thickness from the bottom of the trench to the lowermost edge.

[0018] Preferably, the depth-to-width ratio of the trench is (3 - 10):1, for example, it can be 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc.

[0019] Among them, the depth-to-width ratio is the ratio of the depth of the trench to the width of the trench.

[0020] The present invention further preferably sets the depth-to-width ratio of the trench to be (3 - 10), so that the conductivity of the device is stronger, the specific on-resistance is smaller, and the breakdown voltage resistance ability is stronger.

[0021] Preferably, the depth of the trench is 2 - 11 μm, for example, it can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, etc.

[0022] Preferably, the upper and lower widths of the groove are independently 0.6-1.1 μm, for example, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm or 1.1 μm.

[0023] Preferably, the inclination angle of the sidewall of the groove is 85° to 90°, for example, 85°, 86°, 87°, 88°, 89°, or 90°.

[0024] The sidewall inclination angle of the groove refers to the angle between the sidewall of the groove and the horizontal direction pointing to the inside of the groove.

[0025] Preferably, the doping concentration of N element in the N-type 4H-SiC buffer layer is 0.5×10 18 ~2×10 18 atom / cm 3 , for example, it can be 0.5×10 18 atom / cm 3 , 1×10 18 atom / cm 3 , 1.5×10 18 atom / cm 3 or 2×10 18 atom / cm 3 wait.

[0026] Preferably, the doping concentration of N element in the N-type 4H-SiC epitaxial layer is 1×10 17 ~5×10 17 atom / cm 3 , for example, it can be 1×10 17 atom / cm 3 , 1.5×10 17 atom / cm 3 , 2×10 17 atom / cm 3 , 2.5×10 17 atom / cm 3 , 3×10 17 atom / cm 3 , 3.5×10 17 atom / cm 3 , 4×10 17 atom / cm 3 , 4.5×10 17 atom / cm 3 or 5×10 17 atom / cm 3 wait.

[0027] Preferably, the doping concentration of Mg in the P-type GaN epitaxial layer is 1×1016 ~1×10 19 atoms / cm 3 , for example, it can be 1×10 16 atoms / cm 3 、1×10 17 atoms / cm 3 、1×10 18 atoms / cm 3 or 1×10 19 atoms / cm 3 and so on.

[0028] In a second aspect, the present invention provides a method for preparing the SiC superjunction described in the first aspect, and the preparation method includes the following steps:

[0029] (1) Grow an N-type 4H-SiC buffer layer and an N-type 4H-SiC epitaxial layer on the SiC substrate in sequence, and then etch trenches downward on the surface of the N-type 4H-SiC epitaxial layer;

[0030] (2) Grow a P-type GaN epitaxial layer in the trenches in step (1) until the trenches are filled, and then etch with Cl2 until the thickness of the P-type GaN epitaxial layer is the same as the depth of the trenches, obtaining the SiC superjunction.

[0031] In the method for preparing the SiC superjunction of the present invention, growing a P-type GaN epitaxial layer in the trenches until the trenches are filled not only avoids the influence on the morphology of the trenches with high aspect ratio at high growth temperature, thereby avoiding the risk of generating voids in the trenches during the filling process at high growth temperature, but also enables filling under high growth pressure conditions, making the trench filling more firm; in addition, the post-treatment method of Cl2 etching is adopted, and the operation steps are simple, without the need to adopt chemical mechanical polishing for post-treatment. Using Cl2 etching not only avoids the voids generated due to the growth of the channel layer, thereby improving the surface quality of the SiC superjunction, but also reduces the post-treatment risk and cost.

[0032] Preferably, the SiC substrate in step (1) includes a (0001) SiC substrate biased 4° or 8° in the <11-20> direction.

[0033] Preferably, in step (1), the SiC substrate is etched first, and then an N-type 4H-SiC buffer layer and an N-type 4H-SiC epitaxial layer are grown on the etched SiC substrate in sequence.

[0034] Preferably, the temperature for etching the SiC substrate is 1400 - 1500 °C, for example, it can be 1400 °C, 1420 °C, 1450 °C, 1480 °C or 1500 °C, and so on.

[0035] Preferably, the pressure for etching the SiC substrate is 50 to 100 mbar, for example, it can be 50 mbar, 60 mbar, 70 mbar, 80 mbar, 90 mbar or 100 mbar, etc.

[0036] Preferably, the time for etching the SiC substrate is 5 to 30 min, for example, it can be 5 min, 10 min, 15 min, 20 min, 25 min or 30 min, etc.

[0037] Preferably, the etching gas used for etching the SiC substrate includes HCl and H2.

[0038] Preferably, the flow rate of the HCl is 5 to 10 slm, for example, it can be 5 slm, 6 slm, 7 slm, 8 slm, 9 slm or 10 slm, etc.

[0039] Preferably, the flow rate of the H2 is 10 to 100 slm, for example, it can be 10 slm, 20 slm, 30 slm, 40 slm, 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, etc.

[0040] Preferably, the growth temperature of the N-type 4H-SiC buffer layer in step (1) is 1600 to 1640 °C, for example, it can be 1600 °C, 1610 °C, 1620 °C, 1630 °C or 1640 °C, etc.

[0041] Preferably, the growth pressure of the N-type 4H-SiC buffer layer in step (1) is 50 to 100 mbar, for example, it can be 50 mbar, 60 mbar, 70 mbar, 80 mbar, 90 mbar or 100 mbar, etc.

[0042] Preferably, the growth thickness of the N-type 4H-SiC buffer layer in step (1) is 0.5 to 1 μm, for example, it can be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm or 1 μm, etc.

[0043] Preferably, the doping concentration of the N element in the N-type 4H-SiC buffer layer in step (1) is 0.5×10 18 ~2×10 18 atom / cm 3 ,for example, it can be 0.5×10 18 atom / cm 3 、1×10 18 atom / cm 3 、1.5×10 18 atom / cm 3 or 2×10 18atom / cm 3 etc.

[0044] Preferably, the growth temperature of the N-type 4H-SiC epitaxial layer in step (1) is 1600-1700 °C, for example, it can be 1600 °C, 1620 °C, 1650 °C, 1680 °C or 1700 °C, etc.

[0045] Preferably, the growth pressure of the N-type 4H-SiC epitaxial layer in step (1) is 50-100 mbar, for example, it can be 50 mbar, 60 mbar, 70 mbar, 80 mbar, 90 mbar or 100 mbar, etc.

[0046] Preferably, the growth thickness of the N-type 4H-SiC epitaxial layer in step (1) is 5-11 μm, for example, it can be 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or 11 μm, etc.

[0047] Preferably, the doping concentration of nitrogen element in the N-type 4H-SiC epitaxial layer in step (1) is 1-5×10 17 atom / cm -3 , for example, it can be 1×10 17 atom / cm -3 , 2×10 17 atom / cm -3 , 3×10 17 atom / cm -3 , 4×10 17 atom / cm -3 or 5×10 17 atom / cm -3 etc.

[0048] Preferably, the growth gases used for growing the N-type 4H-SiC buffer layer and the N-type 4H-SiC epitaxial layer in step (1) are all silicon source gas, carbon source gas, N-type dopant and first carrier gas.

[0049] It should be noted that the types of growth gases used for growing the N-type 4H-SiC buffer layer and the N-type 4H-SiC epitaxial layer in step (1) of the present invention can be the same or different.

[0050] Preferably, the silicon source gas includes any one or a combination of at least two of SiCl4, SiHCl3, SiH2C12 or SiH3Cl, and typical but non-limiting combinations include the combination of SiCl4 and SiHCl3, the combination of SiHCl3 and SiH2C12, or the combination of SiCl4, SiHCl3, SiH2C12 and SiH3Cl, etc.

[0051] Preferably, the flow rate of the silicon source gas used for growing the N-type 4H-SiC buffer layer in step (1) is 50 - 100 sccm, for example, it can be 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm or 100 sccm, etc.

[0052] Preferably, the flow rate of the silicon source gas used for growing the N-type 4H-SiC epitaxial layer in step (1) is 100 - 500 sccm, for example, it can be 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm, etc.

[0053] Preferably, the carbon source gas includes C2H4 and / or C3H8.

[0054] Preferably, the flow rate of the carbon source gas used for growing the N-type 4H-SiC buffer layer in step (1) is 50 - 100 sccm, for example, it can be 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm or 100 sccm, etc.

[0055] Preferably, the flow rate of the carbon source gas used for growing the N-type 4H-SiC epitaxial layer in step (1) is 100 - 500 sccm, for example, it can be 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm, etc.

[0056] Preferably, the N-type dopant includes N2 and / or NH3.

[0057] Preferably, the flow rate of the N-type dopant used for growing the N-type 4H-SiC buffer layer in step (1) is 10 - 20 sccm, for example, it can be 10 sccm, 12 sccm, 15 sccm, 18 sccm or 20 sccm, etc.

[0058] Preferably, the flow rate of the N-type dopant used for growing the N-type 4H-SiC epitaxial layer in step (1) is 80 - 150 sccm, for example, it can be 80 sccm, 90 sccm, 100 sccm, 110 sccm, 120 sccm, 130 sccm, 140 sccm or 150 sccm, etc.

[0059] Preferably, the first carrier gas includes H2.

[0060] Preferably, the flow rate of the first carrier gas used for growing the N-type 4H-SiC buffer layer in step (1) is 10 to 100 slm, for example, it can be 10 slm, 20 slm, 30 slm, 40 slm, 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, etc.

[0061] Preferably, the flow rate of the first carrier gas used for growing the N-type 4H-SiC epitaxial layer in step (1) is 10 to 50 slm, for example, it can be 10 slm, 20 slm, 30 slm, 40 slm or 50 slm, etc.

[0062] Preferably, the etching depth of the etched trench in step (1) is 2 to 11 μm, for example, it can be 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm or 11 μm, etc.

[0063] Preferably, the sidewall inclination angle of the trench obtained by etching the trench in step (2) is 85 to 90°, for example, it can be 85°, 86°, 87°, 88°, 89° or 90°, etc.

[0064] Preferably, the upper and lower etching widths of the etched trench in step (2) are each independently 0.6 to 1.1 μm, for example, it can be 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1 μm or 1.1 μm, etc.

[0065] Preferably, the growth gas used for growing the P-type GaN epitaxial layer in step (2) includes a nitrogen source gas, a gallium source gas and a P-type dopant.

[0066] Preferably, the nitrogen source gas includes N2 and / or NH3, preferably N2 and NH3.

[0067] Preferably, the flow rate of the N2 is 50 to 100 slm, for example, it can be 50 slm, 60 slm, 70 slm, 80 slm, 90 slm or 100 slm, etc.

[0068] Preferably, the flow rate of the NH3 is 10 to 50 slm, for example, it can be 10 slm, 20 slm, 30 slm, 40 slm or 50 slm, etc.

[0069] Preferably, the gallium source gas includes trimethylgallium.

[0070] Preferably, the flow rate of the gallium source gas is 100 to 500 sccm, for example, it can be 100 sccm, 150 sccm, 200 sccm, 250 sccm, 300 sccm, 350 sccm, 400 sccm, 450 sccm or 500 sccm, etc.

[0071] Preferably, the P-type dopant includes magnesium cyclopentadienyl.

[0072] Preferably, the flow rate of the P-type dopant is 50-200 sccm, and for example, it can be 50 sccm, 80 sccm, 100 sccm, 120 sccm, 150 sccm, 180 sccm, 200 sccm, etc.

[0073] Preferably, the growth gas for growing the P-type GaN epitaxial layer in step (2) further includes a second carrier gas.

[0074] Preferably, the second carrier gas includes N2.

[0075] Preferably, the flow rate of the second carrier gas is 50-100 slm, and for example, it can be 50 slm, 60 slm, 70 slm, 80 slm, 90 slm, 100 slm, etc.

[0076] Preferably, the growth temperature of the P-type GaN epitaxial layer in step (2) is 850-900 °C, and for example, it can be 850 °C, 860 °C, 870 °C, 880 °C, 890 °C, 900 °C, etc.

[0077] Preferably, the growth pressure of the P-type GaN epitaxial layer in step (2) is 500-800 mbar, and for example, it can be 500 mbar, 550 mbar, 600 mbar, 650 mbar, 700 mbar, 750 mbar, 800 mbar, etc.

[0078] Preferably, the doping concentration of magnesium element in the P-type GaN epitaxial layer in step (2) is 1×10 16 ~1×10 19 atom / cm -3 , and for example, it can be 1×10 16 atom / cm -3 , 1×10 17 atom / cm -3 , 1×10 18 atom / cm -3 or 1×10 19 atom / cm -3 etc.

[0079] The present invention further preferably has the doping concentration of magnesium element in the P-type GaN epitaxial layer in step (2) being 1×10 16 ~1×10 19 atom / cm -3, it is conducive to obtaining a relatively high hole concentration and ensuring good electrical performance of the device; if the doping concentration of magnesium element in the P-type GaN epitaxial layer is too low, the hole concentration of the P-type GaN will be too low, resulting in insufficient conductivity, uneven electric field distribution in the P-type region, and affecting the switching characteristics and conduction ability of the device; if the doping concentration of magnesium element in the P-type GaN epitaxial layer is too high, it will lead to uneven electric field distribution and weaken the conductivity of the P-type GaN.

[0080] Preferably, the flow rate of Cl2 during the Cl2 etching in step (2) is 25-50 slm, such as 25 slm, 30 slm, 35 slm, 40 slm, 45 slm or 50 slm, etc.

[0081] Preferably, the temperature of the Cl2 etching in step (2) is 850-900 °C, such as 850 °C, 860 °C, 870 °C, 880 °C, 890 °C or 900 °C, etc.

[0082] Preferably, the pressure of the Cl2 etching in step (2) is 50-100 mbar, such as 50 mbar, 60 mbar, 70 mbar, 80 mbar, 90 mbar or 100 mbar, etc.

[0083] The present invention further preferably uses the temperature of the Cl2 etching to be 850-900 °C, which is beneficial to ensuring sufficient etching while ensuring that the trench morphology does not change and ensuring excellent device performance: if the temperature of the Cl2 etching is too low, it will lead to insufficient etching, resulting in voids in the subsequent growth of the channel layer and reducing the device quality and performance; if the temperature of the Cl2 etching is too high, it will lead to excessive etching and affect the trench morphology, resulting in a decline in device performance.

[0084] Preferably, the time of the Cl2 etching in step (2) is 15-25 min, such as 15 min, 18 min, 20 min, 22 min or 25 min, etc.

[0085] Preferably, a third carrier gas is introduced during the Cl2 etching in step (2).

[0086] Preferably, the third carrier gas includes H2.

[0087] Preferably, the flow rate of the third carrier gas is 50-80 slm, such as 50 slm, 55 slm, 60 slm, 65 slm, 70 slm, 75 slm or 80 slm, etc.

[0088] As a further preferred technical solution of the present invention, the preparation method of the SiC superjunction includes the following steps:

[0089] (1) Select a (0001) SiC substrate with a selection bias of 4° or 8° in the <11-20> direction. First, etch the SiC substrate for 5-30 minutes at 1400-1500 °C and 50-100 mbar using HCl with a flow rate of 5-10 slm and H2 with a flow rate of 10-100 slm. Then, on the etched SiC substrate, first grow an N-type 4H-SiC buffer layer of 0.5-1 μm under the growth conditions of 1600-1640 °C and 50-100 mbar using a growth gas composed of a silicon source gas with a flow rate of 50-100 sccm, a carbon source gas with a flow rate of 50-100 sccm, an N-type dopant with a flow rate of 10-20 sccm, and a first carrier gas with a flow rate of 10-100 slm. Then, on the N-type 4H-SiC buffer layer, grow an N-type 4H-SiC epitaxial layer of 5-11 μm under the growth conditions of 1600-1700 °C and 50-100 mbar using a growth gas composed of a silicon source gas with a flow rate of 100-500 sccm, a carbon source gas with a flow rate of 100-500 sccm, an N-type dopant with a flow rate of 80-150 sccm, and a first carrier gas with a flow rate of 10-50 slm;

[0090] The silicon source gas includes any one or a combination of at least two of SiCl4, SiHCl3, SiH2C12, or SiH3Cl; the carbon source gas includes C2H4 and / or C3H8; the N-type dopant includes N2 and / or NH3; the first carrier gas includes H2; the doping concentration of N element in the N-type 4H-SiC buffer layer is 0.5×10 18 ~2×10 18 atom / cm 3 ; the doping concentration of nitrogen element in the N-type 4H-SiC epitaxial layer is 1×10 17 ~5×10 17 atom / cm -3 ;

[0091] Subsequently, etch a trench downward on the surface of the N-type 4H-SiC epitaxial layer; the etching depth is 2-11 μm; the upper and lower etching widths are each independently 0.6-1.1 μm; the sidewall inclination angle of the obtained trench is 85-90°;

[0092] (2) Under the growth conditions of 850 - 900 °C and 500 - 800 mbar, a growth gas composed of N₂ with a flow rate of 50 - 100 slm, NH₃ with a flow rate of 10 - 50 slm, a gallium source gas with a flow rate of 100 - 500 sccm, a P-type dopant with a flow rate of 50 - 200 sccm, and a second carrier gas with a flow rate of 50 - 100 slm is used to grow a P-type GaN epitaxial layer in the trench described in step (1) until the trench is filled. Then, under the etching conditions of 850 - 900 °C and 50 - 100 mbar, Cl₂ with a flow rate of 25 - 50 slm and a third carrier gas with a flow rate of 50 - 80 slm are used for Cl₂ etching for 15 - 25 min until the thickness of the P-type GaN epitaxial layer is the same as the depth of the trench, obtaining the SiC superjunction;

[0093] The gallium source gas includes trimethylgallium; the P-type dopant includes magnesium cyclopentadienyl; the second carrier gas includes N₂; the doping concentration of magnesium element in the P-type GaN epitaxial layer is 1×10 16 ~1×10 19 atom / cm -3 ; the third carrier gas includes H₂.

[0094] In a third aspect, the present invention provides an application of the SiC superjunction described in the first aspect, and the SiC superjunction is used in the fields of smart grid, new energy vehicles, industrial motor drives, high-frequency switches, or power devices.

[0095] The SiC superjunction of the present invention optimizes the electric field distribution of the device, improves the breakdown voltage and reduces the on-resistance, enabling it to have broad application prospects in the fields of smart grid, new energy vehicles, industrial motor drives, high-frequency switches, or power devices, and can significantly improve the efficiency and power density of the system, meeting the application requirements in extreme environments.

[0096] Compared with the prior art, the present invention has at least the following beneficial effects:

[0097] (1) For the SiC superjunction provided by the present invention, through the optimized structure and the filling material of its trench, the filling is achieved at a lower growth temperature and a higher growth pressure, ensuring that the trench morphology remains unchanged and no voids are generated, reducing the specific on-resistance of the MOSFET device prepared with the SiC superjunction, preferably as low as 0.94 mΩ·mm 2 hereinafter, improving its breakdown voltage, preferably up to more than 1745 V, and significantly enhancing the consistency and reliability of the device.

[0098] (2) The preparation method of the SiC superjunction provided by the present invention makes the trench morphology of the SiC superjunction unchanged during or after filling without voids by selecting the filling material of the trenches in the SiC superjunction, its growth temperature and growth pressure, and combining with the post-treatment step of Cl2 etching, thereby improving the performance of the device; and the preparation process is simple and the cost is low.

[0099] (3) The application of the SiC superjunction provided by the present invention can meet the application requirements in extreme environments with a lower specific on-resistance and a higher breakdown voltage, and is widely used in fields such as smart grids, new energy vehicles, industrial motor drives, high-frequency switches or power devices. Description of the Drawings

[0100] Figure 1 is a schematic structural diagram of the SiC superjunction provided in Embodiment 1 of the present invention;

[0101] Figure 2 is an atomic force microscope image of the SiC superjunction provided in Embodiment 1 of the present invention;

[0102] In the figure: 1, SiC substrate; 2, N-type 4H-SiC buffer layer; 3, N-type 4H-SiC epitaxial layer; 4, trench; 5, P-type GaN epitaxial layer. Detailed Embodiments

[0103] The technical solutions of the present invention will be further described below with reference to the drawings and through specific embodiments. However, the following examples are only simple examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention is subject to the claims.

[0104] The preparation methods of the SiC superjunctions in the following examples and comparative examples are carried out using a chemical vapor deposition device. Before etching the SiC substrate, the SiC substrate is first cleaned and placed in the reaction chamber of the chemical vapor deposition device that has been evacuated and filled, and the reaction chamber is evacuated to a vacuum (the vacuum degree is 3-10 mbar).

[0105] I. Example

[0106] Example 1

[0107] This example provides a SiC superjunction, as Figure 1 shown, the SiC superjunction includes a SiC substrate 1, an N-type 4H-SiC buffer layer 2, and an N-type 4H-SiC epitaxial layer 3 provided with trenches 4 arranged in sequence; the trenches 4 are filled with a P-type GaN epitaxial layer 5, and the thickness of the P-type GaN epitaxial layer 5 is the same as the depth of the trenches 4;

[0108] The thickness of the SiC substrate 1 is 350 μm; the thickness of the N-type 4H-SiC buffer layer 2 is 0.8 μm; the doping concentration of the N element in the N-type 4H-SiC buffer layer 2 is 1×10 18 atom / cm -3 ; The thickness of the N-type 4H-SiC epitaxial layer 3 provided with the groove 4 is 10 μm; the aspect ratio of the groove 4 is 8:1, the depth is 8 μm, and the upper and lower widths are both 1 μm; the sidewall inclination angle of the groove 4 is 90°; the doping concentration of the N element in the N-type 4H-SiC epitaxial layer 3 provided with the groove 4 is 3×10 17 atom / cm -3 The doping concentration of Mg in the P-type GaN epitaxial layer 5 is 1×10 18 atom / cm -3 .

[0109] like Figure 2 As shown, it can be seen that no voids are generated in the morphology of the trench 4 of the SiC super junction described in this embodiment.

[0110] This embodiment also provides a method for preparing the above-mentioned SiC super junction, the preparation method comprising the following steps:

[0111] (1) A (0001) SiC substrate 1 with a 4° orientation in the <11-20> direction was selected, and the SiC substrate 1 was first etched at 1450°C and 80 mbar using HCl with a flow rate of 8 slm and H2 with a flow rate of 80 slm for 15 min. Then, on the etched SiC substrate 1, a growth condition was firstly set at 1620°C and 80 mbar using SiCl4 with a flow rate of 75 sccm, C2H4 with a flow rate of 85 sccm, N2 with a flow rate of 15 sccm, and H2 with a flow rate of 65 slm. A growth gas composed of H2 is used to grow an N-type 4H-SiC buffer layer 20.8 μm; then, on the N-type 4H-SiC buffer layer 2, a growth gas composed of SiCl4 with a flow rate of 300 sccm, C2H4 with a flow rate of 350 sccm, N2 with a flow rate of 120 sccm, and H2 with a flow rate of 25 slm is used to grow an N-type 4H-SiC epitaxial layer 310 μm; the doping concentration of the N element in the N-type 4H-SiC buffer layer 2 is 1×10 18 atom / cm -3 The doping concentration of nitrogen in the N-type 4H-SiC epitaxial layer 3 is 3×10 17 atom / cm -3 ;

[0112] Subsequently, a groove 4 is etched downward on the surface of the N-type 4H-SiC epitaxial layer 3; the etching depth is 8 μm; the upper and lower etching widths are both 1 μm; the sidewall inclination angle of the obtained groove 4 is 90°;

[0113] (2) Under the growth conditions of 880 °C and 700 mbar, using a growth gas composed of N2 with a flow rate of 80 slm, NH3 with a flow rate of 30 slm, trimethylgallium with a flow rate of 300 sccm, magnesium cyclopentadienyl with a flow rate of 150 sccm, and N2 with a flow rate of 90 slm, a P-type GaN epitaxial layer 5 is grown in the groove 4 described in step (1) until the groove 4 is filled, and then under the etching conditions of 880 °C and 80 mbar, using Cl2 with a flow rate of 45 slm and H2 with a flow rate of 70 slm, Cl2 etching is carried out for 20 min until the thickness of the P-type GaN epitaxial layer is the same as the depth of the groove, obtaining the SiC superjunction; the doping concentration of magnesium element in the P-type GaN epitaxial layer 5 is 1×10 18 atom / cm -3 。

[0114] Example 2

[0115] This example provides a SiC superjunction, which includes a SiC substrate, an N-type 4H-SiC buffer layer, and an N-type 4H-SiC epitaxial layer with grooves arranged in sequence; the groove is filled with a P-type GaN epitaxial layer, and the thickness of the P-type GaN epitaxial layer is the same as the depth of the groove;

[0116] The thickness of the SiC substrate is 400 μm; the thickness of the N-type 4H-SiC buffer layer is 0.5 μm; the doping concentration of N element in the N-type 4H-SiC buffer layer is 0.5×10 18 atom / cm -3 ; the thickness of the N-type 4H-SiC epitaxial layer with grooves is 8 μm; the depth-to-width ratio of the groove is 6:1, the depth is 4.8 μm, and the upper and lower widths are both 0.8 μm; the sidewall inclination angle of the groove is 85°; the doping concentration of N element in the N-type 4H-SiC epitaxial layer with grooves is 1×10 17 cm -3 ; the doping concentration of Mg element in the P-type GaN epitaxial layer is 1×10 17 cm -3 。

[0117] After the groove of the SiC superjunction in this example is filled, no voids are generated.

[0118] This example also provides a preparation method for the above SiC superjunction, and the preparation method includes the following steps:

[0119] (1) Select a (0001) SiC substrate with a <11-20> direction bias of 8°. First, etch the SiC substrate for 10 minutes at 1400 °C and 50 mbar using HCl with a flow rate of 5 slm and H2 with a flow rate of 50 slm. Then, on the etched SiC substrate, first grow an N-type 4H-SiC buffer layer of 0.5 μm at a growth condition of 1600 °C and 60 mbar using a growth gas composed of SiHCl3 with a flow rate of 50 sccm, C3H8 with a flow rate of 50 sccm, NH3 with a flow rate of 10 sccm, and H2 with a flow rate of 50 slm. Then, on the N-type 4H-SiC buffer layer, grow an N-type 4H-SiC epitaxial layer of 8 μm at a growth condition of 1600 °C and 50 mbar using a growth gas composed of SiHCl3 with a flow rate of 100 sccm, C3H8 with a flow rate of 100 sccm, N2 with a flow rate of 80 sccm, and H2 with a flow rate of 10 slm. The doping concentration of N element in the N-type 4H-SiC buffer layer is 0.5×10 18 atom / cm -3 ; The doping concentration of nitrogen element in the N-type 4H-SiC epitaxial layer is 1×10 17 atom / cm -3 ;

[0120] Subsequently, etch a trench downward on the surface of the N-type 4H-SiC epitaxial layer; the etching depth is 4.8 μm; the upper and lower etching widths are both 0.8 μm; the sidewall inclination angle of the obtained trench is 85°;

[0121] (2) Under the growth condition of 850 °C and 500 mbar, use a growth gas composed of N2 with a flow rate of 50 slm, NH3 with a flow rate of 10 slm, trimethylgallium with a flow rate of 100 sccm, bis(cyclopentadienyl)magnesium with a flow rate of 100 sccm, and N2 with a flow rate of 50 slm to grow a P-type GaN epitaxial layer in the trench described in step (1) until the trench is filled, and then under the etching condition of 850 °C and 50 mbar, use Cl2 with a flow rate of 25 slm and H2 with a flow rate of 50 slm to etch with Cl2 for 15 minutes until the thickness of the P-type GaN epitaxial layer is the same as the depth of the trench, obtaining the SiC superjunction; the doping concentration of magnesium element in the P-type GaN epitaxial layer is 1×10 17 atom / cm -3 .

[0122] Example 3

[0123] This embodiment provides a SiC superjunction, which includes an SiC substrate, an N-type 4H-SiC buffer layer arranged in sequence, and an N-type 4H-SiC epitaxial layer with grooves; the grooves are filled with a P-type GaN epitaxial layer, and the thickness of the P-type GaN epitaxial layer is the same as the depth of the grooves;

[0124] The thickness of the SiC substrate is 450 μm; the thickness of the N-type 4H-SiC buffer layer is 1 μm; the doping concentration of N element in the N-type 4H-SiC buffer layer is 2×10 18 atom / cm -3 ; the thickness of the N-type 4H-SiC epitaxial layer with grooves is 5 μm; the depth-to-width ratio of the grooves is 4:1, the depth is 2.4 μm, and the upper and lower widths are both 0.6 μm; the sidewall inclination angle of the grooves is 88°; the doping concentration of N element in the N-type 4H-SiC epitaxial layer with grooves is 5×10 17 atom / cm -3 ; the doping concentration of Mg element in the P-type GaN epitaxial layer is 1×10 16 atom / cm -3 .

[0125] After the grooves of the SiC superjunction in this embodiment are filled, no voids are generated.

[0126] This embodiment also provides a preparation method of the above SiC superjunction, and the preparation method includes the following steps:

[0127] (1) Select a (0001) SiC substrate biased 4° in the <11-20> direction. First, etch the SiC substrate for 30 min at 1500 °C and 100 mbar with HCl at a flow rate of 10 slm and H2 at a flow rate of 100 slm; then, on the etched SiC substrate, first grow an N-type 4H-SiC buffer layer of 1 μm under the growth conditions of 1640 °C and 100 mbar with a growth gas composed of SiCl4 at a flow rate of 100 sccm, C2H4 at a flow rate of 100 sccm, N2 at a flow rate of 20 sccm, and H2 at a flow rate of 100 slm; then, on the N-type 4H-SiC buffer layer, grow an N-type 4H-SiC epitaxial layer of 5 μm under the growth conditions of 1700 °C and 100 mbar with a growth gas composed of SiCl4 at a flow rate of 500 sccm, C2H4 at a flow rate of 500 sccm, N2 at a flow rate of 150 sccm, and H2 at a flow rate of 50 slm; the doping concentration of N element in the N-type 4H-SiC buffer layer is 2×10 18 atom / cm -3 ; the doping concentration of nitrogen element in the N-type 4H-SiC epitaxial layer is 5×1017 atoms / cm -3 ;

[0128] Subsequently, grooves are etched downward on the surface of the N-type 4H-SiC epitaxial layer; the etching depth is 2.4 μm; the upper and lower etching widths are both 0.6 μm; the sidewall inclination angle of the obtained grooves is 88°;

[0129] (2) Under the growth conditions of 900 °C and 800 mbar, a growth gas composed of N2 with a flow rate of 100 slm, NH3 with a flow rate of 50 slm, trimethylgallium with a flow rate of 500 sccm, magnesium bis(cyclopentadienyl) with a flow rate of 200 sccm, and N2 with a flow rate of 100 slm is used to grow a P-type GaN epitaxial layer in the grooves described in step (1) until the grooves are filled, and then under the etching conditions of 900 °C and 100 mbar, Cl2 with a flow rate of 50 slm and H2 with a flow rate of 80 slm are used for Cl2 etching for 25 min until the thickness of the P-type GaN epitaxial layer is the same as the depth of the grooves, obtaining the SiC superjunction; the doping concentration of magnesium element in the P-type GaN epitaxial layer is 1×10 16 atoms / cm -3 。

[0130] Example 4

[0131] This example provides a SiC superjunction. Except that the aspect ratio of the depth to width of the grooves is 2:1, the depth of the grooves is 2 μm, and the preparation parameters are correspondingly changed in the preparation method, the rest are the same as those in Example 1.

[0132] Example 5

[0133] This example provides a SiC superjunction. Except that the thickness of the N-type 4H-SiC buffer layer is 0.3 μm and the preparation parameters are correspondingly changed in the preparation method, the rest are the same as those in Example 1.

[0134] Example 6

[0135] This example provides a SiC superjunction. Except that the thickness of the N-type 4H-SiC buffer layer is 1.2 μm and the preparation parameters are correspondingly changed in the preparation method, the rest are the same as those in Example 1.

[0136] Example 7

[0137] This example provides a SiC superjunction. Except that the doping concentration of Mg element in the P-type GaN epitaxial layer is 1×10 15 atoms / cm -3 , and the preparation parameters are correspondingly changed in the preparation method, the rest are the same as those in Example 1.

[0138] Example 8

[0139] This example provides a SiC superjunction. Except that the doping concentration of Mg element in the P-type GaN epitaxial layer is 1.5×10 19 atom / cm -3 , and the preparation parameters are correspondingly changed in the preparation method, the rest are the same as those in Example 1.

[0140] Example 9

[0141] This example provides a SiC superjunction. Except that the growth temperature of the P-type GaN epitaxial layer in step (2) of its preparation method is 800 °C, the rest are the same as those in Example 1.

[0142] Example 10

[0143] This example provides a SiC superjunction. Except that the growth temperature of the P-type GaN epitaxial layer in step (2) of its preparation method is 950 °C, the rest are the same as those in Example 1.

[0144] Example 11

[0145] This example provides a SiC superjunction. Except that the pressure of Cl2 etching in step (2) of its preparation method is 40 mbar, the rest are the same as those in Example 1.

[0146] Example 12

[0147] This example provides a SiC superjunction. Except that the pressure of Cl2 etching in step (2) of its preparation method is 120 mbar, the rest are the same as those in Example 1.

[0148] II. Comparative Examples

[0149] Comparative Example 1

[0150] This comparative example provides a SiC superjunction. Except that the trench is filled with a P-type 4H-SiC epitaxial layer and the preparation method is correspondingly changed, the rest are the same as those in Example 1.

[0151] Comparative Example 2

[0152] This comparative example provides a SiC superjunction. Except that the thickness of the P-type GaN epitaxial layer is greater than the depth of the trench, that is, no post-treatment is carried out by Cl2 etching during its preparation process, the rest are the same as those in Example 1.

[0153] Comparative Example 3

[0154] This comparative example provides a SiC superjunction. Except that chemical mechanical polishing is used instead of Cl2 etching for post-treatment during its preparation process, the rest is the same as in Example 1.

[0155] III. Tests and Their Results

[0156] Test method: Fabricate a MOSFET device structure from the superjunctions obtained in the above-mentioned examples and comparative examples, and characterize the breakdown voltage according to GB / T29332 - 2012 to evaluate the voltage withstand performance, and test the on-resistance according to GB / T 14028—2018. The test results are shown in Table 1;

[0157] Table 1

[0158]

[0159]

[0160] It can be seen from the data in Table 1 that:

[0161] (1) Considering Examples 1 to 3 comprehensively, it can be seen that for the SiC superjunction and its preparation method provided by the present invention, by optimizing the structure and preparation parameters of the SiC superjunction, the MOSFET device prepared therefrom has a lower specific on-resistance and a higher breakdown voltage. Among them, the specific on-resistance is as low as 0.94 mΩ·mm 2 Hereinafter, the breakdown voltage is as high as more than 1745 V, and there are no voids generated in the trenches of the SiC superjunction, significantly improving the performance and reliability of the device.

[0162] (2) Considering Example 1 and Example 4 comprehensively, it can be seen that in Example 4, the aspect ratio of the trench in the SiC superjunction is relatively low, resulting in an increase in the specific on-resistance of the MOSFET device prepared therefrom to 1.91 mΩ·mm 2 , and the breakdown voltage is reduced to 1569 V, thereby weakening the performance of the device; this indicates that the present invention further preferably sets the aspect ratio of the trench to (3 - 10):1, further reducing the specific on-resistance of the device and further increasing the breakdown voltage of the device, thereby improving the performance of the device.

[0163] (3) Considering Example 1 and Example 5 and Example 6 comprehensively, it can be seen that when the thickness of the N-type 4H-SiC buffer layer in Example 5 is too thin or the thickness of the N-type 4H-SiC buffer layer in Example 6 is too thick, both result in an increase in its specific on-resistance and a decrease in the breakdown voltage; this indicates that the present invention further preferably sets the thickness of the N-type 4H-SiC buffer layer to 0.5 - 1 μm, further reducing the specific on-resistance of the device and increasing the breakdown voltage of the device, obtaining a high-performance device.

[0164] (4) From the comprehensive implementation of Example 1, Example 7, and Example 8, it can be seen that the doping concentration of Mg elements in the P-type GaN epitaxial layer in the SiC superjunction described in Example 7 is relatively low, resulting in an increase in the specific on-resistance of the MOSFET device prepared therefrom to 1.49 mΩ·mm 2 and a decrease in the breakdown voltage to 1543 V; in the SiC superjunction described in Example 8, the doping concentration of Mg elements in the P-type GaN epitaxial layer is relatively high, which does not significantly reduce the specific on-resistance or increase the breakdown voltage. Instead, it increases the specific on-resistance and decreases the breakdown voltage, while causing waste of resources. Thus, it is shown that the present invention further preferably selects the doping concentration of Mg elements in the P-type GaN epitaxial layer to be 1×10 16 ~1×10 19 atom / cm -3 . While further improving the device performance, the manufacturing cost is reduced.

[0165] (5) From the comprehensive implementation of Example 1, Example 9 to Example 12, it can be seen that the present invention further preferably selects the growth temperature of the P-type GaN epitaxial layer in step (2) of the preparation process to be 850 - 900 °C; the pressure of the Cl2 etching is 50 - 100 mbar, further reducing the specific on-resistance of the device, increasing the breakdown voltage of the device, and ensuring that there are no voids in the trench, significantly improving the performance of the device.

[0166] (6) From the comprehensive implementation of Example 1, Comparative Example 1 to Comparative Example 3, it can be seen that since the trench in the SiC superjunction in Comparative Example 1 is filled with a P-type 4H-SiC epitaxial layer, and its growth temperature is relatively high, reaching above 1600 °C, the morphology of the trench is etched, affecting the performance of the device; since the SiC superjunction in Comparative Example 2 is not post-treated by Cl2 etching, voids are generated during the subsequent growth of the channel layer, reducing the device quality and performance; since chemical mechanical polishing is used instead of Cl2 etching for post-treatment in the preparation process of the SiC superjunction in Comparative Example 3, its surface quality is reduced and the process flow is relatively complex.

[0167] In summary, for the SiC superjunction and its preparation method of the present invention, by optimizing the structure, the filling material and growth conditions of the channel in the preparation process, and combining the post-treatment method of Cl2 etching and specific etching parameters, the specific on-resistance of the device is successfully reduced, the breakdown voltage is increased, while ensuring that there are no voids in the channel and the channel morphology does not change, significantly improving the performance of the device, which is widely used in the fields of smart grid, new energy vehicles, industrial motor drives, high-frequency switches or power devices; moreover, the preparation method has a simple process flow and low cost.

[0168] The applicant declares that the above description is only a specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily conceived by any person skilled in the art within the technical scope disclosed by the present invention fall within the protection scope and the disclosure scope of the present invention.

Claims

1. A SiC superjunction, characterized in that, The SiC superjunction includes an SiC substrate, an N-type 4H-SiC buffer layer arranged in sequence, and an N-type 4H-SiC epitaxial layer provided with grooves; the grooves are filled with a P-type GaN epitaxial layer, and the thickness of the P-type GaN epitaxial layer is the same as the depth of the grooves.

2. The SiC superjunction according to claim 1, wherein The thickness of the SiC substrate is 300 - 500 μm; Preferably, the thickness of the N-type 4H-SiC buffer layer is 0.5 - 1 μm; Preferably, the thickness of the N-type 4H-SiC epitaxial layer is 5 - 11 μm.

3. The SiC superjunction according to claim 1 or 2, characterized in that, The depth-to-width ratio of the grooves is (3 - 10):1; Preferably, the depth of the grooves is 2 - 11 μm; Preferably, the upper and lower widths of the grooves are each independently 0.6 - 1.1 μm; Preferably, the sidewall inclination angle of the grooves is 85 - 90°; 4. The SiC super junction according to any one of claims 1 to 3, characterized in that, The doping concentration of N element in the N-type 4H-SiC buffer layer is 0.5×10 18 ~2×10 18 atom / cm 3 ; Preferably, the doping concentration of N element in the N-type 4H-SiC epitaxial layer is 1×10 17 ~5×10 17 atom / cm 3 ; Preferably, the doping concentration of Mg element in the P-type GaN epitaxial layer is 1×10 16 ~1×10 19 atom / cm 3 .

5. A method for preparing a SiC superjunction according to any one of claims 1 to 4, characterized in that, The preparation method includes the following steps: (1) Growing an N-type 4H-SiC buffer layer and an N-type 4H-SiC epitaxial layer on the SiC substrate in sequence, and etching grooves downward on the surface of the N-type 4H-SiC epitaxial layer; (2) Growing a P-type GaN epitaxial layer in the grooves in step (1) until the grooves are filled, and then etching with Cl2 until the thickness of the P-type GaN epitaxial layer is the same as the depth of the grooves, obtaining the SiC superjunction.

6. The preparation method according to claim 5, characterized in that, The growth temperature of the N-type 4H-SiC buffer layer in step (1) is 1600 - 1640 °C; Preferably, the growth pressure of the N-type 4H-SiC buffer layer in step (1) is 50 - 100 mbar; Preferably, the growth thickness of the N-type 4H-SiC buffer layer in step (1) is 0.5 - 1 μm; Preferably, the doping concentration of N element in the N-type 4H-SiC buffer layer in step (1) is 0.5×10 18 ~2×10 18 atom / cm; Preferably, the growth temperature of the N-type 4H-SiC epitaxial layer in step (1) is 1600 - 1700 °C; Preferably, the growth pressure of the N-type 4H-SiC epitaxial layer in step (1) is 50 - 100 mbar; Preferably, the growth thickness of the N-type 4H-SiC epitaxial layer in step (1) is 5 - 11 μm; Preferably, the doping concentration of nitrogen element in the N-type 4H-SiC epitaxial layer in step (1) is 1 to 5×10 17 atom / cm 3 .

7. The preparation method according to claim 5 or 6, characterized in that The etching depth of the grooves in step (1) is 2 - 11 μm; Preferably, the sidewall inclination angle of the grooves obtained by etching the grooves in step (2) is 85 - 90°; Preferably, the upper and lower etching widths of the grooves in step (2) are each independently 0.6 - 1.1 μm.

8. The preparation method according to any one of claims 5 to 7, characterized in that, The growth gas used for growing the P-type GaN epitaxial layer in step (2) includes a nitrogen source gas, a gallium source gas, and a P-type dopant; Preferably, the nitrogen source gas includes N2 and / or NH3, preferably N2 and NH3; Preferably, the flow rate of the introduced N2 is 50 - 100 slm; Preferably, the flow rate of the introduced NH3 is 10 - 50 slm; Preferably, the gallium source gas includes trimethylgallium; Preferably, the flow rate of the introduced gallium source gas is 100 - 500 sccm; Preferably, the P-type dopant includes bis(cyclopentadienyl)magnesium; Preferably, the flow rate of the introduced P-type dopant is 50 - 200 sccm; Preferably, the growth temperature of the P-type GaN epitaxial layer in step (2) is 850 - 900 °C; Preferably, the growth pressure of the P-type GaN epitaxial layer in step (2) is 500 - 800 mbar; Preferably, the doping concentration of magnesium element in the P-type GaN epitaxial layer in step (2) is 1×10 16 ~1×10 19 atom / cm 3 .

9. The preparation method according to any one of claims 5 to 8, characterized in that, During the Cl2 etching in step (2), the flow rate of Cl2 is 25 - 50 slm; Preferably, the temperature of the Cl2 etching in step (2) is 850 - 900 °C; Preferably, the pressure of the Cl2 etching in step (2) is 50 - 100 mbar; Preferably, the time of the Cl2 etching in step (2) is 15 - 25 min.

10. An application of the SiC superjunction according to any one of claims 1 to 4, characterized in that, The SiC superjunction is used in the fields of smart grid, new energy vehicles, industrial motor drives, high-frequency switches, or power devices.

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