Thick gate oxidation process method for improving threshold voltage stability of MOS (Metal Oxide Semiconductor) device

Abstract

The invention relates to the field of integrated circuit manufacturing, and discloses a thick gate oxidation process method for improving the threshold voltage stability of an MOS (Metal Oxide Semiconductor) device, which comprises the following steps: arranging silicon wafers on a boat of a vertical furnace tube in a full-load manner, and placing CV test wafers in the vertical furnace tube for representing the dielectric charge characteristics of oxide layers at different positions in the vertical furnace; air enters the vertical furnace tube through an air inlet and is exhausted through an air outlet, airflow in the vertical furnace tube flows from top to bottom, the exhaust air rate of the gate oxidation process and the distance between two adjacent products are subjected to a pulling deviation experiment to obtain an experiment result, and the influence of the process exhaust air rate and the distance between adjacent silicon wafers on the charge uniformity of the oxidation layer in the furnace is determined according to the experiment result. The stability of the threshold voltage of the thick-gate MOS device is improved. According to the invention, based on in-depth analysis of the test results fed back by the test pieces at different positions, the uniformity of charges in and among the silicon wafers can be comprehensively evaluated, so that the stability and consistency of the whole technological process are ensured.

Description

Technical Field

[0001] The invention relates to the field of integrated circuit manufacturing, and in particular to a thick gate oxidation process method for improving the threshold voltage stability of MOS devices. Background Art

[0002] MOS (metal oxide semiconductor) devices have been widely and deeply used in the field of integrated circuits due to their significant advantages such as low power consumption, high integration and excellent temperature stability. However, the threshold voltage stability of MOS devices has always been a key challenge and difficulty in the integrated circuit manufacturing process. As an important parameter of MOS devices, the stability of threshold voltage directly determines the performance and reliability of the circuit.

[0003] The threshold voltage is affected by many factors, among which the change of gate dielectric charge has a particularly significant impact on the threshold voltage, especially when the gate dielectric capacitance is relatively small. The change of gate dielectric charge will directly lead to the shift of threshold voltage, thus affecting the normal operation of the circuit. This challenge is particularly prominent for high-reliability military integrated circuits. Since the gate dielectric thickness of such products is relatively thick and the gate capacitance is small, the same change of gate dielectric charge will cause a greater change of threshold voltage, which puts higher requirements on the stability and reliability of the circuit.

[0004] Although the industry has conducted extensive and in-depth research on the formation mechanism of gate dielectric charge, there are few systematic studies and reports on how to optimize the uniformity of gate dielectric charge within and between wafers. In the conventional integrated circuit production process, the control of the charge consistency between wafers in the same furnace and between furnaces in the gate dielectric during the gate oxidation process is a crucial link. However, since the fluctuation of gate dielectric charge is difficult to detect directly during the process, it usually needs to be discovered in the subsequent WAT (wafer acceptance test). This not only increases the complexity and cost of the production line, but also poses a severe challenge to the stability of the production line.

[0005] In integrated circuit manufacturing, the thermal oxidation process usually produces 100 pieces per furnace, and the gap between product pieces is small, 4.76mm. Because the equipment does not have a subnormal pressure control system, there is a mismatch between the intake and exhaust, and turbulence occurs in the furnace, causing large fluctuations in the charge of the film growing within and between pieces. The process indicators of concern in the oxidation process are film thickness, particles, and dielectric charge. Usually, film thickness and particles are less affected, and the uniformity within the piece can basically reach less than 1%, but the charge within the dielectric has obvious deviations, and in severe cases, the charge uniformity can reach more than 80%.

[0006] Therefore, how to effectively control and optimize the uniformity of gate dielectric charge and improve the threshold voltage stability of MOS devices has become an important issue that needs to be urgently addressed in the current integrated circuit manufacturing field. Summary of the invention

[0007] In order to overcome the defects existing in the above-mentioned prior art, the object of the present invention is to provide a thick gate oxidation process method for improving the threshold voltage stability of MOS devices, so as to solve the technical problem of how to effectively control and optimize the uniformity of gate dielectric charge.

[0008] The present invention is realized through the following technical solutions: In the first aspect, the present invention provides a thick gate oxidation process method for improving the threshold voltage stability of MOS devices, including the following processes: Load silicon wafers on the boat of a vertical furnace tube, and place CV test wafers inside the vertical furnace tube to characterize the oxide layer dielectric charge characteristics at different positions inside the vertical furnace. The vertical furnace tube intakes air through the air inlet and exhausts air through the exhaust port. The airflow inside the vertical furnace tube flows from top to bottom. Conduct a bias experiment on the exhaust air volume of the gate oxidation process and the spacing between adjacent two products to obtain experimental results. According to the experimental results, determine the influence of the process exhaust air volume and the spacing between adjacent silicon wafers on the uniformity of the oxide layer charge inside the furnace, thereby improving the stability of the threshold voltage of the thick gate MOS device.

[0009] Specifically, the model of the vertical furnace tube is KE-DD802V.

[0010] Specifically, the groove spacing of the boat is 4.75 mm.

[0011] Specifically, the gate dielectric thickness on the surface of the silicon wafer is more than 800 angstroms.

[0012] Specifically, the CV test wafers are respectively located at the inlet end, the middle section, and the tail end of the vertical furnace tube to detect the charge quantity in the silicon wafers at the inlet end, the middle section, and the tail end of the vertical furnace tube.

[0013] Specifically, the CV test wafer includes several test points.

[0014] Specifically, the CV test wafer measures its capacitance-voltage characteristic curve, and then calculates the flat-band voltage value representing the dielectric charge information in the oxide layer. When the flat-band voltage values corresponding to different positions of the CV test wafer and different test points in the CV test wafer are more uniform, the oxide layer charge distribution is uniform; otherwise, the oxide layer charge distribution is non-uniform.

[0015] Specifically, the pressure range of the optimal exhaust air volume of the gate oxidation process is 175 - 195 pa.

[0016] Specifically, in the step of determining the influence of the process exhaust air volume and the spacing between adjacent silicon wafers on the uniformity of the oxide layer charge inside the furnace, the experimental results of the number of spacer grooves between adjacent silicon wafers on the CV test wafers at different positions show that the optimal spacing between adjacent silicon wafers is 2 to 3 spacer grooves, that is, 9 mm to 15 mm.

[0017] In a second aspect, the present invention provides a MOS device with optimized threshold voltage consistency obtained by the thick gate oxidation process method for improving the threshold voltage stability of the MOS device described above.

[0018] Compared with the prior art, the present invention has the following beneficial technical effects: The present invention provides a thick gate oxidation process method for improving the threshold voltage stability of a MOS device. By changing the equipment exhaust parameters and wafer loading method, the uniformity of the gas flow in the furnace is effectively optimized, and the influence of turbulence or circulation on the charges in the film quality is weakened. By offsetting different exhaust pressures to confirm the relationship with the charge uniformity of the oxide layer grown in the furnace, it helps to reveal the potential connection between the exhaust pressure and the gate dielectric charge uniformity. At the same time, by offsetting the product spacing, the gas flow condition on the product surface is optimized, and the influence on the charge uniformity of the growth medium is verified. By optimizing the exhaust pressure and product placement spacing, the charge uniformity in the gate dielectric can be improved, thereby improving the threshold voltage stability of the MOS device. Based on the in-depth analysis of the test results feedback from test wafers at different positions, the charge uniformity within and between wafers can be comprehensively evaluated, thus ensuring the stability and consistency of the entire process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flowchart of the gate oxidation process method for improving the threshold voltage stability of the MOS device in the embodiment of the present invention; Figure 2 It is a schematic diagram of the test point positions in the CV test wafer in the embodiment of the present invention; Figure 3 It is a block diagram of the Vfb distribution of the in-furnace monitoring CV test wafer under different exhaust settings in the embodiment of the present invention; Figure 4 It is a block diagram of the Vfb distribution of the in-furnace mouth-end monitoring CV test wafer under different exhaust settings in the embodiment of the present invention; Figure 5 It is a block diagram of the Vfb distribution of the in-furnace middle-end monitoring CV test wafer under different exhaust settings in the embodiment of the present invention; Figure 6 It is a block diagram of the Vfb distribution of the in-furnace tail-end monitoring CV test wafer under different exhaust settings in the embodiment of the present invention; Figure 7 It is a schematic diagram of the experimental wafer interval slot positions in the embodiment of the present invention; Figure 8 It is the influence of different interval slot placements on the monitored Vfb in the embodiment of the present invention; Figure 9 It is a schematic diagram of the gas flow performance when the wafer spacing on the boat of the vertical furnace tube in the embodiment of the present invention is increased and decreased; Figure 10 Schematic diagram of the unchanged gas flow performance between the wafers on the boat of the vertical furnace tube in the embodiment of the present invention; In the figure, 1 is a vertical furnace tube; 2 is an air inlet; 3 is a boat; 4 is a CV test chip; 5 is a silicon wafer; 6 is an exhaust port. Specific embodiments In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0020] The purpose of the present invention is to provide a thick gate oxidation process method for improving the threshold voltage stability of MOS devices, so as to solve the technical problem of how to effectively control and optimize the uniformity of gate dielectric charges.

[0021] The present invention will be further described in detail below with reference to the accompanying drawings: Embodiment 1 See Figure 1 , in an embodiment of the present invention, a thick gate oxidation process method for improving the threshold voltage stability of MOS devices is provided, including the following processes: Step 1, fully load silicon wafers 5 on the boat 3 of the vertical furnace tube 1, and place a CV test chip 4 inside the vertical furnace tube 1 to characterize the oxide layer dielectric charge characteristics at different positions in the vertical furnace 1; Specifically, the model of the vertical furnace tube 1 is KE-DD802V, the diameter of the vertical furnace tube 1 is 210 mm, the length is 1093 mm, and the groove spacing of the boat is 4.75 mm. The gate oxidation process temperature is 1000 °C, and the oxygen flow rate is set at 10 SLM.

[0022] Specifically, a thermal oxidation process is used in the vertical furnace tube 1 to oxidize the substrate to form an oxide layer. The oxidation process is a process in which silicon atoms of the substrate react with oxygen at high temperature to generate silicon dioxide. At high temperature, silicon atoms can diffuse from the silicon substrate to the oxide layer, so that a silicon-rich layer is formed at the interface between the oxide layer and the silicon substrate. The silicon atoms in the silicon-rich layer are positively charged, and the silicon-rich layer is the main source of fixed charges in the oxide layer dielectric.

[0023] In this embodiment, during the process of oxidizing substrate silicon atoms to form an oxide layer using an integrated circuit thermal oxidation process in the vertical furnace tube 1, silicon atoms react with oxygen at high temperature to generate silicon dioxide. At the same time, silicon atoms also diffuse from the interior of the silicon substrate towards the oxide layer, forming a silicon-rich layer at the interface between the oxide layer and the silicon substrate. The positively charged silicon atoms in the silicon-rich layer are the main source of fixed charges in the oxide layer medium, which has an important impact on the electrical properties of MOS devices. By controlling the formation process of the oxide layer, the characteristics of the silicon-rich layer can be regulated, thereby optimizing the performance of MOS devices.

[0024] Among them, in the step of placing MOS capacitor chips with CV characteristics at different positions in the vertical furnace tube during the oxidation process, different positions of the vertical furnace tube 1 include the mouth end, the middle section, and the tail end of the vertical furnace tube. The MOS capacitor chips are respectively placed at the mouth end, the middle section, and the tail end of the vertical furnace tube, and silicon wafers 5 are placed at the remaining positions.

[0025] In this embodiment, when the gate dielectric thickness on the surface of the silicon wafer 5 is greater than 800 angstroms, the oxidation process changes from a surface reaction to a mass transport process, and the uniformity of the oxide film quality is greatly affected by the uniformity of the gas distribution during the process.

[0026] In this embodiment, silicon wafers 5 are placed at other positions in the vertical furnace tube. The silicon wafers 5 usually have the same size and shape as the MOS capacitor chips, but do not have the CV characteristic measurement function. By filling with silicon wafers 5, the airflow situation in the actual product process can be simulated, making the experimental results consistent with the product operation process.

[0027] The CV test chip 4 includes several test points. Each CV chip is tested at 3 points, including the upper, middle, and lower test points. The test positions are shown in Figure 2 as shown. Among them, the CV test chip measures its capacitance-voltage characteristic curve, and then calculates the flat-band voltage value representing the dielectric charge information in the oxide layer. When the flat-band voltage values corresponding to the test chips at different positions and the test points in different test chips are more uniform, the charge distribution in the oxide layer is uniform; otherwise, the charge distribution in the oxide layer is non-uniform.

[0028] Step 2, the vertical furnace tube 1 intakes air through the air inlet 2 and exhausts air through the exhaust port 6. The airflow in the vertical furnace tube 1 flows from top to bottom. A deviation experiment is conducted on the exhaust air volume of the gate oxidation process and the distance between adjacent products to obtain experimental results. According to the experimental results, the influence of the process exhaust air volume and the distance between adjacent silicon wafers on the charge uniformity of the oxide layer in the furnace is determined, realizing the improvement of the stability of the threshold voltage of thick-gate MOS devices.

[0029] Specifically, the biasing experiment includes gradually adjusting the exhaust air volume of the vertical furnace tube and performing CV characteristic tests on MOS capacitor wafers at each exhaust air volume to obtain CV characteristic results. Regarding the placement method of the biased product wafers, the biasing experiment is carried out when there is no slot between the products, with a 1-slot interval, a 2-slot interval, a 3-slot interval, and a 4-slot interval between the products, respectively, to verify the influence on the consistency of the grown oxide layer charge.

[0030] In this embodiment, the obtained CV (capacitance-voltage) characteristic results are analyzed to compare the test results under different conditions.

[0031] Among them, the magnitude of the exhaust air volume directly affects the gas flow velocity in the furnace tube. Excessive or too small exhaust air volume may both generate turbulence and affect the consistency of the grown film quality.

[0032] Specifically, according to the test results feedback by the CV test wafers 4 at different positions under different exhaust air pressures, the pressure range of the exhaust air volume is 175 - 195 pa.

[0033] Specifically, the CV characteristic results include capacitance-voltage curves. By comparing the capacitance-voltage curves under different exhaust air volumes and evaluating based on the capacitance-voltage curves, the uniformity of the oxide layer charge distribution is obtained.

[0034] Specifically, by testing the capacitance-voltage characteristic curve of the CV wafer, the flat-band voltage value that can characterize the amount of charge in the dielectric is calculated. When the flat-band voltage test results of the test wafers at different positions in the furnace are more consistent, the charge in the grown oxide layer in the furnace is more uniform. The oxide layer charge information is obtained by comparing the test results under different exhaust air volumes.

[0035] In this embodiment, by testing the CV characteristics of MOS capacitor wafers, the amount of charge in the dielectric layer can be characterized by the measured flat-band voltage value of the MOS structure. A KE-DD802V type vertical furnace tube (with a chamber furnace tube diameter of 210 mm and a length of 1093 mm) is selected for the process experiment. The exhaust air volume of the furnace tube is biased. One CV test wafer 4 is placed at each of the inlet end, the middle section, and the tail end of the furnace, and the other positions are filled with silicon wafers 5. Measurements are taken at the upper, middle, and lower points within each MOS capacitor wafer to obtain measurement values; and the standard deviation is calculated based on the measurement values between and within the CV test wafers 4. The threshold voltage stability of the MOS device is determined according to the standard deviation. Among them, if the standard deviation is smaller, the data is more concentrated, the uniformity is better, and the threshold voltage stability of the MOS device is better.

[0036] In this embodiment, the oxidation menu adopts the dry oxygen process, with a temperature of 1000 °C and an oxygen flow rate set at 10 SLM to ensure full saturation in the furnace. To ensure the adequacy of the gas flow contact within and between the wafers, the spacing between adjacent two wafers 5 is offset by 1 slot, 2 slots, 3 slots, and 4 slots respectively.

[0037] The method provided in the embodiment of the present invention shows that when the exhaust air is at 175 Pa - 195 Pa, the product spacing is 2 - 3 slots, and the inter-wafer spacing is between 9 mm and 15 mm, the flat-band voltage Vfb RANGE in the furnace is significantly improved, decreasing from 0.055 V of the baseline to 0.025 V. For details, see Figure 1 Under different exhaust air settings, the CV results of the monitoring wafers at different positions (the furnace mouth, middle, and tail) are shown in Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 。When the exhaust air setting is 210 Pa, when verifying and optimizing the placement of wafers with spaced slots, when the spacing is 2 - 3 slots, the flat-band voltage Vfb RANGE in the furnace decreases from 0.055 V of the baseline to about 0.030 V. For details, see Figure 8 。 Figure 3 The block diagram of the test data of the monitoring wafers in the furnace shown, each block diagram represents 3 wafers (upper, middle, and lower) in the furnace, with 3 points on each wafer, a total of several data. The CV monitoring data block diagrams at other different positions represent the CV wafers detected at the upper, middle, or lower part of the furnace, such as the 3-point test data in Figure 1 。 Figure 7 It is a schematic diagram of the product placement interval.

[0038] According to Figure 9 shown, in the case of a larger wafer spacing, the gas flow entering the wafer surface in all directions is relatively gentle, and the turbulence decreases; after the wafer spacing decreases, the influence of the gas flow in all directions on the wafer surface intensifies, and the turbulence increases.

[0039] According to Figure 10 shown, when the wafer spacing remains unchanged, after the exhaust air decreases, the gas retained in the furnace intensifies, the gas flow in all directions forms disturbances, the stability of the gas flow entering the wafer surface in all directions deteriorates, and the gas flow turbulence on the wafer surface is aggravated.

[0040] In summary, the present invention provides a thick gate oxidation process method for improving the threshold voltage stability of MOS devices. By precisely controlling the oxidation process, it is possible to ensure that the thickness and quality of the oxide layer are uniform, thereby affecting the threshold voltage of MOS devices. In the oxidation process of the present invention, MOS capacitor chips with CV characteristics are placed, which can monitor the quality change of the oxide layer in real time. By conducting a bias experiment on the exhaust air volume of the vertical furnace tube, the influence of different exhaust air volumes on the CV characteristics of MOS capacitor chips can be studied, which helps to discover the internal relationship between process parameters and MOS device performance, thereby optimizing process parameters and improving the threshold voltage stability of MOS devices. After the present invention improves the control of the charge uniformity in the oxidation dielectric layer within and between wafers, it can reduce the influence of the charge change in the dielectric layer on the substrate surface potential, and can improve problems such as the consistency of the threshold voltage of MOS devices and the stability of the bipolar device gain.

[0041] By monitoring the CV characteristics of MOS capacitor chips, the present invention can timely detect deviations and abnormalities in the process, and thus take targeted measures for adjustment. This helps to reduce the influence of process deviations on the performance of MOS devices and improve the reliability and consistency of the devices.

[0042] By changing the equipment exhaust parameters and wafer placement methods, the present invention effectively optimizes the uniformity of the gas flow in the furnace and weakens the influence of turbulence or circulation on the charges in the film quality. By confirming the relationship between the bias of different exhaust pressures and the charge uniformity of the oxide layer grown in the furnace, it helps to reveal the potential connection between the exhaust pressure and the gate dielectric charge uniformity. At the same time, by pulling the product spacing, optimizing the gas flow on the product surface, the influence on the charge uniformity of the grown dielectric is verified. By optimizing the exhaust pressure and product placement spacing, the charge uniformity in the gate dielectric can be improved, thereby improving the threshold voltage stability of MOS devices. Based on the in-depth analysis of the test results feedback from test chips at different positions, the charge uniformity within and between wafers can be comprehensively evaluated, thus ensuring the stability and consistency of the entire process.

[0043] The present invention conducts bias experiments by systematically adjusting the pressure settings of the exhaust system. These experiments aim to explore the change in the charge distribution uniformity during the growth of the oxide layer in the furnace under different exhaust pressures. The experimental results show that reasonable exhaust pressure settings can significantly reduce the instability of the gas flow in the furnace and promote the uniform distribution of charges during the growth of the oxide layer. Through data analysis, the potential connection between the exhaust pressure and the gate dielectric charge uniformity is revealed. In addition to adjusting the exhaust parameters, the present invention also innovates the traditional wafer placement method. By optimizing the arrangement spacing of products (such as wafers) in the furnace, the gas flow condition on the product surface is improved, and the charge distribution difference caused by uneven gas flow is reduced. Experiments prove that appropriately increasing or decreasing the product spacing can significantly affect the charge uniformity during the growth of the gate dielectric, providing a new dimension for the fine-tuning of process parameters.

[0044] By combining the optimization of the exhaust air pressure and the product placement spacing, the present invention not only improves the threshold voltage stability of MOS devices, but also enhances the overall performance and reliability of the devices. The present invention adopts the method of multi-position test chips to comprehensively evaluate the charge uniformity within and between silicon wafers. By deeply analyzing the test results of test chips at different positions, we can accurately judge the improvement degree of the optimization measures on the charge uniformity. This not only ensures the stability and consistency of the entire process, but also provides data support for the continuous improvement of subsequent processes.

[0045] Example 2 A MOS device with optimized threshold voltage consistency obtained by the thick gate oxidation process method for improving the threshold voltage stability of MOS devices as described above.

[0046] In summary, by finely regulating the exhaust air parameters and improving the wafer placement method, this process method effectively optimizes the uniformity of the gas flow in the furnace, thereby ensuring the uniformity of the charge distribution in the gate dielectric during growth. This improvement directly enhances the threshold voltage consistency of MOS devices, making the devices produced in the same batch closer in performance and reducing the performance differences caused by process fluctuations. The optimized charge uniformity of the gate dielectric not only improves the threshold voltage consistency, but also enhances the performance stability of the device under long-term working conditions. By deeply analyzing and verifying the influence of different process parameters on the charge uniformity of the gate dielectric, this process method establishes a complete process control system. This significantly improves the controllability and repeatability of the production process, reduces the rejection rate and scrap rate during production, and improves production efficiency.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications or equivalent replacements can still be made to the specific embodiments of the present invention, and any modification or equivalent replacement that does not depart from the spirit and scope of the present invention shall be covered by the protection scope of the claims of the present invention.

Claims

1. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices, characterized in that The process includes the following steps: Full load arrange silicon wafers (5) on the boat (3) of the vertical furnace tube (1), and place CV test wafers (4) inside the vertical furnace tube (1) to characterize the oxide layer dielectric charge characteristics at different positions inside the vertical furnace (1). The vertical furnace tube (1) intakes air through the air inlet (2) and exhausts air through the exhaust port (6). The air flow inside the vertical furnace tube (1) flows from top to bottom. Conduct a bias experiment on the exhaust air volume of the gate oxidation process and the distance between adjacent two products to obtain experimental results. Determine the influence of the process exhaust air volume and the distance between adjacent silicon wafers on the uniformity of the oxide layer charge in the furnace, thereby improving the stability of the threshold voltage of the thick gate MOS device.

2. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The model of the vertical furnace tube (1) is KE-DD802V.

3. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The groove pitch of the boat (3) is 4.75 mm.

4. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The gate dielectric thickness on the surface of the silicon wafer (5) is above 800 angstroms.

5. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that The CV test wafers (4) are respectively located at the inlet end, middle section and tail end of the vertical furnace tube (1) to detect the charge quantity in the silicon wafers (5) at the inlet end, middle section and tail end of the vertical furnace tube (1).

6. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The CV test wafer (4) includes a plurality of test points.

7. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The CV test wafer (4) measures its capacitance-voltage characteristic curve, and then calculates the flat-band voltage value representing the dielectric charge information in the oxide layer. When the flat-band voltage values corresponding to different positions of the CV test wafers (4) and different test points in the CV test wafers (4) are more uniform, the oxide layer charge distribution is uniform; otherwise, the oxide layer charge distribution is non-uniform.

8. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that, The pressure range of the optimal exhaust air volume for the gate oxidation process is 175 - 195 pa.

9. A thick gate oxidation process method for improving the threshold voltage stability of MOS devices according to claim 1, characterized in that In the step of determining the influence of the process exhaust air volume and the distance between adjacent silicon wafers on the uniformity of the oxide layer charge in the furnace according to the experimental results, it is determined that the experimental results of the number of spacer grooves between adjacent silicon wafers (5) on the CV test wafers (4) at different positions show that the optimal spacer distance between adjacent silicon wafers is 2 to 3 groove positions, that is, 9 mm to 15 mm.

10. A MOS device with optimized threshold voltage consistency obtained by the thick gate oxidation process method for improving the threshold voltage stability of the MOS device according to any one of claims 1 to 9.

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