Method for reducing grid height difference and reducing grid side wall height

Abstract

The invention provides a method for reducing a grid height difference and reducing the height of a grid side wall and a semiconductor structure, and the method comprises the following steps: S1, providing a substrate, the substrate comprises a PMOS region and an NMOS region, the PMOS region and the NMOS region are respectively provided with a grid structure, and the grid structures of the PMOS region and the NMOS region have a height difference; siGe epitaxial layers are arranged on the two sides of the PMOS region gate structure; forming a gate side wall layer on the gate structure; s2, depositing a sacrificial layer on the surface of the substrate; s3, synchronously and downwards etching the sacrificial layer and the gate side wall layer to eliminate the height difference of the gate structure; s4, performing back etching on the sacrificial layer to expose part of the gate side wall layer; s5, etching the upper gate side wall layer; s6, removing the residual sacrificial layer; and S7, etching the lower gate side wall layer to obtain a gate side wall structure. And through two-step back etching and grid electrode side wall step-by-step etching, the height difference of the grid electrode structure is eliminated, the height of the side wall is reduced, and meanwhile other parameters of the grid electrode side wall are controlled.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor manufacturing, and particularly relates to a method for reducing the gate height difference and the height of the gate sidewall. Background Art

[0002] In the 28HK process, the SiGe process will cause the loss of the gate silicon oxide hard mask layer in the gate structure of the PMOS region, resulting in a gate height difference. The existence of the height difference will affect other process steps such as film growth, photoresist coating, and etching load. It is necessary to eliminate this height difference through multiple oxidation deposition and chemical mechanical polishing cycles in subsequent processes to achieve height consistency. This process is cumbersome and costly. In addition, if the height of the gate sidewall is too high, the step after chemical enhanced sub-atmospheric lamp nitridation deposition (CESL) of silicon nitride will also be relatively high, which may affect the subsequent silicon oxide filling; at the same time, in the process of thinning the interlayer dielectric (ILD0) at the bottom of the gate, due to the selectivity of treating silicon oxide and silicon nitride, the gate sidewall may remain protruding, forming a "horn", which is difficult to handle whether using pre-deposition and then etch-back (PREB) or dual chemical mechanical polishing (Dual CMP). Usually, the parameters of the gate sidewall deposition film thickness and etching process must simultaneously meet the requirements of key result parameters such as the final sidewall width, sidewall height, and residual silicon oxide on the substrate. However, these parameters lack the flexibility of independent adjustment, and the adjustment range is also greatly limited. Especially for the height of the gate sidewall, the process of adjusting its height often has a greater impact on other result parameters, and it is difficult to achieve all results meeting the design requirements.

[0003] Based on the above problems, it is necessary to provide a method that can eliminate the gate height difference earlier and reduce the height of the gate sidewall in a larger range while having a smaller impact on other key result parameters. Summary of the Invention

[0004] The present invention is to solve all or part of the above-mentioned existing technical problems, and provides a method for reducing the gate height difference and the height of the gate sidewall. On the basis of having a smaller impact on other key result parameters, it can simultaneously eliminate the gate structure height difference between the NMOS region and the PMOS region earlier, and at the same time reduce the height of the gate sidewall in a larger range: after depositing the gate sidewall film, deposit a sacrificial layer, and through two-step etch-back and step-by-step etching of the gate sidewall, control to eliminate the gate structure height difference and reduce the height of the gate sidewall, so as to achieve simultaneous elimination of the gate structure height difference and reduction of the height of the gate sidewall in a larger range, and at the same time control parameters such as the final width of the gate sidewall and the remaining thickness of silicon oxide after sidewall etching.

[0005] The present invention provides a method for reducing the gate height difference and the height of the gate sidewall, including the following steps:

[0006] S1: Provide a substrate, on which a PMOS region and an NMOS region are included. Gate structures are formed on both the PMOS region and the NMOS region, and there is a height difference between the gate structure of the PMOS region and the gate structure of the NMOS region; SiGe epitaxial layers are formed on both sides of the gate structure on the PMOS region; a gate sidewall layer is formed on the gate structure; S2: Deposit a sacrificial layer on the surface of the substrate; S3: Simultaneously etch the sacrificial layer and the gate sidewall layer downward until the surfaces of the gate structures of both the PMOS region and the NMOS region are exposed simultaneously, eliminating the height difference of the gate structures; S4: Perform a re-etch on the sacrificial layer to expose a part of the gate sidewall layer; S5: Etch the upper gate sidewall layer; S6: Remove the remaining sacrificial layer; S7: Etch the lower gate sidewall layer to obtain a gate sidewall structure. Through two-step re-etching and step-by-step etching of the gate sidewalls, control the elimination of the height difference of the gate structures and reduce the height of the gate sidewalls, so as to achieve the simultaneous elimination of the height difference of the gate structures and a large-scale reduction of the height of the gate sidewalls, and at the same time control parameters such as the final width of the gate sidewalls and the remaining thickness of the silicon oxide after sidewall etching.

[0007] The gate structure sequentially includes a hafnium oxide layer, a titanium nitride layer, a pseudo-gate silicon material layer, a gate silicon nitride hard mask layer, and a gate silicon oxide hard mask layer from bottom to top; the surface of the gate structure is the gate silicon oxide hard mask layer.

[0008] The gate sidewall layer sequentially includes a first doped silicon nitride sidewall, a second silicon oxide sidewall, and a third silicon nitride sidewall from inside to outside.

[0009] In step S2, the sacrificial layer can be spin-coated carbon or a carbon-containing organic film filled; the formed sacrificial layer is a flat surface, protecting the lower gate sidewall layer during subsequent etching processes.

[0010] In step S3, the simultaneous downward etching uses low-selectivity timed etching, with the same etching rate for the sacrificial layer and the gate sidewall layer; eliminate the height difference between the gate structures of the PMOS region and the NMOS region; simultaneously etch the sacrificial layer and the gate structures of the PMOS region and the NMOS region to eliminate the height difference.

[0011] In step S4, the re-etch uses high-selectivity timed etching of the gate sidewall layer by the sacrificial layer; only the sacrificial layer is etched during the etching process, and the gate sidewall layer and the gate structure are basically not affected, and the etching amount of the sacrificial layer can be controlled by controlling the etching time.

[0012] In step S5, high-selectivity timed etching of the upper gate sidewall layer using silicon nitride for silicon oxide is used to etch the upper gate sidewall layer without affecting the gate structure.

[0013] In step S5, the remaining thickness of the sacrificial layer after etching is not less than 10 mm, which can protect the lower gate sidewall layer.

[0014] In step S6, the remaining sacrificial layer is removed by ashing; only the remaining sacrificial layer can be removed by ashing without affecting other film layers.

[0015] A semiconductor structure is also provided, which is prepared according to any one of the methods for reducing the gate height difference and lowering the sidewall height. The height of the obtained gate sidewall structure is 15 - 55 nm lower than the height of the gate sidewall layer in S1.

[0016] Compared with the prior art, the beneficial effects of the present invention mainly include the following: A method for reducing the gate height difference and lowering the gate sidewall height is provided. On the basis of having little influence on other key result parameters, the gate structure height difference can be reduced and the gate sidewall height can be lowered in a large range. After depositing the gate sidewall film, a sacrificial layer is deposited. By two-step re-etching and step-by-step etching of the gate sidewall, the gate structure height difference is controlled and eliminated, and the gate sidewall height is lowered. While achieving the elimination of the gate structure height difference and a large range of reduction of the gate sidewall height, parameters such as the final width of the gate sidewall and the remaining thickness of silicon oxide after sidewall etching are controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a step schematic diagram of a method for reducing the gate height difference and lowering the gate sidewall height provided by the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following description and drawings fully disclose the specific implementation schemes of the present invention, enabling those skilled in the art to practice them. Other implementation schemes may include structural, logical, electrical, process, and other changes. The embodiments only represent possible variations. Unless explicitly required, the individual components and functions are optional, and the order of operations can be changed. Some parts and features of some embodiments can be included in or replaced by parts and features of other embodiments.

[0020] Example 1

[0021] The SiGe process can cause loss of the gate oxide hard mask layer of the gate in the PMOS region, resulting in a gate height difference. The existence of the height difference will affect other process steps, and it is necessary to eliminate this height difference through multiple oxidation deposition and chemical mechanical polishing cycles in subsequent processes to achieve height uniformity. This process is cumbersome and costly. After the SiGe process, the gate sidewall deposition and etching processes are carried out. If the height of the gate sidewall is too high, the steps after the subsequent CESL-deposited silicon nitride will also be relatively high in shape, which may affect the subsequent silicon oxide filling. Due to the selectivity of processing silicon oxide and silicon nitride in the ILD0 thinning process, the gate sidewall may remain protruding, forming a "bull's horn" that is difficult to process. For the height of the gate sidewall, the process of adjusting its height often has a greater impact on other parameters such as the width of the gate sidewall, and it is difficult to achieve all results that meet the design requirements.

[0022] To solve the above problems, a method for reducing the gate height difference and lowering the gate sidewall height is provided, as Figure 1 shown, including the following steps:

[0023] S1: Provide a substrate, which includes a PMOS region and an NMOS region. Gate structures are formed on both the PMOS region and the NMOS region, and there is a height difference between the gate structure in the PMOS region and the gate structure in the NMOS region; SiGe epitaxial layers are formed on both sides of the gate structure on the PMOS region; a gate sidewall layer is formed on the gate structure; the gate structure sequentially includes a hafnium oxide layer, a titanium nitride layer, a dummy gate silicon material layer, a gate silicon nitride hard mask layer, and a gate oxide hard mask layer from bottom to top. The dummy gate silicon material layer can be polysilicon, amorphous silicon, etc.; the surface of the gate structure is the gate oxide hard mask layer; the gate sidewall layer sequentially includes a first doped silicon nitride sidewall, a second silicon oxide sidewall, and a third silicon nitride sidewall from inside to outside.

[0024] S2: Deposit a sacrificial layer on the surface of the substrate. The sacrificial layer can be spin-on carbon or a carbon-containing organic film with a flat surface after filling, such as a bottom anti-reflection coating (barc), etc. The formed sacrificial layer has a flat surface; in this embodiment, the material used for the sacrificial layer is spin-on carbon, which protects the lower part of the gate sidewall layer in the subsequent etching process.

[0025] S3: Etch the sacrificial layer and the gate sidewall layer downward synchronously until the surfaces of the gate structures in both the PMOS region and the NMOS region are exposed simultaneously, eliminating the height difference of the gate structures; the synchronous downward etching adopts low-selectivity timed etching, and the etching rates of the sacrificial layer and the gate sidewall layer are the same, eliminating the height difference between the gate structures in the PMOS region and the NMOS region.

[0026] S4: Perform an etch-back on the sacrificial layer to expose part of the gate sidewall layer. The etch-back uses a high selectivity etch of the sacrificial layer to the gate sidewall layer for a fixed time. During the etching process, only the sacrificial layer is etched, and the gate sidewall layer and the gate structure are basically not affected. The etching amount of the sacrificial layer can be controlled by controlling the etching time.

[0027] S5: Etch the upper gate sidewall layer; perform a high selectivity etch of silicon nitride to silicon oxide for a fixed time on the upper gate sidewall layer to etch the upper gate sidewall layer without affecting the gate structure. After etching, the gate sidewall layer protected by the sacrificial layer is the lower gate sidewall layer. After step S5, the height of the gate sidewall layer can be reduced by 0 - 40 nm; the remaining thickness of the sacrificial layer after etching is not less than 10 nm to ensure that the remaining sacrificial layer is sufficient to protect the lower gate sidewall layer.

[0028] S6: Remove the remaining sacrificial layer; the remaining sacrificial layer is removed by ashing, and only the remaining sacrificial layer can be removed without affecting other film layers.

[0029] S7: Etch the lower gate sidewall layer to obtain the gate sidewall structure; the etching of the lower gate sidewall is similar to the original sidewall etching process; according to the morphology and requirements, one-step or multi-step processes with different selectivities of silicon nitride to silicon oxide can be selected.

[0030] Example 2

[0031] This example provides a semiconductor structure, which is prepared according to the method for reducing the gate height difference and lowering the gate sidewall height described in Example 1. The height of the obtained gate sidewall structure is 15 - 55 nm lower than the height of the gate sidewall layer in S1.

[0032] The present invention has been improved on the basis of the prior art. Through two-step etch-back and step-by-step etching of the gate sidewall, the height difference of the gate structure is controlled and eliminated, and the height of the gate sidewall is reduced to achieve the purpose of eliminating the height difference of the gate structure and reducing the height of the gate sidewall in a large range, while controlling parameters such as the final width of the gate sidewall and the remaining thickness of silicon oxide after sidewall etching.

[0033] It should be understood that some commonly used English nouns or letters used in this application for the convenience of clear description are only for exemplary reference rather than limiting interpretation or specific usage, and the protection scope of this application should not be limited by their possible Chinese translations or specific letters. It should also be noted that in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for reducing the gate height difference and lowering the gate sidewall height, characterized in that, The method includes the following steps: S1: Provide a substrate, on which a PMOS region and an NMOS region are included. Gate structures are formed on both the PMOS region and the NMOS region, and there is a height difference between the gate structure of the PMOS region and the gate structure of the NMOS region; SiGe epitaxial layers are formed on both sides of the gate structure on the PMOS region; a gate sidewall layer is formed on the gate structure; S2: Deposit a sacrificial layer on the surface of the substrate; S3: Simultaneously etch the sacrificial layer and the gate sidewall layer downward until the surfaces of the gate structures of both the PMOS region and the NMOS region are exposed simultaneously, eliminating the height difference of the gate structures; S4: Perform a re-etch on the sacrificial layer to expose a part of the gate sidewall layer; S5: Etch the upper gate sidewall layer; S6: Remove the remaining sacrificial layer; S7: Etch the lower gate sidewall layer to obtain a gate sidewall structure.

2. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein The gate structure sequentially includes a hafnium oxide layer, a titanium nitride layer, a pseudo-gate silicon material layer, a gate silicon nitride hard mask layer, and a gate silicon oxide hard mask layer from bottom to top; the surface of the gate structure is the gate silicon oxide hard mask layer.

3. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein The gate sidewall layer sequentially includes a first doped silicon nitride sidewall, a second silicon oxide sidewall, and a third silicon nitride sidewall from inside to outside.

4. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein In step S2, the sacrificial layer can be spin-coated carbon or a carbon-containing organic film filled.

5. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein In step S3, the simultaneous downward etching uses a low selectivity timed etching, and the etching rates of the sacrificial layer and the gate sidewall layer are the same, eliminating the height difference of the gate structures between the PMOS region and the NMOS region.

6. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, characterized in that, In step S4, the re-etch uses a high selectivity timed etching of the sacrificial layer for the gate sidewall layer.

7. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein In step S5, the upper gate sidewall layer is etched using a high selectivity timed etching of silicon nitride for silicon oxide.

8. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, wherein In step S5, the remaining thickness of the sacrificial layer after etching is not less than 10 mm.

9. The method for reducing the gate height difference and lowering the gate sidewall height according to claim 1, characterized in that In step S6, the remaining sacrificial layer is removed by ashing.

10. A semiconductor structure, characterized in that, Prepared according to the method for reducing the gate height difference and lowering the gate sidewall height according to any one of claims 1-9, the height of the obtained gate sidewall structure is 15-55 nm lower than the height of the gate sidewall layer in S1.

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