Display panel, preparation method and electronic equipment

Abstract

The invention discloses a display panel, a preparation method and electronic equipment, the display panel comprises a low-temperature polycrystalline silicon thin film transistor, and the low-temperature polycrystalline silicon thin film transistor comprises a first source drain electrode, a low-temperature polycrystalline silicon active layer, a gate insulating layer, a gate electrode, a planarization layer and a second source drain electrode. The low-temperature polycrystalline silicon active layer is provided with a first surface facing the substrate and a second surface opposite to the substrate, and the grid electrode surrounds the side wall of the low-temperature polycrystalline silicon active layer and covers a partial area of the second surface. The gate insulating layer is arranged between the gate and the low-temperature polycrystalline silicon active layer, the first source-drain electrode is connected with the first surface, and the second source-drain electrode is connected with the second surface through a first via hole penetrating through the dielectric layer, the gate and the gate insulating layer, so that the low-temperature polycrystalline silicon active layer can form a vertical structure, and carriers can avoid a crystal boundary; transmission between the first source-drain electrode and the second source-drain electrode in the vertical direction as much as possible is achieved, and the mobility is improved.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel, a preparation method and an electronic device. Background Art

[0002] In a display panel, low temperature poly-silicon (LTPS) thin film transistors (TFTs) are usually used as switching devices. In the process, since the active layer of the LTPS TFT usually adopts an excimer laser annealing (ELA) process to convert amorphous silicon into polycrystalline silicon. However, during the melting and recrystallization process of the ELA process, many grain boundaries (such as defects, atomic dislocations, dangling bonds, etc.) will be formed. Due to the existence of grain boundaries, carriers will be continuously captured by the defects in the grain boundaries when migrating in the active layer, resulting in a decrease in mobility. Summary of the Invention

[0003] Embodiments of this application provide a display panel, a preparation method and an electronic device to improve the mobility of LTPS TFTs.

[0004] In a first aspect, an embodiment of the present application provides a display panel. The display panel includes a substrate and a low-temperature polycrystalline silicon thin-film transistor disposed on the substrate. The low-temperature polycrystalline silicon thin-film transistor includes a first source-drain electrode, a low-temperature polycrystalline silicon active layer, a gate insulating layer, a gate electrode, a planarization layer, and a second source-drain electrode. Among them, the first source-drain electrode is disposed on the substrate, and at least a part of the low-temperature polycrystalline silicon active layer is disposed on the first source-drain electrode. The low-temperature polycrystalline silicon active layer has a first surface facing the substrate and a second surface facing away from the substrate. The gate electrode at least partially surrounds the sidewalls of the low-temperature polycrystalline silicon active layer, and at least a part of the gate electrode is disposed on the second surface, that is, the gate electrode is annularly arranged and covers a partial area of the upper surface of the low-temperature polycrystalline silicon active layer facing away from the substrate, which can increase the area of the channel wrapped by the gate electrode, increase the channel length, and can well control the conduction and closing of the channel region. The gate insulating layer is disposed between the gate electrode and the low-temperature polycrystalline silicon active layer to insulate the gate electrode from the low-temperature polycrystalline silicon active layer through the gate insulating layer. The planarization layer is at least partially disposed on the gate electrode, and the second source-drain electrode is disposed on the planarization layer. Moreover, the low-temperature polycrystalline silicon thin-film transistor further includes a first via hole that passes through the gate electrode, the gate insulating layer, and the planarization layer, and the first via hole is used to expose a partial area of the second surface. In addition, at least a part of the first source-drain electrode is connected to the first surface, at least a part of the second source-drain electrode is disposed on the planarization layer, at least a part of the second source-drain electrode is disposed in the first via hole, at least a part of the second source-drain electrode is connected to the second surface, and the second source-drain electrode is insulated from the gate electrode, which can form a vertical structure of the low-temperature polycrystalline silicon active layer. With this setting, when the low-temperature polycrystalline silicon active layer of the LTPS TFT in the embodiment of the present application is conducting, carriers can be made to transport in the low-temperature polycrystalline silicon active layer as much as possible in the vertical direction, so that the carriers can avoid grain boundaries and transport between the first source-drain electrode and the second source-drain electrode as much as possible in the vertical direction. This can not only improve the mobility, but also reduce the characteristic differences of LTPS TFTs at different positions in the display panel, improve the uniformity of low-gray-scale display, and reduce the adverse effects of polycrystalline silicon grain boundaries on the reliability of LTPS TFTs, thereby improving the display effect. In particular, when the LTPS TFT provided by the embodiment of the present application is applied to a display panel with a higher refresh rate (such as 240 Hz or higher), the display effect of the display panel can be improved.

[0005] In some embodiments, the low-temperature polycrystalline silicon active layer includes a channel region, a first ohmic contact region disposed on the side of the channel region facing the substrate, and a second ohmic contact region disposed on the side of the channel region facing away from the substrate. The first surface includes the surface of the first ohmic contact region facing the substrate, so that the first source-drain electrode is connected to the channel region through the first ohmic contact region, reducing the contact resistance. And the second surface includes the surface of the second ohmic contact region facing away from the substrate, so that the second source-drain electrode is connected to the channel region through the second ohmic contact region, reducing the contact resistance.

[0006] In some embodiments, the positive projection of the first ohmic contact region on the substrate overlaps at least partially with the positive projection of the channel region on the substrate. For example, if the positive projection of the first ohmic contact region on the substrate coincides with the positive projection of the channel region on the substrate, the first ohmic contact region and the channel region are stacked vertically. With this arrangement, carriers can be made to transport in the channel region as much as possible in the vertical direction. Alternatively, if the positive projection of the first ohmic contact region on the substrate partially overlaps with the positive projection of the channel region on the substrate, the first ohmic contact region is vertically embedded in the channel region. With this arrangement, part of the lower surface of the low-temperature polysilicon active layer facing the substrate is the first ohmic contact region, and the remaining regions are the channel regions, which can increase the area of the channel region wrapped by the gate and further better control the conduction and cutoff of the channel region.

[0007] In some embodiments, the positive projection of the second ohmic contact region on the substrate overlaps at least partially with the positive projection of the channel region on the substrate. For example, if the positive projection of the second ohmic contact region on the substrate coincides with the positive projection of the channel region on the substrate, the second ohmic contact region and the channel region are stacked vertically. With this arrangement, carriers can be made to transport in the channel region as much as possible in the vertical direction. Alternatively, if the positive projection of the second ohmic contact region on the substrate partially overlaps with the positive projection of the channel region on the substrate, the second ohmic contact region is vertically embedded in the channel region. With this arrangement, part of the upper surface of the low-temperature polysilicon active layer facing away from the substrate is the second ohmic contact region, and the remaining regions are the channel regions, which can increase the area of the channel region wrapped by the gate and further better control the conduction and cutoff of the channel region.

[0008] Moreover, the vertical direction is perpendicular to the plane of the substrate. Additionally, the substrate is a glass substrate or a flexible substrate.

[0009] In some embodiments, the first ohmic contact region, the channel region, and the second ohmic contact region are stacked vertically, and the positive projection of the first ohmic contact region on the substrate, the positive projection of the channel region on the substrate, and the positive projection of the second ohmic contact region on the substrate coincide.

[0010] In some embodiments, in order to insulate the second source / drain from the gate, the gate on the second surface has an opening, and the positive projection of the gate on the substrate covers the region of the positive projection of the low-temperature polysilicon active layer on the substrate except for the positive projection of the opening on the substrate. Moreover, the positive projection of the first via on the substrate is located within the positive projection of the opening on the substrate, and the distance between the outer boundary of the positive projection of the first via on the substrate and the outer boundary of the positive projection of the opening on the substrate is greater than 0, and the region between the second source / drain and the gate at the sidewall of the opening is filled with an insulating layer to achieve insulation performance.

[0011] In some embodiments, the second source / drain is in direct contact with the gate insulating layer at the sidewall of the first via.

[0012] In some embodiments, the gate insulation layer covers the area of ​​the low-temperature polysilicon active layer in the orthographic projection of the substrate except for the orthographic projection of the first via in the substrate, and the gate insulation layer extends on the second surface to the side wall of the first via, so that the second source and drain are in direct contact with the gate insulation layer at the side wall of the first via.

[0013] In some embodiments, a gap is provided between the second source / drain and the gate insulating layer at the sidewall of the first via hole, and a region between the second source / drain and the gate insulating layer at the sidewall of the first via hole is filled with an insulating layer.

[0014] In some embodiments, the gate insulating layer covers the area of ​​the low-temperature polysilicon active layer in the orthographic projection of the substrate except the orthographic projection of the opening in the substrate, and the gate insulating layer extends to the side wall of the opening on the second surface. In addition, the area between the second source and drain and the gate insulating layer extending to the side wall of the opening is filled with an insulating layer.

[0015] In some embodiments, the insulating layer may be made of a material capable of achieving electrical insulation. For example, the insulating layer includes but is not limited to a planarization layer, so that the second source and drain are insulated from the gate at the sidewall of the opening by the planarization layer, reducing the process steps.

[0016] In some embodiments, the first source and drain have a first electrode portion and a second electrode portion that are connected to each other, the orthographic projection of the low-temperature polysilicon active layer on the substrate covers the orthographic projection of the first electrode portion on the substrate, the orthographic projection of the low-temperature polysilicon active layer on the substrate does not overlap with the orthographic projection of the second electrode portion on the substrate, and is connected to the first surface of the low-temperature polysilicon active layer through the first electrode portion, and then the first electrode portion is led out through the second electrode portion. In addition, the LTPS TFT also includes source and drain lead-out lines, which are arranged on the side of the planarization layer facing away from the substrate, and the source and drain lead-out lines are insulated from the second source and drain. In addition, the planarization layer also has a second via hole that penetrates the planarization layer, the second via hole exposes a partial area of ​​the second electrode portion, and the source and drain lead-out lines are connected to the second electrode portion through the second via hole to lead out the first ohmic contact area through the first source and drain and the source and drain lead-out lines.

[0017] In some embodiments, the first source and drain electrodes include a transparent conductive oxide material layer with a single layer or a multi-layer structure, or a metal material layer with a single layer or a multi-layer structure.

[0018] In some embodiments, the second source and drain electrodes include a transparent conductive oxide material layer with a single layer or a multi-layer structure, or a metal material layer with a single layer or a multi-layer structure.

[0019] Exemplarily, the materials of the transparent conductive oxide material layer include, but are not limited to: indium tin oxide (ITO), antimony tin oxide (ATO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), magnesium indium oxide (MIO), one of the metal oxides composed of titanium, zinc, zirconium, antimony, indium, tin, aluminum, and silicon, carbon nanotubes, graphene, etc.

[0020] Exemplarily, the metal material layer includes, but is not limited to: Ti, Al, Mo, etc. For example, when the first source / drain is a metal material layer with a multi-layer structure, it can be set as a multi-layer structure of TiAlTi. When the second source / drain is a metal material layer with a multi-layer structure, it can also be set as a multi-layer structure of TiAlTi.

[0021] In some embodiments, the orthographic projection of the first source / drain on the substrate covers the orthographic projection of the low-temperature polycrystalline silicon active layer on the substrate. Especially when the first source / drain includes a single-layer or multi-layer metal material layer, by making the orthographic projection of the first source / drain on the substrate cover the orthographic projection of the low-temperature polycrystalline silicon active layer on the substrate, the first source / drain can be used as a light-shielding layer to reduce the adverse effects of light on the performance of the low-temperature polycrystalline silicon active layer.

[0022] In some embodiments, a buffer layer is further included between the first source / drain and the substrate to improve the adhesion of the first source / drain through the buffer layer.

[0023] In some embodiments, in order to further achieve light shielding, a light-shielding layer can be provided between the buffer layer and the substrate, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the low-temperature polycrystalline silicon active layer on the substrate.

[0024] In some embodiments, the material of the channel region is an intrinsically doped low-temperature polycrystalline silicon material. And, the material of the first ohmic contact region is a heavily doped low-temperature polycrystalline silicon material to improve the ohmic contact. Also, the material of the second ohmic contact region is a heavily doped low-temperature polycrystalline silicon material to improve the ohmic contact.

[0025] In some embodiments, the display panel includes a display area, the display area includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes: an organic light-emitting diode and a pixel circuit connected to the organic light-emitting diode; the pixel circuit includes one or more low-temperature polycrystalline silicon thin-film transistors. With this setting, the display panel can be set as an organic light-emitting diode (OLED) display panel. Further, the OLED display panel in the present application can be a flexible OLED display panel.

[0026] In some embodiments, the display panel includes a display area, the display area includes a plurality of sub-pixels, and at least one of the plurality of sub-pixels includes: a pixel electrode and one or more low-temperature polysilicon thin-film transistors connected to the pixel electrode. With this arrangement, the display panel can be set as a liquid crystal display panel.

[0027] In some embodiments, a plurality of gate lines are further provided in the display panel, and the gate lines can be set to be of the same layer and the same material as the gates. In this way, there is no need to add an additional process for preparing the gate lines. Only through one patterning process, the patterns of the respective gate lines and the respective gates can be formed, which can simplify the manufacturing process, save production costs, and improve production efficiency.

[0028] In some embodiments, a plurality of data lines are further provided in the display panel, and the data lines can be set to be of the same layer and the same material as the second source / drain electrodes. In this way, there is no need to add an additional process for preparing the data lines. Only through one patterning process, the patterns of the respective data lines and the respective second source / drain electrodes can be formed, which can simplify the manufacturing process, save production costs, and improve production efficiency. Of course, the data lines and the second source / drain electrodes can also be arranged in different layers, which is not limited herein.

[0029] In some embodiments, the display panel further includes a non-display area, the non-display area includes a gate driving circuit, the gate driving circuit includes a plurality of cascaded shift register units, and the shift register unit includes one or more low-temperature polysilicon thin-film transistors. With this arrangement, the adverse effects of polysilicon grain boundaries on the mobility, characteristics, and reliability of the LTPS TFTs in the shift register unit can be reduced, and the display effect can be improved.

[0030] In a second aspect, an embodiment of the present application further provides an electronic device, including a display panel as described in the first aspect or various implementation manners of the first aspect. Exemplarily, the electronic device includes but is not limited to a terminal device. Among them, the terminal device includes but is not limited to a mobile phone, a computer, a television, a set-top box, a watch, a personal computer (PC), a wearable device (such as a smart watch, a virtual reality (VR) glasses, a smart bracelet), a vehicle-mounted display device, etc. In addition, the principle of the electronic device for solving problems is similar to that of the foregoing display panel. Therefore, the implementation of the electronic device can refer to the implementation of the foregoing display panel, and the repeated parts will not be described again.

[0031] In some embodiments, it further includes: a system controller, a timing controller, and a source driver chip. The system controller is connected to the timing controller, and the timing controller is connected to the source driver chip and the gate driver circuit. The system controller processes the display gray-scale information in a series of steps in each display frame and then sends it to the timing controller. The timing controller processes the received display gray-scale information in a series of steps and then sends it to the source driver chip, and sends a control signal to the gate driver circuit. The gate driver circuit responds to the control signal and sends a gate scanning signal to the gate line. The source driver chip receives the display gray-scale information, converts the received display gray-scale information into an analog signal, and then inputs an actual data voltage to the connected data line.

[0032] In a third aspect, an embodiment of the present application further provides a method for manufacturing a display panel, including:

[0033] Form a first source-drain on the substrate;

[0034] Adopt an excimer laser annealing process to form a low-temperature polycrystalline silicon material layer on the side of the first source-drain facing away from the substrate;

[0035] Adopt a patterning process to pattern the low-temperature polycrystalline silicon material layer to form a low-temperature polycrystalline silicon active layer. The low-temperature polycrystalline silicon active layer has a first surface facing the substrate and a second surface facing away from the substrate, and the first surface is connected to the first source-drain;

[0036] Deposit a gate insulating layer and a gate on the side of the low-temperature polycrystalline silicon active layer facing away from the substrate, so that the gate at least partially surrounds the sidewall of the low-temperature polycrystalline silicon active layer, and the gate also extends along the sidewall of the low-temperature polycrystalline silicon active layer to the second surface, and the gate encloses an opening on the second surface. The gate insulating layer is disposed between the gate and the low-temperature polycrystalline silicon active layer;

[0037] Form a planarization layer on the side of the gate facing away from the substrate, and form a first via hole penetrating the planarization layer. The first via hole also penetrates the opening;

[0038] Form a second source-drain on the side of the planarization layer facing away from the substrate, and connect the second source-drain to the second surface through the first via hole, and the second source-drain is insulated from the gate.

[0039] In order to form the low-temperature polycrystalline silicon material layer, in some embodiments, an excimer laser annealing process is adopted to form a low-temperature polycrystalline silicon material layer on the side of the first source-drain facing away from the substrate, including but not limited to the following process:

[0040] Adopt an excimer laser annealing process to form a first polycrystalline silicon layer on the side of the first source-drain facing away from the substrate, and heavily dope at least part of the region of the first polycrystalline silicon layer to form a first ohmic contact region;

[0041] Using an excimer laser annealing process, a second polysilicon layer is formed on the side of the first polysilicon layer facing away from the substrate, and the second polysilicon layer is intrinsically doped to form a channel region;

[0042] Using an excimer laser annealing process, a third polysilicon layer is formed on the side of the second polysilicon layer facing away from the substrate, and at least part of the third polysilicon layer is heavily doped to form a second ohmic contact region.

[0043] To form the first polysilicon layer, in some embodiments, an excimer laser annealing process is used to form a first polysilicon layer on the side of the first source / drain facing away from the substrate, and at least part of the first polysilicon layer is heavily doped to form a first ohmic contact region, including but not limited to the following process: a deposition process is used to deposit a first amorphous silicon layer on the side of the first source / drain facing away from the substrate. Thereafter, an excimer laser annealing process is used to crystallize the first amorphous silicon layer into a first polysilicon layer. Thereafter, an ion implantation process is used to heavily dope at least part of the crystallized first polysilicon layer to form a first ohmic contact region.

[0044] To form the first polysilicon layer, in some embodiments, an excimer laser annealing process is used to form a first polysilicon layer on the side of the first source / drain facing away from the substrate, and at least part of the first polysilicon layer is heavily doped to form a first ohmic contact region, including but not limited to the following process: a deposition process is used to deposit a first amorphous silicon layer on the side of the first source / drain facing away from the substrate, and during the deposition of the first amorphous silicon layer, at least part of the first amorphous silicon layer is heavily doped. Thereafter, an excimer laser annealing process is used to crystallize the first amorphous silicon layer into a first polysilicon layer, and the heavily doped region forms a first ohmic contact region.

[0045] To form the second polysilicon layer, in some embodiments, the excimer laser annealing process is used to form a second polysilicon layer on the side of the first polysilicon layer facing away from the substrate, and the second polysilicon layer is intrinsically doped to form the channel region, including but not limited to the following process: a deposition process is used to deposit a second amorphous silicon layer on the side of the first polysilicon layer facing away from the substrate. Thereafter, the excimer laser annealing process is used to crystallize the second amorphous silicon layer into a second polysilicon layer. Thereafter, an ion implantation process is used to intrinsically dope the crystallized second polysilicon layer to form the channel region.

[0046] In order to form the second polysilicon layer, in some embodiments, the excimer laser annealing process is used to form the second polysilicon layer on the side of the first polysilicon layer facing away from the substrate, and the second polysilicon layer is intrinsically doped to form the channel region, including but not limited to the following process: A deposition process is used to deposit a second amorphous silicon layer on the side of the first polysilicon layer facing away from the substrate, and during the deposition of the second amorphous silicon layer, the second amorphous silicon layer is intrinsically doped. Thereafter, the excimer laser annealing process is used to crystallize the second amorphous silicon layer into a second polysilicon layer.

[0047] In order to form the third polysilicon layer, in some embodiments, the excimer laser annealing process is used to form the third polysilicon layer on the side of the second polysilicon layer facing away from the substrate, and at least a part of the third polysilicon layer is heavily doped to form the second ohmic contact region, including but not limited to the following process: A deposition process is used to deposit a third amorphous silicon layer on the side of the second polysilicon layer facing away from the substrate. Thereafter, the excimer laser annealing process is used to crystallize the third amorphous silicon layer into a third polysilicon layer. Thereafter, an ion implantation process is used to heavily dope at least a part of the crystallized third polysilicon layer to form the second ohmic contact region; or,

[0048] In order to form the third polysilicon layer, in some embodiments, the excimer laser annealing process is used to form the third polysilicon layer on the side of the second polysilicon layer facing away from the substrate, and at least a part of the third polysilicon layer is heavily doped to form the second ohmic contact region, including but not limited to the following process: A deposition process is used to deposit a third amorphous silicon layer on the side of the second polysilicon layer facing away from the substrate, and during the deposition of the third amorphous silicon layer, at least a part of the third amorphous silicon layer is heavily doped. Thereafter, the excimer laser annealing process is used to crystallize the third amorphous silicon layer into a third polysilicon layer, and the heavily doped region forms the second ohmic contact region.

[0049] In order to form the gate insulating layer and the gate, in some embodiments, the gate insulating layer and the gate are sequentially deposited on the side of the low-temperature polysilicon active layer facing away from the substrate, including but not limited to the following process: The gate insulating layer and the gate material layer are sequentially deposited on the side of the low-temperature polysilicon active layer facing away from the substrate. Thereafter, a patterning process is used to pattern the gate material layer to form a gate covering the active layer.

[0050] In some embodiments, it further includes: When forming the gate covering the active layer, a gate line is also formed. Description of the Drawings

[0051] Figure 1A schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0052] Figure 2 A schematic circuit diagram of a pixel circuit and an OLED provided by an embodiment of the present application;

[0053] Figure 3 A signal timing diagram of a pixel circuit in one display frame provided by an embodiment of the present application;

[0054] Figure 4 A schematic cross-sectional structure diagram of an LTPS TFT in the prior art;

[0055] Figure 5 A schematic cross-sectional structure diagram when carriers are transported in an active layer in the prior art;

[0056] Figure 6 Another schematic cross-sectional structure diagram of a display panel in an embodiment of the present application;

[0057] Figure 7 A top-view structure diagram of a low-temperature polysilicon active layer, a gate insulating layer, and a gate in an embodiment of the present application;

[0058] Figure 8 A schematic cross-sectional structure diagram when carriers are transported in a low-temperature polysilicon active layer in an embodiment of the present application;

[0059] Figures 9a to 9f Respectively, a schematic cross-sectional structure diagram during the preparation process of a display panel in an embodiment of the present application;

[0060] Figure 10 Another schematic cross-sectional structure diagram of a display panel in an embodiment of the present application;

[0061] Figures 11a to 11j Respectively, a schematic cross-sectional structure diagram during the preparation process of a display panel in an embodiment of the present application;

[0062] Figure 12 Another schematic cross-sectional structure diagram of a display panel in an embodiment of the present application;

[0063] Figure 13a And Figure 13b Respectively, another schematic cross-sectional structure diagram during the preparation process of a display panel in an embodiment of the present application;

[0064] Figure 14 Another schematic cross-sectional structure diagram of a display panel in an embodiment of the present application;

[0065] Figure 15 Another schematic cross-sectional structure diagram of a display panel in an embodiment of the present application.

[0066] Reference numerals

[0067] 100 - Display panel; 110a / 110b / 110c - Gate driving circuit; 120 - Pixel circuit; 130 - Substrate; 140 - Low-temperature polycrystalline silicon thin-film transistor; 141 - First source-drain; 1411 - First electrode portion; 1412 - Second electrode portion; 142 - Low-temperature polycrystalline silicon active layer; 1421 - First ohmic contact region; 1422 - Second ohmic contact region; 1423 - Channel region; 143 - Gate insulating layer; 144 - Gate; 145 - Planarization layer; 1461 - Source-drain lead-out line; 1462 - Second source-drain; 147 - Insulating layer; 150 - Low-temperature polycrystalline silicon material layer; 151 - First polysilicon layer; 152 - Second polysilicon layer; 153 - Third polysilicon layer; 160 - Gate material layer; 200 - Timing controller; 300 - System controller; 400 - Source driver chip; GK0 - Opening; GK1 - First via; GK2 - Second via; GK3 - Gate insulating layer via; 11 - Active layer; AA - Display area; BB - Non-display area; spx - Sub-pixel; GAa / GAb / GAc - Gate line, DA - Data line. Detailed implementation manners

[0068] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings. The specific operation methods in the method embodiments can also be applied to the device embodiments or system embodiments. It should be noted that in the description of the present application, "a plurality of" can be understood as "at least two". In addition, it should be understood that in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying an order. In the description of the present application, "disposed on" can be "directly disposed on" or "indirectly disposed on", and the embodiments of the present application do not make specific limitations in this regard.

[0069] It should be noted that the same reference numerals in the accompanying drawings of the present application represent the same or similar structures, and thus repeated descriptions thereof will be omitted. The words expressing positions and directions described in the present application are all illustrated by taking the accompanying drawings as examples, but can also be changed according to needs, and all the changes made are included in the protection scope of the present application. The accompanying drawings of the present application are only used to illustrate the relative positional relationship and do not represent the true proportion.

[0070] The display panel provided by this application can be widely applied to various electronic devices. For example, the electronic devices include, but are not limited to, terminal devices. Among them, the terminal devices include, but are not limited to, mobile phones, computers, televisions, set-top boxes, watches, personal computers (PCs), wearable devices (such as smart watches, virtual reality (VR) glasses, smart bracelets), in-vehicle display devices, etc., which are not listed one by one here. It can be understood that the specific implementation manners of the electronic devices can be determined according to the actual application scenarios and are not limited herein.

[0071] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of this application. Referring to Figure 1 , the electronic device includes: a display panel 100, a timing controller 200, a system controller 300, and a source driver chip 400. Exemplarily, the display panel 100 includes: a display area AA and a non-display area BB. The display area AA includes a plurality of pixel units, and each pixel unit includes sub-pixels spx of multiple different colors. For example, the pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that color mixing can be performed through red, green, and blue to achieve color display. Alternatively, the pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that color mixing can be performed through red, green, blue, and white to achieve color display. Of course, in actual applications, the light-emitting colors of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment and are not limited herein.

[0072] The display area AA also includes a plurality of gate lines GAa, a plurality of gate lines GAb, a plurality of gate lines GAc, and a plurality of data lines DA. Among them, one row of sub-pixels is connected to one gate line GAa, one gate line GAb, and one gate line GAc, and one column of sub-pixels is connected to one data line. Of course, it is also possible to connect one row of sub-pixels to two gate lines GAa, two gate lines Gab, two gate lines GAc, and one column of sub-pixels to two data lines. In actual applications, the number of gate lines GAa, Gab, and GAc connected to one row of sub-pixels and the number of data lines connected to one column of sub-pixels can be determined according to the requirements of the actual application scenario and are not limited herein.

[0073] The non-display area BB includes gate driving circuits 110a, 110b, and 110c. Among them, the gate driving circuit 110a is respectively connected to a plurality of gate lines GAa, and the gate driving circuit 110a sends a first gate scanning signal to each gate line GAa. The gate driving circuit 110b is connected to a plurality of gate lines GAb, and the gate driving circuit 110b sends a second gate scanning signal to each gate line GAb. The gate driving circuit 110c is connected to a plurality of gate lines GAc, and the gate driving circuit 110c sends a third gate scanning signal to each gate line GAc. In addition, the non-display area BB may further include circuits with other functions, such as an Electro-Static Discharge (ESD) circuit, etc.

[0074] The source driver chip 400 is bonded in the non-display area BB through a Chip On Film (COF), and the source driver chip is also connected to the data line DA through the COF to input a data voltage to the data line DA. Exemplarily, a plurality of source driver chips 400 may be provided, and different source driver chips 400 are connected to different data lines. Figure 1 Only two source driver chips 400 are taken as an example for illustration. In practical applications, the number of source driver chips can be determined according to the resolution of the display panel and the data output channels of the source driver chip. For example, for a display panel with a resolution of 3840*2160, the number of data lines in the display panel can be 3840*3. If a source driver chip has 1920 data output channels, then 6 (i.e., 3840*3 / 1920) source driver chips need to be correspondingly set for this display panel.

[0075] The system controller 300 is connected to the timing controller 200, and the timing controller 200 is respectively connected to the gate driving circuits 110a - 110c and the source driving chip 400. During specific operation, the system controller 300 obtains the display gray - scale information of the picture to be displayed in each display frame (the display gray - scale information includes digital signals carrying corresponding gray - scale values corresponding to each sub - pixel in the display panel), and after a series of processing on the display gray - scale information, it sends it to the timing controller 200. After receiving the display gray - scale information, the timing controller 200 sends control signals (such as frame trigger signals and clock control signals) to the gate driving circuits 110a - 110c and after a series of processing on the display gray - scale information, it sends it to the source driving chip 400. The gate driving circuits 110a - 110c respectively input the first gate scanning signal to the third gate scanning signal to the gate lines G Aa - 110c according to the received control signals. The source driving chip 400 receives the display gray - scale information, converts the received display gray - scale information into an analog signal, and then inputs the actual data voltage to the data lines D A to write the data voltage into the sub - pixels, so as to enable the display panel to realize the picture display function. In addition, the system controller 300 can be a field - programmable gate array (FPGA), a general - purpose central processing unit (CPU), a general - purpose processor, a digital signal processing (DSP), an application - specific integrated circuit (ASIC), a system - on - chip (SOC), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute various exemplary logic blocks, modules, and circuits described in combination with the disclosure of this application. The above - mentioned system controller can also be a combination that realizes computing functions, such as including a combination of one or more microprocessors, a combination of DSP and microprocessors, etc.

[0076] OLED has advantages such as self - emission and low power consumption. The display panel provided in the embodiment of this application can be an OLED display panel, and each sub - pixel can include an OLED and a pixel circuit for driving the OLED to emit light. Among them, the OLED includes an anode, an organic light - emitting layer, and a cathode arranged in a stacked manner. The pixel circuit is connected to the anode of the OLED. And the pixel circuit can include multiple transistors such as a driving transistor and a data - writing transistor, and a storage capacitor. Further, the OLED display panel in this application can be a flexible OLED display panel.

[0077] Figure 2A circuit schematic diagram of a pixel circuit and an OLED provided by an embodiment of the present application. Refer to Figure 2 , the pixel circuit 120 may include a driving transistor M0, a data writing transistor M1, a threshold compensation transistor M2, a first light-emitting control transistor M3, a second light-emitting control transistor M4, a first reset control transistor M5, a second reset control transistor M6, and a storage capacitor CST. Among them, the gate of the data writing transistor M1 is connected to the gate line GAa, the first pole of the data writing transistor M1 is connected to the data line DA, and the second pole of the data writing transistor M1 is connected to the first pole of the driving transistor M0. The gate of the threshold compensation transistor M2 is connected to the gate line GAa, the first pole of the threshold compensation transistor M2 is connected to the gate of the driving transistor M0, and the second pole of the threshold compensation transistor M2 is connected to the second pole of the driving transistor M0. The gate of the first light-emitting control transistor M3 is connected to the gate line GAb, the first pole of the first light-emitting control transistor M3 is connected to the first power supply line VDD, and the second pole of the first light-emitting control transistor M3 is connected to the first pole of the driving transistor M0. The gate of the second light-emitting control transistor M4 is connected to the gate line GAb, the first pole of the second light-emitting control transistor M4 is connected to the second pole of the driving transistor M0, and the second pole of the second light-emitting control transistor M4 is connected to the anode of the OLED. The gate of the first reset control transistor M5 is connected to the gate line GAc, the first pole of the first reset control transistor M5 is connected to the initialization signal line VINIT, and the second pole of the first reset control transistor M5 is connected to the gate of the driving transistor M0. The gate of the second reset control transistor M6 is connected to the gate line GAc, the first pole of the second reset control transistor M6 is connected to the initialization signal line VINIT, and the second pole of the second reset control transistor M6 is connected to the anode of the OLED. The cathode of the OLED is connected to the second power supply line VSS. The first end of the storage capacitor CST is connected to the first power supply line VDD, and the second end of the storage capacitor CST is connected to the gate of the driving transistor M0. And, the voltage of the first power supply line VDD is a high-level voltage, and the voltage of the second power supply line VSS is a ground voltage or a low-level voltage. In addition, the first pole of the above transistor may be the source electrode, the second pole is the drain electrode, or the first pole is the drain electrode and the second pole is the source electrode.

[0078] Figure 3 A signal timing diagram of the pixel circuit provided by an embodiment of the present application in a display frame. Refer to Figure 2 And Figure 3 , gaa represents the first gate scanning signal transmitted on the gate line GAa, gab represents the second gate scanning signal transmitted on the gate line Gab, and gac represents the third gate scanning signal transmitted on the gate line GAc. Among them, the reset stage T1, the data input stage T2, and the light-emitting stage T3 in a display frame FA are mainly selected.

[0079] In the reset stage T1, the first reset control transistor M5 is turned on under the control of the low level of the signal gac, and provides the initialization signal transmitted on the initialization signal line VINIT to the gate of the driving transistor M0 to initialize the gate of the driving transistor M0. The second reset control transistor M6 is turned on under the control of the low level of the signal gac, and provides the initialization signal transmitted on the initialization signal line VINIT to the anode of the OLED to initialize the anode of the OLED. The remaining transistors are all turned off.

[0080] In the data input stage T2, the data writing transistor M1 is turned on under the control of the low level of the signal gaa, and provides the data voltage transmitted on the data line DA to the first pole of the driving transistor M0. The threshold compensation transistor M2 is turned on under the control of the low level of the signal gaa, and conducts the gate and the second pole of the driving transistor M0, so that the driving transistor M0 forms a diode connection mode, and the voltage of the gate of the driving transistor M0 becomes Vda + Vth. Vda represents the data voltage, and Vth represents the threshold voltage of the driving transistor M0. The remaining transistors are all turned off.

[0081] In the light emitting stage T3, the first light emitting control transistor M3 is turned on under the control of the low level of the signal gab, and provides the high voltage vdd transmitted on the first power supply line VDD to the first pole of the driving transistor M0, so that the voltage of the first pole of the driving transistor M0 is vdd. And, the voltage of the gate of the driving transistor M0 is Vda + Vth, so the driving transistor M0 generates a driving current IL, and the driving current IL satisfies the formula: IL = K(Vda - vdd) 2 . Wherein, K = 1 / 2 * μ * Cox * W / L, μ is the mobility of the driving transistor M0, Cox is the gate insulation layer capacitance, and W / L is the channel width-to-length ratio of the driving transistor M0. The second light emitting control transistor M4 is turned on under the control of the low level of the signal gaa, and conducts the second pole of the driving transistor M0 and the anode of the OLED, so that the driving current IL is input into the OLED to drive the OLED to emit light.

[0082] The above is only illustrated by taking the Figure 2 shown pixel circuit as an example. The pixel circuit in the present application may also be a pixel circuit with other structural forms, which is not limited herein.

[0083] Since transistors using LTPS material as the active layer can be made thinner, smaller, and have lower power consumption, etc., based on this, the material of the active layer of one or part or all of the transistors in the pixel circuit can be set to LTPS, so that this part of the transistors is set to LTPS TFTs. Exemplarily, one transistor or part of the transistors or all of the driving transistor M0, data writing transistor M1, threshold compensation transistor M2, first light emission control transistor M3, second light emission control transistor M4, first reset control transistor M5, and second reset control transistor M6 can be set to LTPS TFTs.

[0084] Figure 4 FIG. is a schematic cross-sectional structure diagram of an LTPS TFT in the prior art. Refer to Figure 4 , in the existing LTPS TFTs, the source electrode and the drain electrode are respectively connected to both ends of the active layer 11, and the gate electrode is directly above the active layer 11. Since the ELA crystallization process will generate large and small spikes (i.e., grain boundaries) on the surface of polysilicon, as Figure 5 shown, Figure 5 FIG. is a schematic cross-sectional structure diagram when the active layer in the prior art conducts carrier transmission. There is an angle between the grain boundary and the horizontal direction F1 (the angle is greater than 0° and less than or equal to 90°). When the LTPS TFT is turned on, since the active layer 11 is arranged along the horizontal direction F1, the carriers need to cross the grain boundaries of polysilicon in the active layer 11, and the defects in the grain boundaries will capture the carriers, resulting in a decrease in mobility and unstable characteristics of the LTPS TFT. Moreover, since the number of grain boundaries in the active layers of different LTPS TFTs may be different, there are differences in the characteristics of LTPS TFTs at different positions in the display panel, resulting in uneven low gray-scale display. In addition, due to the existence of grain boundary defects, the reliability of the LTPS TFT will gradually degrade during the process of repeatedly capturing and releasing carriers, resulting in display anomalies.

[0085] Therefore, the embodiments of the present application provide a vertical structure LTPS TFT applied to a display panel. When the LTPS TFT is turned on, the carriers can be transmitted without crossing the grain boundaries, which can not only improve the mobility, but also reduce the characteristic differences of LTPS TFTs at different positions in the display panel, improve the uniformity of low gray-scale display, and reduce the adverse effects of polysilicon grain boundaries on the reliability of the LTPS TFT, thereby improving the display effect.

[0086] Figure 6 FIG. is a schematic cross-sectional structure diagram of a display panel in the embodiments of the present application. Figure 7 FIG. is a schematic top view structure diagram of a low-temperature polysilicon active layer, a gate insulating layer, and a gate electrode in the embodiments of the present application. Refer to Figure 6 and Figure 7, the display panel in the embodiment of the present application includes: a substrate 130 and an LTPS TFT 140 disposed on the substrate 130. The LTPS TFT 140 may include: a first source-drain 141, a low-temperature polysilicon active layer 142, a gate insulating layer 143, a gate 144, a planarization layer 145, and a second source-drain 1462. Among them, the first source-drain 141 may be at least partially disposed on the substrate 130, the low-temperature polysilicon active layer 142 may be at least partially disposed on the first source-drain 141, the gate insulating layer 143 may be at least partially disposed on the low-temperature polysilicon active layer 142, the gate 144 may be at least partially disposed on the gate insulating layer 143, the planarization layer 145 may be at least partially disposed on the gate 144, and the second source-drain 1462 may be at least partially disposed on the planarization layer 145.

[0087] In the embodiment of the present application, the low-temperature polysilicon active layer 142 has a first surface S1 facing the substrate 130 and a second surface S2 facing away from the substrate 130. Among them, at least a partial region of the first surface S1 is in direct contact with the first source-drain 141, connecting the first surface S1 and the first source-drain 141. The gate 144 may be at least partially disposed around the sidewall of the low-temperature polysilicon active layer 142, and the gate 144 may be at least partially disposed on the second surface S2. Exemplarily, during preparation, after surrounding the sidewall of the low-temperature polysilicon active layer 142 with the gate 144, the gate 144 may be extended along the sidewall of the low-temperature polysilicon active layer 142 to its second surface S2. With this setting, the area of the channel wrapped by the gate 144 can be increased, the channel length can be increased, and the conduction and cut-off of the channel region 1423 can be well controlled. In addition, the gate insulating layer 143 is disposed between the gate 144 and the low-temperature polysilicon active layer 142, and the gate 144 and the low-temperature polysilicon active layer 142 can be insulated through the gate insulating layer 143.

[0088] In the embodiment of the present application, a part of the gate 144 disposed on the second surface S2 may be provided with an opening GK0, and the opening GK0 may be filled with an insulating layer 147.

[0089] In some embodiments, the LTPS TFT 140 may have a first via GK1. Among them, the first via GK1 may penetrate through the planarization layer 145, the insulating layer 147, and the gate insulating layer 143, and the first via GK1 may expose a partial region of the second surface S2. The second source-drain 1462 may be at least partially disposed in the first via GK1, the second source-drain 1462 may be at least partially in direct contact with the second surface S2, and the second source-drain 1462 may be connected to the second surface S2.

[0090] In some embodiments, refer to Figure 6 and Figure 7, the second source / drain 1462 can be in direct contact with the gate insulating layer 143 at the sidewall of the first via GK1.

[0091] In some embodiments, the second source / drain 1462 and the gate 144 can be insulated by an insulating layer 147. Exemplarily, the material of the insulating layer 147 can be a material capable of achieving electrical insulation. It can enable the low-temperature polysilicon active layer 142 to form a vertical structure, and enable carriers to be transmitted between the first source / drain 141 and the second source / drain 1462 as much as possible along the vertical direction F0.

[0092] In some embodiments, in order to reduce the process preparation steps, the insulating layer 147 can be a part of the planarization layer 145. With this setting, when depositing the planarization layer 145, the material of the planarization layer 145 can be used to fill the opening GK0. Then, the first via GK1 is formed, and the size of the first via GK1 is smaller than the size of the opening GK0. In this way, the insulation performance between the second source / drain 1462 and the gate 144 can be achieved by setting the planarization layer 145. Figure 7 Taking the shapes of the opening GK0 and the first via GK1 as rectangles as an example, in specific implementation, the shapes of the opening GK0 and the first via GK1 can also be circular, elliptical, polygonal, etc., which are not limited herein.

[0093] With this setting, referring to Figure 8 , Figure 8 is a schematic cross-sectional structure diagram for carrier transmission in the low-temperature polysilicon active layer in the embodiments of the present application. When the channel region 1423 of the low-temperature polysilicon active layer 142 in the LTPS TFT in the embodiments of the present application is turned on, it can enable carriers to be transmitted in the channel region 1423 as much as possible along the vertical direction F0, so that the carriers can avoid grain boundaries and be transmitted between the first source / drain and the second source / drain as much as possible along the vertical direction. This can not only improve the mobility, but also reduce the characteristic differences of LTPS TFTs at different positions in the display panel, improve the uniformity of low gray-scale display, and reduce the adverse effects of polysilicon grain boundaries on the reliability of LTPS TFTs, thereby improving the display effect. In particular, when the LTPS TFT 140 provided in the embodiments of the present application is applied to a display panel with a higher refresh rate (such as 240 Hz or higher), it can improve the display effect of the display panel.

[0094] It can be understood that the first source / drain 141 can be a source, and the second source / drain 1462 can be a drain, or the first source / drain 141 can be a drain, and the second source / drain 1462 can be a source. Moreover, the horizontal direction F1 is parallel to the plane of the substrate 130, and the vertical direction F0 is perpendicular to the plane of the substrate 130. In addition, the substrate 130 can be a glass substrate, a flexible substrate, etc., which are not limited herein.

[0095] In an embodiment of the present application, the low-temperature polycrystalline silicon active layer 142 has a channel region, and the material of the channel region is an intrinsically doped low-temperature polycrystalline silicon material. Referring to Figure 6 , if the entire region of the low-temperature polycrystalline silicon active layer 142 is the channel region, then in this embodiment, the surface of the channel region facing the substrate 130 is the first surface S1, and the surface of the channel region facing away from the substrate 130 is the second surface S2.

[0096] In a specific implementation, the first source / drain 141 may include a transparent conductive oxide material layer with a single-layer or multi-layer structure. Exemplarily, the material of the transparent conductive oxide material layer includes but is not limited to: indium tin oxide (ITO), antimony tin oxide (ATO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), magnesium indium oxide (MIO), one of the metal oxides composed of titanium, zinc, zirconium, antimony, indium, tin, aluminum, and silicon, carbon nanotubes, graphene, etc. Alternatively, the first source / drain 141 may also include a metal material layer with a single-layer or multi-layer structure. Exemplarily, the metal material layer includes but is not limited to: Ti, Al, Mo, etc. And when the first source / drain 141 is a multi-layer structure metal material layer, it may be set as a multi-layer structure of TiAlTi.

[0097] Exemplarily, the orthographic projection of the first source / drain 141 on the substrate 130 may cover the orthographic projection of the low-temperature polycrystalline silicon active layer 142 on the substrate 130. Especially when the first source / drain 141 includes a metal material layer with a single-layer or multi-layer structure, by making the orthographic projection of the first source / drain 141 on the substrate 130 cover the orthographic projection of the low-temperature polycrystalline silicon active layer 142 on the substrate 130, the first source / drain 141 can be used as a light-shielding layer to reduce the adverse effect of light on the performance of the low-temperature polycrystalline silicon active layer 142.

[0098] In a specific implementation, the second source / drain may also include a metal material layer with a single-layer or multi-layer structure. Among them, the implementation manners of the transparent conductive oxide material layer and the metal material layer may refer to the above description.

[0099] Referring to Figure 1 And Figure 6 , a plurality of gate lines GAa to GAc may also be provided in the display panel, and the gate lines GAa to GAc and the gate 144 may be provided on the same layer and made of the same material. In this way, there is no need to add an additional process for preparing the gate lines GAa to GAc. Only through one patterning process, the patterns of the gate lines GAa to GAc and the gates 144 can be formed, which can simplify the preparation process, save production costs, and improve production efficiency. For example, referring to Figure 2 And Figure 6, if the LTPS in the embodiments of the present application is set as the data writing transistor M1 or the threshold compensation transistor M2, the gate line GAa is connected to the gate 144 of the data writing transistor M1 or the gate 144 of the threshold compensation transistor M2. If the LTPS in the embodiments of the present application is set as the first light emitting control transistor M3 or the second light emitting control transistor M4, the gate line GAb is connected to the gate 144 of the first light emitting control transistor M3 or the gate 144 of the second light emitting control transistor M4. If the LTPS in the embodiments of the present application is set as the first reset control transistor M5 or the second reset control transistor M6, the gate line GAc is connected to the gate 144 of the first reset control transistor M5 or the gate 144 of the second reset control transistor M6.

[0100] Referring to Figure 1 , a plurality of data lines DA are also provided in the display panel, and the data lines DA can be set on the same layer and of the same material. In this way, there is no need to add additional processes for preparing the data lines DA. Only through one patterning process, the patterns of the respective data lines DA can be formed, which can simplify the manufacturing process, save production costs, and improve production efficiency. Of course, the data lines can also be set in a different layer from the second source-drain electrode, which is not limited herein.

[0101] The LTPS TFTs in the embodiments of the present application can be applied to the pixel circuit, and one or more or all of the transistors in the pixel circuit are set as the LTPS TFTs in the present application. Based on this, the adverse effects of the polysilicon grain boundaries on the mobility, characteristics, and reliability of the LTPS TFTs in the pixel circuit can be reduced, and the display effect can be improved.

[0102] The LTPS TFTs in the embodiments of the present application can also be applied to the gate driving circuit 110a or the gate driving circuit 110b or the gate driving circuit 110c. Taking the gate driving circuit 110a as an example, the gate driving circuit 110a includes a plurality of cascaded shift register units, and one or some or all of the transistors in the shift register units are set as the LTPS TFTs in the present application. Based on this, the adverse effects of the polysilicon grain boundaries on the mobility, characteristics, and reliability of the LTPS TFTs in the shift register units can be reduced, and the display effect can be improved. In addition, the implementation manners of the gate driving circuit 110b or the gate driving circuit 110c can refer to the implementation manner of the gate driving circuit 110a, which will not be elaborated herein.

[0103] The display panel in the embodiments of the present application may also be a liquid crystal display panel. Exemplarily, a liquid crystal display panel generally includes an upper substrate and a lower substrate that are opposed to each other, and liquid crystal molecules encapsulated between the upper substrate and the lower substrate. A sub-pixel includes: a pixel electrode and one or more switching transistors connected to the pixel electrode. When displaying an image, since there is a voltage difference between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage applied to the common electrode, this voltage difference can form an electric field, so that the liquid crystal molecules are deflected under the action of this electric field. Since different intensities of the electric field cause different degrees of deflection of the liquid crystal molecules, the transmittance of the sub-pixels is different, so that the sub-pixels can achieve different gray-scale brightnesses, and thus the image display is realized. Moreover, some or all of the switching transistors can be set as the LTPS TFTs in the embodiments of the present application. Based on this, the adverse effects of polysilicon grain boundaries on the mobility, characteristics, and reliability of the LTPS TFTs in the shift register unit can be reduced, and the display effect can be improved. In addition, for the implementation manner of the gate driving circuit in the liquid crystal display panel, reference may also be made to the implementation manner of the gate driving circuit 110a, which will not be elaborated here.

[0104] To prepare Figure 6 Taking the structure of the display panel shown as an example, the preparation method provided by the embodiments of the present application may include the following contents:

[0105] Referring to Figure 9a , Figure 9a FIG. is a schematic cross-sectional structure diagram of the display panel in the embodiments of the present application during the preparation process. Exemplarily, a simple glass substrate or a flexible substrate formed by coating polyimide (PI) on the glass is used as the substrate 130 of the display panel. A first source-drain electrode 141 is formed on the substrate 130. For example, the ITO or AZO is sputtered on the buffer layer by a sputter process to form the first source-drain electrode 141 layer. Then, a patterning process is used to pattern the first source-drain electrode 141 layer to form the first source-drain electrode 141. Among them, the thickness of the first source-drain electrode 141 in the vertical direction F0 is about 200 nm to 300 nm. For example, the thickness of the first source-drain electrode 141 in the vertical direction F0 is 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, etc. Of course, the thickness of the first source-drain electrode 141 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario, which will not be limited here.

[0106] Referring to Figure 9b , Figure 9bAnother cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, using the ELA process, a polysilicon material layer is formed on the substrate 130, and the polysilicon material layer is subjected to intrinsic doping. For example, an amorphous silicon material layer is deposited using a deposition process such as PECVD. Then, using the ELA process, the amorphous silicon material layer is crystallized into a polysilicon material layer. Then, using the ion implantation process, intrinsic doping is performed in the crystallized polysilicon material layer. Alternatively, an amorphous silicon material layer is deposited using a deposition process such as PECVD, and during the deposition of the amorphous silicon material layer, the amorphous silicon material layer is subjected to intrinsic doping. Then, using the ELA process, the amorphous silicon material layer is crystallized into a polysilicon material layer. Using the patterning process, the polysilicon material layer is patterned to form the low-temperature polysilicon active layer 142. For example, using a photolithography process (exposure, development, etc.) and an etching process, the polysilicon material layer is patterned to form the low-temperature polysilicon active layer 142.

[0107] Referring to Figure 9c and Figure 9d , Figure 9c and Figure 9d Another cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, a gate insulating layer 143 and a gate electrode 144 are sequentially deposited on the side of the low-temperature polysilicon active layer 142 facing away from the substrate 130, so that the gate electrode 144 surrounds the sidewall of the low-temperature polysilicon active layer 142, and an opening GK0 is formed by enclosing on the second surface of the low-temperature polysilicon active layer 142. For example, referring to Figure 9c , using a deposition process such as PECVD, a gate insulating layer 143 is deposited on the side of the low-temperature polysilicon active layer 142 facing away from the substrate 130. Then, using a deposition process such as PECVD, a metal material (such as Mo) is deposited on the side of the gate insulating layer 143 facing away from the substrate 130 to form a gate material layer 160. Then, referring to Figure 9d, a patterning process is adopted to pattern the gate material layer 160 to form the gate 144 and also form gate lines GAa - GAc. For example, a lithography process (exposure, development, etc.) and an etching process are used to pattern the gate material layer 160 to form the gate 144 and the gate lines GAa - GAc. In addition, the thickness of the above-mentioned gate insulating layer 143 in the vertical direction F0 is approximately 100 nm - 150 nm. For example, the thickness of the gate insulating layer 143 in the vertical direction F0 is 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc. Of course, the thickness of the gate insulating layer 143 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited here. And, the thickness of the gate material layer 160 in the vertical direction F0 is approximately 200 nm - 250 nm. For example, the thickness of the gate material layer 160 in the vertical direction F0 is 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, etc. Of course, the thickness of the gate material layer 160 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited here.

[0108] Referring to Figure 9e , Figure 9e is another cross-sectional structure schematic diagram in the preparation process of the display panel in the embodiment of the present application. Exemplarily, a planarization layer 145 is formed on the side of the gate 144 facing away from the substrate 130, and a first via hole GK1 is formed through the planarization layer 145 and the gate insulating layer 143. The first via hole GK1 also passes through the opening GK0. For example, a deposition process such as PECVD is used to deposit the planarization layer 145 on the side of the gate 144 facing away from the substrate 130, or an organic planarization layer 145 is coated to form the planarization layer 145 on the side of the gate 144 facing away from the substrate 130. Then, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the planarization layer 145 and the gate insulating layer 143 to form the first via hole GK1. In addition, the thickness of the planarization layer 145 in the vertical direction F0 is approximately 500 nm - 600 nm. For example, the thickness of the planarization layer 145 in the vertical direction F0 is 500 nm, 520 nm, 540 nm, 560 nm, 580 nm, 600 nm, etc. Of course, the thickness of the planarization layer 145 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited here.

[0109] Referring to Figure 9f , Figure 9fAnother cross-sectional structure schematic diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, a second source-drain electrode 1462 is deposited on the side of the planarization layer 145 facing away from the substrate 130, and the second source-drain electrode 1462 is connected to the low-temperature polycrystalline silicon active layer 142 through the first via hole GK1. Moreover, in the vertical direction F0, the thickness of the second source-drain electrode 1462 is approximately 700 nm to 800 nm. For example, in the vertical direction F0, the thickness of the second source-drain electrode 1462 is 700 nm, 720 nm, 750 nm, 780 nm, 800 nm, etc. Of course, in the vertical direction F0, the thickness of the second source-drain electrode 1462 can also be determined according to the requirements of the actual application scenario, which is not limited herein. In specific implementation, a first Ti layer (the thickness of the first Ti layer in the vertical direction F0 can be approximately 50 nm) is deposited on the side of the planarization layer 145 facing away from the substrate 130 by using a deposition process such as PECVD. Then, an Al layer (the thickness of the Al layer in the vertical direction F0 can be approximately 650 nm) is deposited on the side of the first Ti layer facing away from the substrate 130 by using a deposition process such as PECVD. Then, a second Ti layer (the thickness of the second Ti layer in the vertical direction F0 can be approximately 50 nm) is deposited on the side of the Al layer facing away from the substrate 130 by using a deposition process such as PECVD. Then, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the first Ti layer, the Al layer, and the second Ti layer to form the second source-drain electrode 1462.

[0110] Figure 10 Another cross-sectional structure schematic diagram of the display panel in the embodiment of the present application, referring to Figure 10 , the display panel in the embodiment of the present application is deformed with respect to the implementation manner of the display panel in the Figure 6 illustrated embodiment. Only the differences between this embodiment and the above embodiment are described below, and the same parts are not elaborated herein. The difference between this embodiment and the Figure 6 illustrated embodiment is as follows: The low-temperature polycrystalline silicon active layer 142 includes a channel region 1423, a first ohmic contact region 1421 disposed on the side of the channel region 1423 facing the substrate 130, and a second ohmic contact region 1422 disposed on the side of the channel region 1423 facing away from the substrate 130. The first surface S1 includes the surface of the first ohmic contact region 1421 facing the substrate 130, so that the first source-drain electrode 141 can be connected to the channel region 1423 through the first ohmic contact region 1421, reducing the contact resistance. In addition, the second surface S2 includes the surface of the second ohmic contact region S2 facing away from the substrate 130, so that the second source-drain electrode 1462 can be connected to the channel region 1423 through the second ohmic contact region 1422, reducing the contact resistance.

[0111] Referring to Figure 10, the first source-drain 141 has a first electrode portion 1411 and a second electrode portion 1412 connected thereto. The orthographic projection of the low-temperature polysilicon active layer 142 on the substrate 130 covers the orthographic projection of the first electrode portion 1411 on the substrate 130, and the orthographic projection of the low-temperature polysilicon active layer 142 on the substrate 130 does not overlap with the orthographic projection of the second electrode portion 1412 on the substrate 130. It is connected to the first surface S1 of the low-temperature polysilicon active layer 142 through the first electrode portion 1411, and then the first electrode portion 1411 is led out through the second electrode portion 1412. Moreover, the LTPS TFT 140 further includes a source-drain lead 1461, the source-drain lead 1461 is disposed on the side of the planarization layer facing away from the substrate 130, and the source-drain lead 1461 is insulated from the second source-drain 1462. In addition, the planarization layer 145 further has a second via hole GK2 penetrating through the planarization layer 145, the second via hole GK2 exposes a partial area of the second electrode portion 1412, and the source-drain lead 1461 is connected to the second electrode portion 1412 through the second via hole GK2 to lead out the first ohmic contact region 1421 through the first source-drain 141 and the source-drain lead 1461.

[0112] Referring to Figure 10 , the gate insulating layer 143 also covers the second electrode portion 1412, and the second via hole GK2 also penetrates through the gate insulating layer 143.

[0113] Continuing to refer to Figure 10, it is possible to make the orthographic projection of the first ohmic contact region 1421 on the substrate 130, the orthographic projection of the channel region 1423 on the substrate 130, and the orthographic projection of the second ohmic contact region 1422 on the substrate 130 coincide. Then, the first ohmic contact region 1421, the channel region 1423, and the second ohmic contact region 1422 are stacked along the vertical direction F0, so that the low-temperature polycrystalline silicon active layer 142 can have three parts arranged along the vertical direction F0, enabling carriers to be transmitted in the channel region 1423 along the vertical direction F0 as much as possible. In specific applications, the low-temperature polycrystalline silicon active layer 142 can be a planar structure or a columnar structure, which is not limited herein. Additionally, the shape of the orthographic projection of the low-temperature polycrystalline silicon active layer 142 on the substrate 130 can be strip-shaped, circular, rectangular, or polygonal, etc., which is not limited herein. It is worth mentioning that due to process conditions or other factors, in actual processes, there may be some deviations or errors, resulting in the "coincidence" described above may not be completely accurate. For example, the "coincidence" described above can be the coincidence allowed within the error tolerance range. Of course, the "coincidence" can also be understood as "substantially coincident" or "completely coincident". Therefore, as long as the "coincidence" relationship described above generally meets the above conditions, it falls within the protection scope of this application. And, the material of the channel region 1423 is an intrinsically doped low-temperature polycrystalline silicon material. And, the material of the first ohmic contact region 1421 is a heavily doped low-temperature polycrystalline silicon material to improve the ohmic contact. And, the material of the second ohmic contact region 1422 is a heavily doped low-temperature polycrystalline silicon material to improve the ohmic contact. With this setting, the low-temperature polycrystalline silicon active layer 142 can have a three-layer polycrystalline silicon stack arranged along the vertical direction F0.

[0114] Continuing to refer to Figure 10 , a buffer layer 147 is further provided between the first source / drain 141 and the substrate 130 to improve the adhesion of the first source / drain 141. Further, in order to further achieve light shielding, a light-shielding layer can be provided between the buffer layer and the substrate, and the orthographic projection of the light-shielding layer on the substrate covers the orthographic projection of the low-temperature polycrystalline silicon active layer on the substrate.

[0115] To prepare Figure 10 Taking the structure of the display panel shown as an example, the manufacturing method provided by the embodiments of the present application may include the following content:

[0116] Referring to Figure 11a , Figure 11aThis is a schematic cross-sectional structure diagram of the display panel in the preparation process of the embodiments of the present application. Exemplarily, a simple glass substrate or a flexible substrate formed by coating polyimide (PI) on the glass is used as the substrate 130 of the display panel, and a buffer layer 147 is deposited on the substrate 130. For example, a stacked structure of a SiNx layer and a SiO2 layer is deposited on the substrate 130 as the buffer layer 147 by using a deposition process such as plasma enhanced chemical vapor deposition (PECVD). Among them, the thickness of the buffer layer in the vertical direction F0 is approximately 500 nm to 5500 nm. For example, the thickness of the buffer layer in the vertical direction F0 is 500 nm, 700 nm, 1000 nm, 1500 nm, 2000 nm, 2500 nm, 3000 nm, 3500 nm, 4000 nm, 4500 nm, 5000 nm, 5500 nm, etc. Of course, the thickness of the buffer layer in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0117] Refer to Figure 11b , Figure 11b This is another schematic cross-sectional structure diagram of the display panel in the preparation process of the embodiments of the present application. Exemplarily, a first source-drain electrode 141 is formed on the substrate 130. For example, ITO or AZO is sputtered on the buffer layer by using a sputter process to form a first source-drain electrode 141 layer. Then, a patterning process is used to pattern the first source-drain electrode 141 layer to form the first source-drain electrode 141. Among them, the thickness of the first source-drain electrode 141 in the vertical direction F0 is approximately 200 nm to 300 nm. For example, the thickness of the first source-drain electrode 141 in the vertical direction F0 is 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, etc. Of course, the thickness of the first source-drain electrode 141 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0118] Refer to Figure 11c , Figure 11cAnother cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, using the ELA process, a first polysilicon layer 151 is formed on the side of the first source-drain 141 facing away from the substrate 130, and the first polysilicon layer is heavily doped to form a first ohmic contact region 1421. For example, using a deposition process such as PECVD, a first amorphous silicon layer is deposited on the side of the first source-drain 141 facing away from the substrate 130. Then, using the excimer laser annealing process (ELA), the first amorphous silicon layer is crystallized into the first polysilicon layer 151. After that, using the ion implantation process, heavy doping is performed in the crystallized first polysilicon layer 151, and the doping ions can be B ions to form the first ohmic contact region 1421. Alternatively, using a deposition process such as PECVD, a first amorphous silicon layer is deposited on the side of the first source-drain 141 facing away from the substrate 130, and during the deposition of the first amorphous silicon layer, the first amorphous silicon layer is heavily doped, and the doping ions can be B ions. Then, using the ELA process, the first amorphous silicon layer is crystallized into the first polysilicon layer 151, and the heavily doped region forms the first ohmic contact region 1421. In addition, the first ohmic contact region 1421 is formed as a conductor and can form a good ohmic contact with the first source-drain 141. And the thickness of the first amorphous silicon layer in the vertical direction F0 is approximately 50 nm to 100 nm. For example, the thickness of the first amorphous silicon layer in the vertical direction F0 is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc. Of course, the thickness of the first amorphous silicon layer in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0119] Referring to Figure 11d , Figure 11dAnother cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, using the ELA process, a second polysilicon layer 152 is formed on the side of the first polysilicon layer facing away from the substrate 130, and the second polysilicon layer 152 is intrinsically doped to form a channel region 1423. For example, using a deposition process such as PECVD, a second amorphous silicon layer is deposited on the side of the first polysilicon layer 151 facing away from the substrate 130. Then, using the ELA process, the second amorphous silicon layer is crystallized into the second polysilicon layer 152. After that, using an ion implantation process, intrinsic doping is performed in the crystallized second polysilicon layer 152 to form a channel region 1423. Alternatively, using a deposition process such as PECVD, a second amorphous silicon layer is deposited on the side of the first polysilicon layer 151 facing away from the substrate 130, and during the deposition of the second amorphous silicon layer, the second amorphous silicon layer is intrinsically doped. Then, using the ELA process, the second amorphous silicon layer is crystallized into the second polysilicon layer 152. Additionally, the thickness of the second amorphous silicon layer in the vertical direction F0 is approximately 100 nm to 200 nm. For example, the thickness of the second amorphous silicon layer in the vertical direction F0 is 100 nm, 120 nm, 150 nm, 180 nm, 190 nm, 200 nm, etc. Of course, the thickness of the second amorphous silicon layer in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0120] Referring to Figure 11e , Figure 11eAnother cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, using the ELA process, a third polysilicon layer 153 is formed on the side of the second polysilicon layer 152 facing away from the substrate 130, and the third polysilicon layer 153 is heavily doped to form the second ohmic contact region 1422. For example, using a deposition process such as PECVD, a third amorphous silicon layer is deposited on the side of the second polysilicon layer 152 facing away from the substrate 130. Then, using the ELA process, the third amorphous silicon layer is crystallized into the third polysilicon layer 153. Then, using an ion implantation process, heavy doping is performed in the crystallized third polysilicon layer 153, and the doping ions can be B ions to form the second ohmic contact region 1422. Alternatively, using a deposition process such as PECVD, a third amorphous silicon layer is deposited on the side of the second polysilicon layer 152 facing away from the substrate 130, and during the deposition of the third amorphous silicon layer, heavy doping is performed in the third amorphous silicon layer, and the doping ions can be B ions. Then, using the ELA process, the third amorphous silicon layer is crystallized into the third polysilicon layer 153, and the heavily doped region forms the second ohmic contact region 1422. In addition, the second ohmic contact region 1422 is formed as a conductor and can form a good ohmic contact with the second source / drain 1462. And the first polysilicon layer 151, the second polysilicon layer 152, and the third polysilicon layer 153 are formed as a low-temperature polysilicon material layer 150. And the thickness of the third amorphous silicon layer in the vertical direction F0 is approximately 50 nm to 100 nm. For example, the thickness of the third amorphous silicon layer in the vertical direction F0 is 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc. Of course, the thickness of the third amorphous silicon layer in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0121] Refer to Figure 11f , Figure 11f Another cross-sectional structure diagram during the preparation of the display panel in the embodiment of the present application. Exemplarily, using a patterning process, the low-temperature polysilicon material layer 150 is patterned to form a low-temperature polysilicon active layer 142 having a channel region 1423, a first ohmic contact region 1421, and a second ohmic contact region 1422. For example, using a photolithography process (such as exposure and development) and an etching process, the low-temperature polysilicon material layer 150 is patterned to form the low-temperature polysilicon active layer 142.

[0122] Refer to Figure 11g And Figure 11h , Figure 11g And Figure 11hAnother cross-sectional structural schematic diagram of the display panel in the embodiment of the present application during the manufacturing process. Exemplarily, a gate insulating layer 143 and a gate 144 are sequentially deposited on the side of the low-temperature polysilicon active layer 142 facing away from the substrate 130, so that the gate 144 surrounds the sidewall of the low-temperature polysilicon active layer 142, and an opening GK0 penetrating the gate 144 is formed on the second surface of the low-temperature polysilicon active layer 142. For example, referring to Figure 11g , a gate insulating layer 143 is deposited on the side of the low-temperature polysilicon active layer 142 facing away from the substrate 130 by using a deposition process such as PECVD. After that, a metal material (such as Mo) is deposited on the side of the gate insulating layer 143 facing away from the substrate 130 by using a deposition process such as PECVD to form a gate material layer 160. After that, referring to Figure 11h , a patterning process is used to pattern the gate material layer 160 to form a gate 144 covering the active layer, and gate lines GAa to GAc are also formed. For example, a photolithography process (such as exposure and development) and an etching process are used to pattern the gate material layer 160 to form the gate 144 and the gate lines GAa to GAc. In addition, the thickness of the above-mentioned gate insulating layer 143 in the vertical direction F0 is approximately 100 nm to 150 nm. For example, the thickness of the gate insulating layer 143 in the vertical direction F0 is 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc. Of course, the thickness of the gate insulating layer 143 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein. And, the thickness of the gate material layer 160 in the vertical direction F0 is approximately 200 nm to 250 nm. For example, the thickness of the gate material layer 160 in the vertical direction F0 is 200 nm, 210 nm, 220 nm, 230 nm, 240 nm, 250 nm, etc. Of course, the thickness of the gate material layer 160 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein.

[0123] Referring to Figure 11i , Figure 11iAnother cross-sectional structure schematic diagram of the display panel in the embodiment of the present application during the manufacturing process. Exemplarily, a planarization layer 145 is formed on the side of the gate 144 facing away from the substrate 130, and a second via hole GK2 and a first via hole GK1 are formed through the planarization layer 145 and the gate insulating layer 143, and the first via hole GK1 also penetrates through the opening GK0. For example, by using a deposition process such as PECVD, the planarization layer 145 is deposited on the side of the gate 144 facing away from the substrate 130, or by coating with an organic planarization layer 145, the planarization layer 145 is formed on the side of the gate 144 facing away from the substrate 130. After that, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the planarization layer 145 and the gate insulating layer 143 to form the second via hole GK2 and the first via hole GK1. In addition, the thickness of the planarization layer 145 in the vertical direction F0 is approximately 500 nm to 600 nm. For example, the thickness of the planarization layer 145 in the vertical direction F0 is 500 nm, 520 nm, 540 nm, 560 nm, 580 nm, 600 nm, etc. Of course, the thickness of the planarization layer 145 in the vertical direction F0 can also be determined according to the requirements of the actual application scenario, which is not limited here.

[0124] Refer to Figure 11j , Figure 11jAnother cross-sectional structure diagram of the display panel in the embodiment of the present application during the manufacturing process. Exemplarily, a conductive layer is deposited on the side of the planarization layer 145 facing away from the substrate 130. The conductive layer includes a source / drain lead-out line 1461 and a second source / drain electrode 1462. The source / drain lead-out line 1461 is connected to the first source / drain electrode 141 through a second via GK2, and the second source / drain electrode 1462 is connected to the second ohmic contact region 1422 through a first via GK1. Moreover, the thickness of the conductive layer in the vertical direction F0 is approximately 700 nm to 800 nm. For example, the thickness of the conductive layer in the vertical direction F0 is 700 nm, 720 nm, 750 nm, 780 nm, 800 nm, etc. Of course, the thickness of the conductive layer in the vertical direction F0 can also be determined according to the requirements of the actual application scenario and is not limited herein. In specific implementation, a first Ti layer (the thickness of the first Ti layer in the vertical direction F0 can be approximately 50 nm) is deposited on the side of the planarization layer 145 facing away from the substrate 130 by using a deposition process such as PECVD. Then, an Al layer (the thickness of the Al layer in the vertical direction F0 can be approximately 650 nm) is deposited on the side of the first Ti layer facing away from the substrate 130 by using a deposition process such as PECVD. Then, a second Ti layer (the thickness of the second Ti layer in the vertical direction F0 can be approximately 50 nm) is deposited on the side of the Al layer facing away from the substrate 130 by using a deposition process such as PECVD. Then, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the first Ti layer, the Al layer, and the second Ti layer to form the source / drain lead-out line 1461 and the second source / drain electrode 1462.

[0125] Figure 12 Another cross-sectional structure diagram of the display panel in the embodiment of the present application, referring to Figure 12 , the display panel in the embodiment of the present application is deformed with respect to the implementation manner of the display panel in the embodiment shown in Figure 10 . Only the differences between this embodiment and the above embodiment are described below, and the same parts are not elaborated herein. This embodiment and Figure 10The difference in the illustrated embodiment is that there is a gap between the second source / drain 1462 and the gate insulating layer 143 at the sidewall of the first via GK1, and the region between the second source / drain 1462 and the gate insulating layer 143 at the sidewall of the first via GK1 is filled with an insulating layer 147. Exemplarily, the orthographic projection of the gate insulating layer 143 on the substrate 130 covers the region of the low-temperature polysilicon active layer 142 on the substrate 130 except for the orthographic projection of the opening GK0 on the substrate 130, that is, the gate insulating layer 143 extends to the sidewall of the opening GK0 on the second surface S2 to form a gate insulating layer via GK3. Also, the region between the second source / drain 1462 and the gate 144 at the sidewall of the opening GK0 is filled with the insulating layer 147, and the region between the second source / drain 1462 and the gate insulating layer 143 extending to the sidewall of the opening GK0 is also filled with the insulating layer 147. With this arrangement, the orthographic projection of the opening GK0 on the substrate 130 can coincide with the orthographic projection of the gate insulating layer via GK3 on the substrate 130, making the size of the opening GK0 the same as the size of the gate insulating layer via GK3, reducing the design difficulty of the opening GK0. Alternatively, the size of the gate insulating layer via GK3 can be made smaller than the size of the opening GK0, then the orthographic projection of the gate insulating layer via GK3 on the substrate 130 is inside the orthographic projection of the opening GK0 on the substrate 130. Also, the orthographic projection of the gate insulating layer via GK3 on the substrate 130 covers the orthographic projection of the first via GK1 on the substrate 130. For example, the size of the first via GK1 can be made smaller than the size of the gate insulating layer via GK3, then the orthographic projection of the first via GK1 on the substrate 130 is inside the orthographic projection of the gate insulating layer via GK3 on the substrate 130. Additionally, the insulating layer 147 can also be a planarization layer 145.

[0126] To prepare Figure 12 Taking the structure of the display panel shown as an example, the manufacturing method provided by the embodiments of the present application not only includes Figures 11a to 11h the manufacturing process shown, but also includes the following:

[0127] Referring to Figure 13a , Figure 13a FIG. is another cross-sectional structural schematic diagram of the display panel in the manufacturing process of the embodiments of the present application. Exemplarily, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the gate insulating layer 143 to form a gate insulating layer via GK3 penetrating the gate insulating layer 143.

[0128] Referring to Figure 13b , Figure 13bAnother cross-sectional structure schematic diagram during the preparation process of the display panel in the embodiment of the present application. Exemplarily, a deposition process such as PECVD is used to deposit a planarization layer 145 on the side of the gate 144 facing away from the substrate 130, or an organic planarization layer 145 is coated to form a planarization layer 145 on the side of the gate 144 facing away from the substrate 130. Then, a patterning process (such as a lithography process (exposure, development, etc.) and an etching process) is used to pattern the planarization layer 145 and the gate insulating layer 143, forming a second via GK2 penetrating through the planarization layer 145 and the gate insulating layer 143, and forming a first via GK1 penetrating through the planarization layer 145, the opening GK0, and the gate insulating layer via GK3.

[0129] For the subsequent preparation process, refer to Figure 11j , which will not be elaborated here.

[0130] Figure 14 Another cross-sectional structure schematic diagram of the display panel in the embodiment of the present application. Refer to Figure 14 , the display panel in the embodiment of the present application is deformed based on the implementation manner of the display panel in the embodiment shown in Figure 10 . Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be elaborated here. The difference between this embodiment and the embodiment shown in Figure 10 is that: it is also possible to make the positive projection of the second ohmic contact region 1422 on the substrate 130 partially overlap with the positive projection of the channel region 1423 on the substrate 130, then the second ohmic contact region 1422 is embedded in the channel region 1423 along the vertical direction F0, that is, a partial region on the upper surface of the low-temperature polycrystalline silicon active layer 142 facing away from the substrate 130 is the second ohmic contact region 1422, and the remaining region is the channel region 1423. With this setting, the area of the channel region 1423 wrapped by the gate 144 can be increased, and the conduction and cut-off of the channel region 1423 can be further better controlled. Exemplarily, the positive projection of the channel region 1423 on the substrate 130 covers the positive projection of the second ohmic contact region 1422 on the substrate 130. Further, the positive projection of the second ohmic contact region 1422 on the substrate 130 covers the positive projection of the first via GK1 on the substrate 130 to achieve better ohmic contact. Further, the positive projection of the second ohmic contact region 1422 on the substrate 130 is within the positive projection of the opening GK0 on the substrate 130, or the positive projection of the second ohmic contact region 1422 on the substrate 130 covers the positive projection of the opening GK0 on the substrate 130. Additionally, when preparing the structure of the display panel shown in Figure 14 , a partial region of the third polysilicon layer can be heavily doped to form the second ohmic contact region 1422, and the remaining preparation process can refer to the preparation process shown in Figures 11a to 11j .

[0131] Figure 15Another cross-sectional structure schematic diagram of the display panel in the embodiment of the present application. Refer to Figure 15 , the display panel in the embodiment of the present application is deformed based on the implementation manner of the display panel in the embodiment shown in Figure 14 . Only the differences between this embodiment and the above embodiment will be described below, and the same parts will not be elaborated here. The differences between this embodiment and Figure 14 are as follows: It is also possible to make the orthographic projection of the first ohmic contact region 1421 on the substrate 130 overlap partially with the orthographic projection of the channel region 1423 on the substrate 130. Then, the first ohmic contact region 1421 is embedded in the channel region 1423 along the vertical direction F0. That is, a partial area of the lower surface of the low-temperature polycrystalline silicon active layer 142 facing the substrate 130 is the first ohmic contact region 1421, and the remaining area is the channel region 1423. With this setting, the area of the channel region 1423 wrapped by the gate 144 can be increased, and the conduction and cutoff of the channel region 1423 can be controlled better. Exemplarily, the orthographic projection of the channel region 1423 on the substrate 130 covers the orthographic projection of the first ohmic contact region 1421 on the substrate 130. In addition, when preparing Figure 15 , the structure of the display panel shown, a partial area of the first polysilicon layer can be heavily doped to form the first ohmic contact region 1421, and the remaining preparation process can refer to Figures 11a to 11j .

[0132] It is worth mentioning that, without conflict, the features in the above embodiments and the embodiments can be combined with each other, which will not be elaborated here. Moreover, the above content is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application.

Claims

1. A display panel, characterized in that, Comprising: A substrate and a low-temperature polysilicon thin-film transistor disposed on the substrate, the low-temperature polysilicon thin-film transistor comprising: a first source-drain, a low-temperature polysilicon active layer, a gate insulating layer, a gate, a planarization layer, and a second source-drain; The first source-drain is disposed on the substrate; The low-temperature polysilicon active layer is at least partially disposed on the first source-drain, the low-temperature polysilicon active layer has a first surface facing the substrate and a second surface facing away from the substrate, and the first source-drain is at least partially connected to the first surface; The gate at least partially surrounds the sidewall of the low-temperature polysilicon active layer, and the gate is at least partially disposed on the second surface; The gate insulating layer is disposed between the gate and the low-temperature polysilicon active layer; The planarization layer is at least partially disposed on the gate, and the low-temperature polysilicon thin-film transistor further comprises a first via hole, the first via hole passes through the gate, the gate insulating layer, and the planarization layer, and the first via hole is used to expose a partial region of the second surface; The second source-drain is at least partially disposed on the planarization layer, the second source-drain is at least partially disposed in the first via hole, and the second source-drain is at least partially connected to the second surface, and the second source-drain is insulated from the gate.

2. The display panel according to claim 1, wherein The low-temperature polysilicon active layer includes a channel region, a first ohmic contact region disposed on a side of the channel region facing the substrate, and a second ohmic contact region disposed on a side of the channel region facing away from the substrate; The first surface includes the surface of the first ohmic contact region facing the substrate; The second surface includes the surface of the second ohmic contact region facing away from the substrate.

3. The display panel according to claim 2, wherein The orthographic projection of the first ohmic contact region on the substrate at least partially overlaps with the orthographic projection of the channel region on the substrate; Or, The orthographic projection of the second ohmic contact region on the substrate at least partially overlaps with the orthographic projection of the channel region on the substrate.

4. The display panel according to claim 3, wherein, The orthographic projection of the first ohmic contact region on the substrate, the orthographic projection of the channel region on the substrate, and the orthographic projection of the second ohmic contact region on the substrate coincide.

5. The display panel according to any one of claims 2-4, characterized in that, The orthographic projection of the second ohmic contact region on the substrate covers the orthographic projection of the first via hole on the substrate.

6. The display panel according to any one of claims 1-5, characterized in that, The gate on the second surface has an opening, and the orthographic projection of the gate on the substrate covers the region of the orthographic projection of the low-temperature polysilicon active layer on the substrate except for the orthographic projection of the opening on the substrate; The orthographic projection of the first via hole on the substrate is located within the orthographic projection of the opening on the substrate, the distance between the outer boundary of the orthographic projection of the first via hole on the substrate and the outer boundary of the orthographic projection of the opening on the substrate is greater than 0, and the region between the second source-drain and the gate at the sidewall of the opening is filled with an insulating layer.

7. The display panel according to claim 6, wherein The second source-drain is in direct contact with the gate insulating layer at the sidewall of the first via hole; or, There is a gap between the second source-drain and the gate insulating layer at the sidewall of the first via hole, and the region between the second source-drain and the gate insulating layer at the sidewall of the first via hole is filled with the insulating layer.

8. The display panel according to claim 7, wherein The insulating layer includes the planarization layer.

9. The display panel according to any one of claims 1-8, characterized in that, The first source-drain electrode has a first electrode portion and a second electrode portion connected thereto. The positive projection of the low-temperature polycrystalline silicon active layer on the substrate covers the positive projection of the first electrode portion on the substrate, and the positive projection of the low-temperature polycrystalline silicon active layer on the substrate does not overlap with the positive projection of the second electrode portion on the substrate. It further includes a source-drain lead-out line. The source-drain lead-out line is disposed on a side of the planarization layer facing away from the substrate. The source-drain lead-out line is insulated from the second source-drain electrode. The planarization layer has a through second via hole, the second via hole exposes the second electrode portion, and the source-drain lead-out line is connected to the second electrode portion through the second via hole.

10. The display panel according to any one of claims 1-9, characterized in that, At least one of the first source-drain electrode and the second source-drain electrode includes: a transparent conductive oxide material layer with a single-layer or multi-layer structure, or a metal material layer with a single-layer or multi-layer structure; or The positive projection of the first source-drain electrode on the substrate covers the positive projection of the low-temperature polycrystalline silicon active layer on the substrate.

11. The display panel according to any one of claims 1-10, characterized in that, The display panel includes a display area, and the display area includes a plurality of sub-pixels. At least one of the plurality of sub-pixels includes: an organic light-emitting diode and a pixel circuit connected to the organic light-emitting diode; the pixel circuit includes one or more of the low-temperature polycrystalline silicon thin-film transistors; or At least one of the plurality of sub-pixels includes: a pixel electrode and one or more of the low-temperature polycrystalline silicon thin-film transistors connected to the pixel electrode.

12. The display panel according to claim 11, wherein The display panel further includes a non-display area, and the non-display area includes a gate driving circuit. The gate driving circuit includes a plurality of cascaded shift register units, and each shift register unit includes one or more of the low-temperature polycrystalline silicon thin-film transistors.

13. An electronic device, characterized in that, It includes the display panel according to any one of claims 1-12.

14. A method for manufacturing a display panel, characterized in that, It includes: Form a first source-drain electrode on the substrate; Using an excimer laser annealing process, form a low-temperature polycrystalline silicon material layer on a side of the first source-drain electrode facing away from the substrate; Using a patterning process, pattern the low-temperature polycrystalline silicon material layer to form a low-temperature polycrystalline silicon active layer. The low-temperature polycrystalline silicon active layer has a first surface facing the substrate and a second surface facing away from the substrate, and the first surface is connected to the first source-drain electrode; Deposit a gate insulating layer and a gate on a side of the low-temperature polycrystalline silicon active layer facing away from the substrate, so that the gate at least partially surrounds the sidewall of the low-temperature polycrystalline silicon active layer, and the gate also extends along the sidewall of the low-temperature polycrystalline silicon active layer to the second surface, and the gate encloses an opening on the second surface. The gate insulating layer is disposed between the gate and the low-temperature polycrystalline silicon active layer; Form a planarization layer on a side of the gate facing away from the substrate, and form a first via hole penetrating the planarization layer. The first via hole also passes through the opening; Form a second source-drain electrode on a side of the planarization layer facing away from the substrate, and connect the second source-drain electrode to the second surface through the first via hole, and the second source-drain electrode is insulated from the gate.

15. The preparation method according to claim 14, characterized in that, Adopting an excimer laser annealing process to form a low-temperature polysilicon material layer on the side of the first source-drain facing away from the substrate, includes: Adopting the excimer laser annealing process to form a first polysilicon layer on the side of the first source-drain facing away from the substrate, and heavily doping at least a part of the first polysilicon layer to form the first ohmic contact region; Adopting the excimer laser annealing process to form a second polysilicon layer on the side of the first polysilicon layer facing away from the substrate, and intrinsically doping the second polysilicon layer to form the channel region; Adopting the excimer laser annealing process to form a third polysilicon layer on the side of the second polysilicon layer facing away from the substrate, and heavily doping at least a part of the third polysilicon layer to form the second ohmic contact region.

16. The preparation method according to claim 15, wherein, The step of adopting the excimer laser annealing process to form a first polysilicon layer on the side of the first source-drain facing away from the substrate, and heavily doping at least a part of the first polysilicon layer to form the first ohmic contact region, includes: Adopting a deposition process to deposit a first amorphous silicon layer on the side of the first source-drain facing away from the substrate; Adopting the excimer laser annealing process to crystallize the first amorphous silicon layer into a first polysilicon layer; Adopting an ion implantation process to heavily dope at least a part of the crystallized first polysilicon layer to form the first ohmic contact region; or, The step of adopting the excimer laser annealing process to form a first polysilicon layer on the side of the first source-drain facing away from the substrate, and heavily doping at least a part of the first polysilicon layer to form the first ohmic contact region, includes: Adopting a deposition process to deposit a first amorphous silicon layer on the side of the first source-drain facing away from the substrate, and during the deposition of the first amorphous silicon layer, heavily doping at least a part of the first amorphous silicon layer; Adopting the excimer laser annealing process to crystallize the first amorphous silicon layer into a first polysilicon layer, and the heavily doped region forms the first ohmic contact region.

17. The preparation method according to claim 15 or 16, characterized in that, The step of adopting the excimer laser annealing process to form a second polysilicon layer on the side of the first polysilicon layer facing away from the substrate, and intrinsically doping the second polysilicon layer to form the channel region, includes: Adopting a deposition process to deposit a second amorphous silicon layer on the side of the first polysilicon layer facing away from the substrate; Adopting the excimer laser annealing process to crystallize the second amorphous silicon layer into a second polysilicon layer; Adopting an ion implantation process to intrinsically dope the crystallized second polysilicon layer to form the channel region; or, The step of adopting the excimer laser annealing process to form a second polysilicon layer on the side of the first polysilicon layer facing away from the substrate, and intrinsically doping the second polysilicon layer to form the channel region, includes: Adopting a deposition process to deposit a second amorphous silicon layer on the side of the first polysilicon layer facing away from the substrate, and during the deposition of the second amorphous silicon layer, intrinsically doping the second amorphous silicon layer; Using the excimer laser annealing process, the second amorphous silicon layer is crystallized into a second polycrystalline silicon layer.

18. The preparation method according to any one of claims 15-17, characterized in that, Using the excimer laser annealing process, a third polycrystalline silicon layer is formed on the side of the second polycrystalline silicon layer facing away from the substrate, and at least a part of the third polycrystalline silicon layer is heavily doped to form the second ohmic contact region, including: Using a deposition process, a third amorphous silicon layer is deposited on the side of the second polycrystalline silicon layer facing away from the substrate; Using the excimer laser annealing process, the third amorphous silicon layer is crystallized into a third polycrystalline silicon layer; Using an ion implantation process, at least a part of the crystallized third polycrystalline silicon layer is heavily doped to form the second ohmic contact region; or, Using the excimer laser annealing process, a third polycrystalline silicon layer is formed on the side of the second polycrystalline silicon layer facing away from the substrate, and at least a part of the third polycrystalline silicon layer is heavily doped to form the second ohmic contact region, including: Using a deposition process, a third amorphous silicon layer is deposited on the side of the second polycrystalline silicon layer facing away from the substrate, and during the deposition of the third amorphous silicon layer, at least a part of the third amorphous silicon layer is heavily doped; Using the excimer laser annealing process, the third amorphous silicon layer is crystallized into a third polycrystalline silicon layer, and the heavily doped region forms the second ohmic contact region.

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