Preparation method of image sensor
By using the patterned photoresist layer as a mask during the image sensor preparation process, the dielectric layer is gradually removed and low-temperature silicon ion implantation is carried out, and the problem of pixel region deterioration caused by amorphous silicon implantation is solved, and the device yield and electrical performance are improved.
Patent Information
- Application Number
- CN202510326087.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2025-07-08
AI Technical Summary
In the image sensor preparation process, the amorphous silicon injection process on the surface of the logic region device causes abnormal deterioration of white pixels in the pixel region, affecting the device yield and electrical performance.
After forming the first and second dielectric layers, a photoresist layer is coated on the second dielectric layer, and the patterned photoresist layer is used as a mask to gradually remove the dielectric layer in the PMOS and NMOS device regions and perform silicon ion implantation to avoid misetching of the pixel regions and lattice defects, and low-temperature silicon ion implantation technology is used.
It effectively avoids the risk of misetching and impurities in the pixel area, ensures the device morphology and lattice integrity, improves electrical performance and improves device yield.
Smart Images
Figure CN120282557A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor manufacturing technology, and specifically relates to a method for manufacturing an image sensor. Background Art
[0002] In the logic process of the manufacturing process of an image sensor (CIS) at the 40nm node, in order to ensure power consumption, it is desired to reduce the resistance of the S / D (source / drain region) and the LDD (lightly doped drain region). Currently, in order to reduce the resistance of the S / D (source / drain region) and the LDD (lightly doped drain region), before depositing the metal silicide layer, a layer of amorphous silicon is usually implanted on the surface of the logic region devices through an ion implantation process. The amorphous form has stronger activity and can react better with the metal, so it can effectively reduce the metal resistance in the logic region, thereby reducing power consumption.
[0003] However, currently in the platform of the image sensor at the 45nm / 40nm node, in the manufacturing process of the image sensor at the 40nm node, when a layer of amorphous silicon implantation process is added to the surface of the logic region devices, it is found that the white pixels (WhitePixel) in the pixel region deteriorate abnormally, thereby affecting the yield and electrical performance of the device. Summary of the Invention
[0004] This application provides a method for manufacturing an image sensor, which can solve the problem that in the traditional manufacturing process of an image sensor, the amorphous silicon implantation process on the surface of the logic region devices will cause abnormal deterioration of the white pixels in the pixel region, thereby affecting the yield and electrical performance of the device.
[0005] An embodiment of this application provides a method for manufacturing an image sensor, including:
[0006] Providing a substrate, the substrate includes a pixel region and a logic region. A first gate structure is formed on the substrate of the pixel region. The logic region at least includes: a PMOS device region and an NMOS device region. A second gate structure is formed on the substrate of the PMOS device region, and a third gate structure is formed on the substrate of the NMOS device region. A first dielectric layer covering the first to third gate structures and a second dielectric layer covering the first dielectric layer are further formed on the substrate;
[0007] Coating a photoresist layer on the second dielectric layer;
[0008] Through a photolithography process, opening the photoresist layer in the PMOS device region and the NMOS device region to obtain a patterned photoresist layer;
[0009] Using the patterned photoresist layer as a mask, removing the second dielectric layer in the PMOS device region and the NMOS device region;
[0010] Using the patterned photoresist layer as a mask, remove the first dielectric layer in the PMOS device region and the NMOS device region;
[0011] Using the patterned photoresist layer as a mask, perform silicon ion implantation on the PMOS device region and the NMOS device region to form amorphous silicon layers on the surfaces of the source / drain regions and the second gate structure in the PMOS device region and on the surfaces of the source / drain regions and the third gate structure in the NMOS device region;
[0012] Remove the patterned photoresist layer;
[0013] Form a metal silicide layer that covers the source / drain regions and the second gate structure in the PMOS device region and the source / drain regions and the third gate structure in the NMOS device region.
[0014] Optionally, in the method for manufacturing the image sensor, using the patterned photoresist layer as a mask, perform low-temperature silicon ion implantation on the PMOS device region and the NMOS device region, where the process temperature of the ion implantation is 0°C to 100°C; the ion implantation energy is 1 keV to 20 keV; the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .
[0015] Optionally, in the method for manufacturing the image sensor, the thickness of the amorphous silicon layer is 50 Å to 80 Å.
[0016] Optionally, in the method for manufacturing the image sensor, the material of the second dielectric layer is silicon nitride.
[0017] Optionally, in the method for manufacturing the image sensor, use a dry etching process to remove the second dielectric layer in the PMOS device region and the NMOS device region.
[0018] Optionally, in the method for manufacturing the image sensor, the material of the first dielectric layer is silicon dioxide.
[0019] Optionally, in the method for manufacturing the image sensor, use a wet etching process to remove the first dielectric layer in the PMOS device region and the NMOS device region.
[0020] Optionally, in the method for manufacturing the image sensor, during the process of using a wet etching process to remove the first dielectric layer in the PMOS device region and the NMOS device region, the solution used at least includes: hydrofluoric acid.
[0021] Optionally, in the method for manufacturing the image sensor, the step of removing the patterned photoresist layer includes:
[0022] The patterned photoresist layer is removed by a dry etching process;
[0023] The semiconductor structure after removing the patterned photoresist layer is cleaned by a wet cleaning process.
[0024] The technical solution of the present application has at least the following advantages:
[0025] In the method for manufacturing an image sensor provided in the present application, after forming the first dielectric layer and the second dielectric layer, a photoresist layer is coated on the second dielectric layer. Subsequently, the second dielectric layer and the first dielectric layer in the PMOS device region and the NMOS device region are removed and silicon ion implantation is performed in the PMOS device region and the NMOS device region by using the patterned photoresist layer as a mask all the time. After the silicon ion implantation is completed, the patterned photoresist layer is removed. By using the patterned photoresist layer, the second dielectric layer and the first dielectric layer as a triple mask structure of the pixel region, the etching of the second dielectric layer and the first dielectric layer in the logic region and the silicon ion implantation in the PMOS device region and the NMOS device region are carried out, which can avoid the situation that the second dielectric layer in the pixel region is accidentally etched in the process of removing the second dielectric layer and / or the first dielectric layer in the logic region, and can also avoid the risk of generating impurities such as NiSi in the pixel region and the situation that lattice defects are forcedly introduced into the pixel region due to silicon ion implantation, thereby deteriorating the white pixels, ensuring the integrity of the device morphology and lattice in the pixel region, improving the electrical performance of the device and increasing the device yield. Description of the Drawings
[0026] In order to more clearly illustrate the specific embodiments of the present application or the technical solutions in the prior art, the following will briefly introduce the drawings required for the description of the specific embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.
[0027] Figure 1 is a flowchart of the method for manufacturing an image sensor according to an embodiment of the present invention;
[0028] Figures 2 - 8 is a schematic diagram of the semiconductor structure in each process step of manufacturing an image sensor according to an embodiment of the present invention;
[0029] Among them, the reference numerals are explained as follows:
[0030] 100 - substrate, 110 - shallow trench isolation structure, 120 - first dielectric layer, 130 - second dielectric layer, 140 - photoresist layer, 150 - metal silicide layer;
[0031] 101 - The first gate oxide layer, 102 - The first gate, 103 - The first spacer;
[0032] 201 - The second gate oxide layer, 202 - The second gate, 203 - The second spacer, 204 - The first lightly doped drain region, 205 - The first source region, 206 - The first drain region;
[0033] 301 - The third gate oxide layer, 302 - The third gate, 303 - The third spacer, 304 - The second lightly doped drain region, 305 - The second source region, 306 - The second drain region. Detailed implementation manners
[0034] Next, the technical solutions in the present application will be clearly and completely described in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.
[0035] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present application. In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.
[0036] In the description of the present application, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "connected", "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two elements. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to specific situations.
[0037] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0038] The embodiment of the present application provides a method for manufacturing an image sensor. Refer to Figure 1 , Figure 1 is a flowchart of the method for manufacturing an image sensor according to an embodiment of the present invention. The method for manufacturing the image sensor includes:
[0039] First, perform step S1: Refer to Figure 2 , Figure 2 FIG. is a schematic diagram of a semiconductor structure after forming a second dielectric layer according to an embodiment of the present application. A substrate 100 is provided. The substrate 100 includes a pixel region and a logic region. A first gate structure is formed on the substrate 100 in the pixel region. The logic region at least includes: a PMOS device region and an NMOS device region. A second gate structure is formed on the substrate in the PMOS device region, and a third gate structure is formed on the substrate in the NMOS device region. A first dielectric layer 120 covering the first to third gate structures and a second dielectric layer 130 covering the first dielectric layer are further formed on the substrate.
[0040] Among them, the first gate structure includes: a first gate oxide layer 101 on the substrate 100 in the pixel region, a first gate 102 covering the first gate oxide layer 101, and first sidewalls 103 on both sides of the first gate 102; the second gate structure includes: a second gate oxide layer 201 on the substrate 100 in the PMOS device region, a second gate 202 covering the second gate oxide layer 201, and second sidewalls 203 on both sides of the second gate 202; the third gate structure includes: a third gate oxide layer 301 on the substrate 100 in the NMOS device region, a third gate 302 covering the third gate oxide layer 301, and third sidewalls 303 on both sides of the third gate 302.
[0041] Further, an N-type well region (not shown) is further formed in the substrate 100 in the PMOS device region. A first lightly doped drain region 204, a first source region 205, and a first drain region 206 are further formed in the N-type well region. Two first lightly doped drain regions 204 are located in the substrate 100 on both sides of the second gate structure. The first source region 205 and the first drain region 206 are respectively located in the two first lightly doped drain regions 204; a P-type well region (not shown) is further formed in the substrate 100 in the NMOS device region. A second lightly doped drain region 304, a second source region 305, and a second drain region 306 are further formed in the P-type well region. Two second lightly doped drain regions 304 are located in the substrate 100 on both sides of the third gate structure. The second source region 305 and the second drain region 306 are respectively located in the two second lightly doped drain regions 304.
[0042] In this embodiment, the material of the second dielectric layer 130 is silicon nitride.
[0043] In this embodiment, the material of the first dielectric layer 120 is silicon dioxide.
[0044] Then, perform step S2: Refer to Figure 3 , Figure 3It is a schematic diagram of a semiconductor structure after coating a photoresist layer on the second dielectric layer in an embodiment of the present application. A photoresist layer 140 is coated on the second dielectric layer 130 in the pixel region and the logic region.
[0045] Next, perform step S3: Refer to Figure 4 , Figure 4 It is a schematic diagram of a semiconductor structure after removing the second dielectric layer in the PMOS device region and the NMOS device region in an embodiment of the present application. Through a photolithography process, the photoresist layer 140 in the PMOS device region and the NMOS device region is opened to obtain a patterned photoresist layer 140.
[0046] Further, perform step S4: Continue to refer to Figure 4 , and using the patterned photoresist layer 140 as a mask, the second dielectric layer 130 in the PMOS device region and the NMOS device region is removed by a self-alignment process.
[0047] In this embodiment, a dry etching process is used to remove the second dielectric layer 130 in the PMOS device region and the NMOS device region.
[0048] Next, perform step S5: Refer to Figure 5 , Figure 5 It is a schematic diagram of a semiconductor structure after removing the first dielectric layer in the PMOS device region and the NMOS device region in an embodiment of the present application. Using the patterned photoresist layer as a mask, the first dielectric layer 120 in the PMOS device region and the NMOS device region is removed by a self-alignment process.
[0049] In this embodiment, a wet etching process is used to remove the first dielectric layer 120 in the PMOS device region and the NMOS device region.
[0050] It should be noted that during the process of using a wet etching process to remove the first dielectric layer 120 in the PMOS device region and the NMOS device region, the solution used at least includes: hydrofluoric acid to thoroughly remove impurities on the surface of the second gate structure in the PMOS device region and the surface of the third gate structure in the NMOS device region; secondly, the self-alignment process with the photoresist for wet etching the first dielectric layer 120 can keep some specially designed regions from growing metal silicides.
[0051] Further, perform step S6: Refer to Figure 6 , Figure 6It is a schematic diagram of a semiconductor structure after forming an amorphous silicon layer by ion implantation according to an embodiment of the present application. Using the patterned photoresist layer 140 as a mask, a self-aligned process is adopted to perform silicon ion implantation on the PMOS device region and the NMOS device region, so as to form an amorphous silicon layer on the surfaces of the first source region 205, the first drain region 206, and the second gate 202 in the PMOS device region, and on the surfaces of the second source region 305, the second drain region 306, and the third gate 302 in the NMOS device region.
[0052] Preferably, using the patterned photoresist layer 140 as a mask, low-temperature silicon ion implantation is performed on the PMOS device region and the NMOS device region, wherein the process temperature of the ion implantation is 0°C to 100°C; the ion implantation energy is 1 KeV to 20 KeV; the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .
[0053] Preferably, the thickness of the amorphous silicon layer is 50 Å to 80 Å.
[0054] Among them, the low-temperature silicon ion implantation using the patterned photoresist layer as a mask forms an amorphous silicon layer in the region where metal silicide will grow, which can react better with the metal, thereby reducing the contact resistance in the logic region. And the patterned photoresist layer, the second dielectric layer, and the first dielectric layer in the pixel region act as a triple mask structure in the pixel region to block silicon ions from being implanted and prevent the lattice of the pixel region film layer from being damaged, ensuring the integrity of the device morphology and lattice in the pixel region, improving the electrical performance of the device, and increasing the device yield.
[0055] Next, step S7 is executed: Refer to Figure 7 , Figure 7 It is a schematic diagram of a semiconductor structure after removing the patterned photoresist layer according to an embodiment of the present application. The patterned photoresist layer 140 is removed.
[0056] Preferably, the step of removing the patterned photoresist layer 140 may specifically include:
[0057] Step S7.1: Use a dry etching process to remove the patterned photoresist layer 140;
[0058] Step S7.2: Use a wet cleaning process to clean the semiconductor structure after removing the patterned photoresist layer 140;
[0059] Among them, through step S7.1 and step S7.2 of the present application, the patterned photoresist layer 140 can be completely removed.
[0060] Finally, step S8 is executed: Refer to Figure 8 ,Figure 8 It is a schematic diagram of a semiconductor structure after forming a metal silicide layer in an embodiment of the present application. By using a self-alignment process, a metal silicide layer 150 is formed. The metal silicide layer 150 covers the first source region 205, the first drain region 206, and the second gate 202 of the PMOS device region, and the second source region 305, the second drain region 306, and the third gate 302 of the NMOS device region.
[0061] In the present application, after forming the first dielectric layer and the second dielectric layer, a photoresist layer is coated on the second dielectric layer. Subsequently, the second dielectric layer and the first dielectric layer in the PMOS device region and the NMOS device region are removed by using the patterned photoresist layer as a mask, and silicon ion implantation is performed in the PMOS device region and the NMOS device region. After the silicon ion implantation is completed, the patterned photoresist layer is removed. By using the patterned photoresist layer, the second dielectric layer, and the first dielectric layer as a triple mask structure in the pixel region, etching of the second dielectric layer and the first dielectric layer in the logic region and silicon ion implantation in the PMOS device region and the NMOS device region are carried out, which can avoid the situation that the second dielectric layer in the pixel region is mis-etched in the process of removing the second dielectric layer and / or the first dielectric layer in the logic region, and can also avoid the risk of generating impurities such as NiSi in the pixel region and the situation that lattice defects are forcedly introduced into the pixel region due to silicon ion implantation, thereby deteriorating the white pixels. This ensures the integrity of the device morphology and lattice in the pixel region, improves the electrical performance of the device, and increases the device yield.
[0062] Obviously, the above embodiments are only examples for clear illustration and not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or variations can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or variations derived therefrom are still within the protection scope of the present invention.
Claims
1. A method for manufacturing an image sensor, characterized in that, Comprising: Providing a substrate, the substrate including a pixel region and a logic region, a first gate structure being formed on the substrate of the pixel region, the logic region at least including: a PMOS device region and an NMOS device region, a second gate structure being formed on the substrate of the PMOS device region, a third gate structure being formed on the substrate of the NMOS device region, a first dielectric layer covering the first to third gate structures and a second dielectric layer covering the first dielectric layer being further formed on the substrate; Coating a photoresist layer on the second dielectric layer; Through a photolithography process, opening the photoresist layer in the PMOS device region and the NMOS device region to obtain a patterned photoresist layer; Using the patterned photoresist layer as a mask to remove the second dielectric layer in the PMOS device region and the NMOS device region; Using the patterned photoresist layer as a mask to remove the first dielectric layer in the PMOS device region and the NMOS device region; Using the patterned photoresist layer as a mask to perform silicon ion implantation on the PMOS device region and the NMOS device region to form amorphous silicon layers on the surfaces of the source / drain regions and the second gate structure in the PMOS device region and on the surfaces of the source / drain regions and the third gate structure in the NMOS device region; Removing the patterned photoresist layer; Forming a metal silicide layer, the metal silicide layer covering the source / drain regions and the second gate structure in the PMOS device region and the source / drain regions and the third gate structure in the NMOS device region.
2. The method for manufacturing an image sensor according to claim 1, wherein Using the patterned photoresist layer as a mask, perform low-temperature silicon ion implantation on the PMOS device region and the NMOS device region, where the process temperature of the ion implantation is 0°C to 100°C; the ion implantation energy is 1 KeV to 20 KeV; the ion implantation dose is 1E13 / cm 2 ~1E15 / cm 2 .
3. The manufacturing method of the image sensor according to claim 1, characterized in that, The thickness of the amorphous silicon layer is 50 Å to 80 Å.
4. The manufacturing method of the image sensor according to claim 1, characterized in that, The material of the second dielectric layer is silicon nitride.
5. The method for manufacturing an image sensor according to claim 1 or 4, characterized in that, Using a dry etching process to remove the second dielectric layer in the PMOS device region and the NMOS device region.
6. The method for manufacturing an image sensor according to claim 1, wherein, The material of the first dielectric layer is silicon dioxide.
7. The method for manufacturing an image sensor according to claim 1 or 6, characterized in that, Using a wet etching process to remove the first dielectric layer in the PMOS device region and the NMOS device region.
8. The manufacturing method of the image sensor according to claim 7, characterized in that, During the process of using the wet etching process to remove the first dielectric layer in the PMOS device region and the NMOS device region, the solution used at least includes: hydrofluoric acid.
9. The method for manufacturing an image sensor according to claim 1, wherein, The step of removing the patterned photoresist layer includes: Using a dry etching process to remove the patterned photoresist layer; Using a wet cleaning process to clean the semiconductor structure after removing the patterned photoresist layer.