Light-emitting chip epitaxial layer, manufacturing method and light-emitting chip

Abstract

The invention relates to a light-emitting chip epitaxial layer, a manufacturing method and a light-emitting chip. The light-emitting chip epitaxial layer comprises a first semiconductor layer; the active layer is arranged on the first semiconductor layer; the second semiconductor layer is arranged on one side, far away from the first semiconductor layer, of the active layer; wherein the first semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer, and the conduction type of the second semiconductor layer is different from that of the first semiconductor layer; the N-type semiconductor layer comprises a stark effect enhancement layer and comprises low-potential-barrier sub-layers and high-potential-barrier sub-layers which are alternately stacked for multiple periods, and the higher the potential barrier height of the high-potential-barrier sub-layer closer to the active layer is; the active layer is configured to have a quantum-limited stark effect, and the quantum-limited stark effect causes emission wavelengths of the active layer at different currents to have a wavelength shift of more than 60 nanometers. The bicolor light emitting based on the epitaxial layer of the light-emitting chip can be realized only by providing different currents, so that the manufacturing of a bicolor integrated display product is simpler.

Description

Technical Field

[0001] The present application relates to the field of LEDs, in particular to an epitaxial layer of a light-emitting chip, a manufacturing method thereof, and a light-emitting chip. Background Art

[0002] With the development of display technology, existing LCDs (Liquid Crystal Displays) and OLEDs (Organic Light-Emitting Diodes) are gradually unable to meet higher performance requirements. Display products of MicroLEDs (Micro Light Emitting Diodes) are expected to be widely used in near-eye display fields such as VR (Virtual Reality) and AR (Augmented Reality). However, the dual-color MicroLED solutions mainly include fabricating MicroLEDs of different colors using materials with different components respectively, and then setting them on a display panel through a mass transfer method; or performing color conversion on monochromatic MicroLEDs. These dual-color display solutions all require one or more monochromatic MicroLED chips, and the manufacturing process of the display products is complex, and it is impossible to simply implement a dual-color integrated MicroLED chip.

[0003] Therefore, how to simply achieve dual-color integration based on a single epitaxial layer is an urgent problem to be solved. Summary of the Invention

[0004] In view of the deficiencies of the above-mentioned related technologies, the purpose of the present application is to provide an epitaxial layer of a light-emitting chip, a manufacturing method thereof, and a light-emitting chip, aiming to solve the problems that the dual-color display solutions require one or more monochromatic MicroLED chips, and the manufacturing process of the display products is complex, and it is impossible to simply implement a dual-color integrated MicroLED chip.

[0005] An epitaxial layer of a light-emitting chip includes:

[0006] A first semiconductor layer;

[0007] An active layer disposed on the first semiconductor layer; and

[0008] A second semiconductor layer disposed on a side of the active layer away from the first semiconductor layer;

[0009] Among them, the first semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer, and the second semiconductor layer has a different conductivity type from that of the first semiconductor layer; the N-type semiconductor layer includes a Stark effect enhancement layer configured to enhance the quantum-confined Stark effect of the active layer; the Stark effect enhancement layer includes a plurality of periods of low-barrier sub-layers and high-barrier sub-layers stacked alternately, and the high-barrier sub-layer closer to the active layer has a greater barrier height; the active layer is configured to have a quantum-confined Stark effect, and the quantum-confined Stark effect causes the emission wavelength of the active layer at different currents to have a wavelength shift of more than 60 nanometers.

[0010] In the above-mentioned light-emitting chip epitaxial layer, during the process of electrons passing through the Stark effect enhancement layer, they repeatedly move from a low electric potential to a high electric potential, and their kinetic energy is reduced, thereby reducing the electron overflow in the active layer, making the wave function coincidence region of electron-hole pairs larger, and ensuring the light efficiency at a larger current. It also makes the active layer more strongly affected by the quantum-confined Stark effect, so as to have a wavelength shift of more than 60 nanometers, realizing the emission of two colors of light with significantly different visual effects from a single light-emitting chip epitaxial layer. In some implementation processes, it can make the production of dual-color integrated display products simpler. On the other hand, the barrier height of the high-barrier sub-layer gradually increases in the direction close to the active layer, so that the current can have a better lateral expansion effect during the process of passing through the Stark effect enhancement layer, which further ensures the light efficiency and enables the active layer to emit light normally under a stronger quantum-confined Stark effect.

[0011] Optionally, the number of periods of the low-barrier sub-layer and the high-barrier sub-layer is in the range of 5 to 20.

[0012] More periods of low-barrier sub-layers and high-barrier sub-layers enable electrons to move from a low electric potential to a high electric potential multiple times when passing through the Stark effect enhancement layer, which can well weaken the kinetic energy of electrons.

[0013] Optionally, the N-type semiconductor layer further includes an electron aggregation layer disposed on the side of the Stark effect enhancement layer close to the active layer, and the doping concentration of the electron aggregation layer changes alternately between high and low multiple times along the growth direction.

[0014] The electron aggregation layer can converge the electrons whose kinetic energy has been weakened by the Stark effect enhancement layer here, further enhancing the hindering effect on electrons, and can further improve the quantum-confined Stark effect of the active layer in some implementation processes.

[0015] Optionally, the active layer includes alternately arranged quantum barrier layers and quantum well layers, and the number of periods of the quantum barrier layers and the quantum well layers is not less than 15.

[0016] Increasing the number of periods of the active layer will, in some implementations, result in a larger region where the wave functions of electron-hole pairs in the active layer overlap, no longer being concentrated only in the last one or two quantum well layers. Thus, at different currents, recombination positions in different energy bands can be achieved, with a stronger quantum-confined Stark effect.

[0017] Based on the same inventive concept, the present application also provides a method for fabricating a light-emitting chip epitaxial layer, including:

[0018] Providing a first semiconductor layer on a substrate;

[0019] Providing an active layer on the first semiconductor layer; and

[0020] Providing a second semiconductor layer on the active layer;

[0021] Wherein, the first semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer, and the second semiconductor layer has a different conductivity type from the first semiconductor layer; the N-type semiconductor layer includes a Stark effect enhancement layer configured to enhance the quantum-confined Stark effect of the active layer; the Stark effect enhancement layer includes a plurality of periods of low-barrier sub-layers and high-barrier sub-layers stacked alternately, and the high-barrier sub-layer closer to the active layer has a larger barrier height; the active layer is configured to have a quantum-confined Stark effect, and the quantum-confined Stark effect causes the emission wavelength of the active layer to have a wavelength shift of more than 60 nanometers at different currents.

[0022] In the above fabricated light-emitting chip epitaxial layer, electrons repeatedly move from a low electric potential to a high electric potential during the process of passing through the Stark effect enhancement layer, and their kinetic energy is reduced, thereby reducing the electron overflow in the active layer, making the overlapping region of the wave functions of electron-hole pairs larger, and ensuring the light efficiency at a larger current. It also makes the active layer more strongly affected by the quantum-confined Stark effect, thereby having a wavelength shift of more than 60 nanometers, and realizing the emission of two kinds of light with significantly different visual effects from a single light-emitting chip epitaxial layer. In some implementations, it can make the fabrication of dual-color integrated display products simpler. On the other hand, the barrier height of the high-barrier sub-layer gradually increases in the direction closer to the active layer, enabling the current to have a better lateral expansion effect during the process of passing through the Stark effect enhancement layer, which further ensures the light efficiency and enables the active layer to emit light normally under a stronger quantum-confined Stark effect.

[0023] Based on the same inventive concept, the present application also provides a light-emitting chip, including:

[0024] The above-mentioned light-emitting chip epitaxial layer;

[0025] A first electrode connected to the first semiconductor layer; and

[0026] The second electrode is connected to the second semiconductor layer.

[0027] The above light-emitting chip adopts the aforementioned light-emitting chip epitaxial layer, and its active layer has a wavelength shift of more than 60 nanometers under different currents, and can have different emission wavelengths based on different currents, and can be well applied in dual-color display products. Description of the Drawings

[0028] Figure 1 It is a schematic diagram of the basic structure of the light-emitting chip epitaxial layer provided by the embodiment of the present application;

[0029] Figure 2 It is a schematic diagram of the active layer structure of the light-emitting chip epitaxial layer provided by the embodiment of the present application;

[0030] Figure 3 It is a schematic diagram of a structure of the Stark effect enhancement layer provided by the embodiment of the present application;

[0031] Figure 4 It is a schematic diagram of the structural characteristics of the Stark effect enhancement layer and the electron aggregation layer provided by the embodiment of the present application;

[0032] Figure 5 It is another schematic diagram of the light-emitting chip epitaxial layer provided by the embodiment of the present application;

[0033] Figure 6 It is a schematic diagram of a structure of the light-emitting chip provided by the embodiment of the present application;

[0034] Figure 7 It is a schematic flow chart of the manufacturing method of the light-emitting chip epitaxial layer provided by the embodiment of the present application;

[0035] Figure 8 It is a schematic flow chart of the setting process of the Stark effect enhancement layer provided by the embodiment of the present application;

[0036] Figure 9 It is a schematic diagram of the manufacturing process of an exemplary light-emitting chip epitaxial layer provided by the embodiment of the present application;

[0037] Figure 10 It is a schematic diagram of a structure of a stress release layer provided by the embodiment of the present application;

[0038] Description of the Reference Numerals:

[0039] 1 - The first semiconductor layer; 11 - The Stark effect enhancement layer; 101 - The low-barrier sub-layer; 102 - The high-barrier sub-layer; 12 - The electron aggregation layer; 13 - The GaN buffer layer; 14 - The N-type doped GaN layer; 15 - The stress release layer; 151 - In x Ga 1-xN - layer; 152 - GaN layer; 2 - active layer; 21 - quantum barrier layer; 22 - quantum well layer; 3 - second semiconductor layer; 31 - hole - accumulation layer; 32 - P - type doped GaN layer; 33 - P - type doped ohmic contact layer; 41 - N - type electrode; 42 - P - type electrode; 5 - substrate. Detailed implementation manners

[0040] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] The dual - color display solutions in the related art need to be based on one or more monochromatic Micro LED chips, and the manufacturing process of the display product is complex, and it is impossible to simply implement a dual - color integrated Micro LED chip. Based on this, the present application hopes to provide a solution that can solve the above - mentioned technical problems, and the detailed content will be elaborated in the subsequent embodiments.

[0043] Based on this, the present application hopes to provide a solution that can solve the above - mentioned technical problems, and the detailed content will be elaborated in the subsequent embodiments.

[0044] Embodiment:

[0045] This embodiment provides a light - emitting chip epitaxial layer. Refer to Figure 1 As shown, the light - emitting chip epitaxial layer includes a first semiconductor layer 1, an active layer 2, and a second semiconductor layer 3. Among them, the first semiconductor layer 1 is an N - type semiconductor layer or a P - type semiconductor layer, and the second semiconductor layer 3 has a different conductivity type from the first semiconductor layer 1; that is, if the first semiconductor layer 1 is an N - type semiconductor layer, then the second semiconductor layer 3 is a P - type semiconductor layer, and vice versa.

[0046] In this embodiment, the active layer 2 can be a multi-quantum well active layer or a superlattice active layer. The active layer 2 includes a plurality of quantum barrier layers 21 and a plurality of quantum well layers 22 which are alternately arranged. The N-type semiconductor layer in this embodiment includes a Stark effect enhancement layer 11 which is configured to enhance the quantum-confined Stark effect of the active layer 2. Affected by the quantum-confined Stark effect, as the injection current increases, the emission wavelength of the active layer 2 will exhibit a blue shift phenomenon, that is, the emission wavelength at high current is shorter than that at low current. The Stark effect enhancement layer 11 of this embodiment enhances the influence of the quantum-confined Stark effect on the active layer 2, making the blue shift phenomenon more significant, that is, it can generate a larger wavelength shift range. In this application, the quantum-confined Stark effect enables the active layer 2 to have a wavelength shift of more than 60 nanometers at different currents.

[0047] It should be noted that in the conventional design of the epitaxial layer of a light-emitting chip, the wavelength shift range caused by the quantum-confined Stark effect is usually controlled within a few nanometers or a dozen nanometers. In some applications, the quantum-confined Stark effect is also suppressed by structural or material settings to keep the emission wavelength of the light-emitting chip stable. In actual applications, in order to avoid the drift of the emission wavelength, in some applications, pulse width modulation is also used to adjust the brightness to avoid color inconsistency at different brightness levels caused by changing the current intensity.

[0048] As Figure 2 shown, the active layer 2 includes a plurality of quantum well layers 22 and a plurality of quantum barrier layers 21 which are alternately arranged. However, in actual applications, the region where effective recombination of electrons and holes occurs is mainly concentrated in the last one or two quantum well layers 22 close to the P-type semiconductor layer. As the current increases, although the active layer 2 undergoes a certain degree of blue shift under the influence of the quantum-confined Stark effect, electrons are likely to overflow the active layer 2, forming ineffective current injection, and the optical efficiency rapidly decreases. Therefore, in some applications, the blue shift range of the active layer 2 can be limited to a few nanometers or a dozen nanometers.

[0049] Different from the above solutions, this application forms a strong quantum-confined Stark effect to utilize it to achieve a large range of wavelength shifts and realize dual-color emission based on the same epitaxial layer of a light-emitting chip. In this embodiment, through the design of the quantum-confined Stark effect of the active layer 2, the active layer 2 has a wavelength shift of more than 60 nanometers at different currents, so as to realize a single epitaxial layer of a light-emitting chip emitting two colors of light with significantly different visual effects. Therefore, only by forming different currents, dual-color emission based on the epitaxial layer of the light-emitting chip can be realized.

[0050] It can be understood that due to the strong quantum-confined Stark effect, the optical efficiency may be reduced. Refer to Figure 3, in the present application, while enhancing the quantum-confined Stark effect of the active layer 2, the Stark effect enhancement layer 11 is configured to include a plurality of periods of low-barrier sub-layers 101 and high-barrier sub-layers 102 stacked alternately, and the high-barrier sub-layer 102 closer to the active layer 2 has a higher barrier height. For the convenience of description, in this embodiment, the first semiconductor layer 1 is taken as an N-type semiconductor layer as an example, but in other examples, the N-type semiconductor layer may also be the second semiconductor layer 3. When electrons pass through the Stark effect enhancement layer 11, they repeatedly move from a low electric potential to a high electric potential, and their kinetic energy is reduced, thereby reducing the electron overflow in the active layer 2, making the overlapping region of the wave functions of electron-hole pairs larger, ensuring the optical efficiency at a larger current, and also making the active layer 2 more strongly affected by the quantum-confined Stark effect. On the other hand, the barrier height of the high-barrier sub-layer 102 gradually increases in the direction closer to the active layer 2, so that when the current passes through the Stark effect enhancement layer 11, it can have a better lateral expansion effect, which further ensures the optical efficiency and enables the active layer 2 to emit light normally under a stronger quantum-confined Stark effect. It should be noted that the low-barrier sub-layer 101 and the high-barrier sub-layer 102 in the present application are only distinguished based on the relative height of the barriers, and no specific numerical limit is imposed on their barriers, where the barrier of the low-barrier sub-layer 101 is lower than that of the high-barrier sub-layer 102.

[0051] In fact, in the process of fabricating a light-emitting chip epitaxial layer into a light-emitting chip, the current magnitude at a specific driving voltage can be controlled by controlling the overall resistance of the light-emitting chip, so as to obtain the required emission color; or different driving voltages can be directly supplied to different light-emitting chips during driving, so that the light-emitting chips formed by the same light-emitting chip epitaxial layer can emit different emission colors. Therefore, the above-mentioned light-emitting chip epitaxial layer makes the production of dual-color integrated display products simpler. In some implementation processes, the number of times of transferring light-emitting chips required for manufacturing display products is also reduced, which is beneficial to production efficiency and yield; in some implementation processes, the number of times of setting up color conversion layers is reduced, simplifying the manufacturing process.

[0052] Exemplarily, the material of the light-emitting chip epitaxial layer can be selected from III / V group semiconductor materials including but not limited to Al (aluminum), Ga (gallium), In (indium), and P (phosphorus), As (arsenic), or N (nitrogen), etc. Usually, it can include, for example, GaN (gallium nitride) - based materials, AlGaInP (aluminum gallium indium phosphide) - based materials, GaAs (gallium arsenide) - based materials, and so on. In practical applications, the light-emitting chip epitaxial layer can be grown on a substrate 5, and the material of the substrate 5 includes but not limited to Al2O3 (aluminum oxide, i.e., sapphire), SiC (silicon carbide), Si (silicon), GaN, and can also be other semiconductor materials; the material of the substrate 5 with better lattice matching can be selected according to the material of the light-emitting chip epitaxial layer.

[0053] In this application, the N-type semiconductor layer and the P-type semiconductor layer only represent the distinction of the conduction type. Specifically, in the epitaxial layer of the light-emitting chip, the N-type semiconductor layer includes an N-type doping source, and the P-type semiconductor layer includes a P-type doping source. For example, Si (silicon) can be used as the N-type doping source for GaN materials, and Mg (magnesium) can be used as the P-type doping source for GaN materials, but it is not limited thereto. The N-type semiconductor layer is used to provide electrons, and the P-type semiconductor layer is used to provide holes. The electrons and holes move to the active region for effective recombination, thereby realizing light emission. When growing the epitaxial layer of the light-emitting chip, the N-type semiconductor layer can be grown first. In some examples, the P-type semiconductor layer can also be grown first, which can be specifically set according to actual needs, and this embodiment does not limit it.

[0054] In practical applications, various means can be used to make the epitaxial layer of the light-emitting chip have a strong quantum-confined Stark effect (that is, having a large range of wavelength shifts under the influence of the quantum-confined Stark effect). As long as the epitaxial layer of the light-emitting chip can have a wavelength shift of more than 60 nanometers, it is feasible. Of course, the 60-nanometer wavelength shift should occur within the normal operating current range of the light-emitting chip, that is, it is not destructive, so as to realize normal application display. For different processes or materials, the specific operating current range will be different, and this application does not specifically limit this.

[0055] In some implementation processes, the quantum-confined Stark effect of the active layer 2 can be enhanced by making the region where the wave functions of electron-hole pairs coincide larger. As an example, the number of periods of the active layer 2 can be increased, which will make the region where the wave functions of electron-hole pairs coincide larger in the active layer 2, and will no longer be concentrated only in the last one or two quantum well layers 22. Thus, under different currents, the recombination positions of different energy bands can be realized. For example, the wave functions of electron-hole pairs can coincide well in the last 4 to 5 quantum well layers 22. In practical applications, various means can also be comprehensively used to make the emission wavelength of the active layer 2 have a wavelength shift of more than 60 nanometers under different currents. For another example, by controlling the stress distribution in the active layer 2, strong stress can enhance the quantum-confined Stark effect of the active layer 2; in practical applications, under the premise of balancing various performances, the stress in the active layer 2 can be increased to a certain extent.

[0056] It should also be noted that in practical applications, in order to ensure the performance in other aspects, the epitaxial layer of the light-emitting chip can also include a structure that suppresses the quantum-confined Stark effect, as long as it is ensured that the epitaxial layer of the light-emitting chip can finally have a wavelength shift of more than 60 nanometers in the emission wavelength under different currents.

[0057] In some embodiments, the high-barrier sub-layer 102 in the Stark effect enhancement layer 11 may adopt an Al-containing material. By controlling the Al component content therein, the barrier height can be controlled. To make the barrier of the high-barrier sub-layer 102 closer to the active layer 2 higher, the high-barrier sub-layer 102 closer to the active layer 2 will have a higher Al component content.

[0058] In this embodiment, the low-barrier sub-layer 101 may include GaN, and the high-barrier sub-layer 102 may include AlN or AlGaN. The high-barrier sub-layer 102 closer to the active layer 2 is configured to have a higher Al component content.

[0059] As Figure 4 As shown in (a), in the low-barrier sub-layer 101 and the high-barrier sub-layer 102, the barrier height within a single layer (shown as the longitudinal height in the figure) can remain unchanged. For example, in a single high-barrier sub-layer 102, the Al component content remains unchanged, and a differentiated barrier height is formed between different high-barrier sub-layers 102. In this embodiment, the Al component content range of the high-barrier sub-layer 102 farthest from the active layer 2 can be configured to be 1% to 7%, such as 2%, 3%, 4%, 5%, 6%, etc.; the Al component content range of the high-barrier sub-layer 102 closest to the active layer 2 can be configured to be 7% to 20%, such as 9%, 11%, 13%, 15%, 17%, 19%, etc. For the high-barrier sub-layer 102, during the process of approaching the active layer 2, its Al component content can increase linearly layer by layer. In some embodiments, it can also be configured to increase non-linearly layer by layer.

[0060] To ensure that the kinetic energy of electrons is sufficiently reduced, the number of periods of the low-barrier sub-layer 101 and the high-barrier sub-layer 102 is in the range of 5 to 20, such as 7, 9, 10, 13, 15, 17, 19, etc.; in some examples, it can also be configured to exceed 20. More periods of the low-barrier sub-layer 101 and the high-barrier sub-layer 102 enable electrons to move from a low electric potential to a high electric potential multiple times when passing through the Stark effect enhancement layer 11. Moreover, the positive electrode has an excess of positive charges and lacks negative-charged electrons. When the positive charges and electrons neutralize, it also promotes the deceleration of electrons. At the same time, since the electric field strength near the positive electrode is greater than that near the negative electrode, the electric force on the electrons near the positive electrode is also greater, which further promotes the deceleration of electrons; thereby increasing the concentration of electron-hole pairs in the active region. It can be seen that setting the above-mentioned Stark effect enhancement layer 11 in the N-type semiconductor layer can well weaken the kinetic energy of electrons. It can be understood that the Stark effect enhancement layer 11 is not limited to the exemplary structure, and the effect of reducing the kinetic energy of electrons may be different for different structures of the Stark effect enhancement layer 11. In practical applications, the number of its layers can be set according to the actual situation.

[0061] The changing trends of the doping concentration and the Al component content in the exemplary Stark effect enhancement layer 11 can be respectively as shown in Figure 4 (b) and Figure 4 (c). Figure 4 The vertical height of (b) reflects the relative level of its doping concentration. Figure 4 The vertical height of (c) reflects the relative level of its Al component concentration.

[0062] Continuing with the Stark effect enhancement layer 11 in the foregoing example, the doping concentration range of the low barrier sub-layer 101 therein is 1E 18 atoms per cubic centimeter to 9E 18 atoms per cubic centimeter. For example, it can be 2E 18 atoms per cubic centimeter, 3E 18 atoms per cubic centimeter, 4E 18 atoms per cubic centimeter, 5E 18 atoms per cubic centimeter, 6E 18 atoms per cubic centimeter, 7E 18 atoms per cubic centimeter, 8E 18 atoms per cubic centimeter, etc.; its thickness range can be set to 0.5 nanometers to 5 nanometers, such as 1 nanometer, 1.5 nanometers, 2 nanometers, 2.5 nanometers, 3 nanometers, 3.5 nanometers, 4 nanometers, 4.5 nanometers, etc.

[0063] The high barrier sub-layer 102 therein can be undoped; its thickness range can be set to 0.2 nanometers to 3 nanometers, such as 0.5 nanometers, 0.8 nanometers, 1.2 nanometers, 1.5 nanometers, 2 nanometers, 2.3 nanometers, 2.8 nanometers, etc. In this embodiment, the total thickness range of the Stark effect enhancement layer 11 can be controlled within 50 nanometers to 150 nanometers, such as 70 nanometers, 90 nanometers, 110 nanometers, 130 nanometers, etc.

[0064] As Figure 5 shown, in some embodiments, the N-type semiconductor layer further includes an electron aggregation layer 12, which is disposed on the side of the Stark effect enhancement layer 11 close to the active layer 2. The doping concentration of the electron aggregation layer 12 changes alternately in a high-low pattern along the growth direction; Exemplarily, referring to Figure 4 (b), the doping concentration of the electron aggregation layer 12 gradually increases from the lower limit to the upper limit, and then decreases from the upper limit to the lower limit, thus forming an alternating high-low change. The rate of change of the doping concentration can be linear or non-linear. The electron aggregation layer 12 can converge the electrons whose kinetic energy has been weakened by the Stark effect enhancement layer 11 here, further enhancing the hindering effect on the electrons, and can further improve the quantum-confined Stark effect of the active layer 2 in some implementation processes.

[0065] Exemplarily, the electron aggregation layer 12 can be configured to satisfy at least one of the following conditions:

[0066] The lower limit range of the doping concentration of the electron accumulation layer 12 is 1E 17 atoms per cubic centimeter to 5E 17 atoms per cubic centimeter, such as 2E 17 atoms per cubic centimeter, 3E 17 atoms per cubic centimeter, 4E 17 atoms per cubic centimeter, etc.; the upper limit range of the doping concentration is 6E 17 atoms per cubic centimeter to 9E 17 atoms per cubic centimeter, such as 7E 17 atoms per cubic centimeter, 8E 17 atoms per cubic centimeter, etc. The doping concentration of the electron accumulation layer 12 is configured to be a relatively low doping concentration, and at the same time, it can cover the rough interface with high doping, which is beneficial to the growth of the active layer 2.

[0067] The number of change cycles of the doping concentration of the electron accumulation layer 12 ranges from 20 to 30, such as 22, 24, 26, 28, etc.;

[0068] The thickness range of the electron accumulation layer 12 is 20 nanometers to 100 nanometers, such as 40 nanometers, 60 nanometers, 80 nanometers, etc.

[0069] In this embodiment, the material of the electron accumulation layer 12 can be GaN, but is not limited thereto.

[0070] In traditional applications, the number of periods of the quantum barrier layer 21 and the quantum well layer 22 in the active layer 2 is usually configured to be about 10. The design of the number of periods is only to meet the requirement of monochromatic light emission and ensure stable light emission within a fixed driving voltage range. In some embodiments of the present embodiment, the number of periods of the quantum barrier layer 21 and the quantum well layer 22 in the active layer 2 is configured to be not less than 15. As mentioned above, this will make the region where the wave functions of electron-hole pairs overlap larger in the active layer 2, weaken the rapid decrease of the light efficiency when the current increases, and thus enhance the influence that the quantum-confined Stark effect can produce. The number of periods of the quantum barrier layer 21 and the quantum well layer 22 can be configured to be more, such as 17 periods, 19 periods, or even more than 20 periods, such as 21 periods, 23 periods, etc. In practical applications, the specific number of periods of the quantum barrier layer 21 and the quantum well layer 22 can be configured according to the overlap of the wave functions of electron-hole pairs. For example, the number of periods can be determined such that the wave functions of electron-hole pairs can form a good overlap in the last 4 to 5 pairs of quantum well layers 22 or even a larger range. In some embodiments, for the consideration of the overall thickness and performance, the number of periods of the quantum barrier layer 21 and the quantum well layer 22 can be set to not more than 20, that is, the number of periods of the quantum barrier layer 21 and the quantum well layer 22 ranges from 15 to 20, and usually a good overlap of the wave functions of electron-hole pairs can be obtained.

[0071] This embodiment does not limit the material of the epitaxial layer of the light-emitting chip. According to the differences in its materials and components, the emission wavelength of the active layer 2 also varies accordingly. In this embodiment, regardless of the maximum emission wavelength of the active layer 2, as the current increases, a blue shift of 60 nm can be generated on the basis of its maximum emission wavelength.

[0072] To simplify the epitaxial layer of the light-emitting chip and make it easier to fabricate, in some embodiments, the quantum barrier layer 21 includes GaN, the quantum well layer 22 includes InGaN (indium gallium nitride), and the active layer 2 is configured to have an emission wavelength corresponding to green, and as the current increases, the emission wavelength moves to the emission wavelength corresponding to blue. Through a wavelength shift of at least 60 nm, the transition from green light to blue light can be achieved. It can be seen that in some embodiments, the epitaxial layer of the light-emitting chip can achieve dual-color display of green and blue. At low currents, the emission wavelength of the active layer 2 is in the green band, and at high currents, the emission wavelength of the active layer 2 is in the blue band. The In component content of the green light-emitting chip is relatively high, and the stress between the GaN material quantum barrier layer 21 and the InGaN material quantum well layer 22 is relatively large, which further enhances the quantum-confined Stark effect, and the wavelength blue shift is more obvious; it can relatively easily achieve a large range of wavelength blue shift and achieve the effect of dual-color light emission.

[0073] For another example, the active layer 2 can also be configured to have a light-emitting wavelength corresponding to red, and as the current increases, the light-emitting wavelength moves to the light-emitting wavelength corresponding to green, realizing dual-color display of red and green. In this example, the active layer 2 with a light-emitting wavelength corresponding to red can also use InGaN and GaN materials. In other examples, the material of the active layer 2 can also be others.

[0074] In some embodiments, the N-type semiconductor layer further includes a stress relaxation layer 15 adjacent to the active layer 2. The stress relaxation layer 15 can slow down dislocations and stress before growing subsequent materials, ensuring better growth of the active layer 2.

[0075] In some embodiments, the P-type semiconductor layer further includes a hole-accumulating layer 31 disposed on the active layer 2. The hole-accumulating layer 31 can serve as a relay station for hole migration, ensuring the effective number and distribution of holes in the active region.

[0076] The epitaxial layer of the light-emitting chip in this embodiment can be fabricated into a light-emitting chip. In practical applications, a single epitaxial layer of the light-emitting chip can usually be fabricated into multiple light-emitting chips. Based on the epitaxial layer of the light-emitting chip in this embodiment, MicroLED chips can be fabricated, but not limited thereto. For example, Mini LED (Mini Light Emitting Diode) chips can also be fabricated. It can be understood that for light-emitting chips of different sizes, the specific parameter performance of the epitaxial layer of the light-emitting chip can be adjusted, and this application does not limit this. Each light-emitting chip can be closely arranged in an array during fabrication, and the epitaxial layer of the light-emitting chip is divided into multiple regions and corresponds to the light-emitting chips one by one. To simplify the fabrication process of the display product, the interval for fabricating the epitaxial layer of the light-emitting chip into a light-emitting chip can be designed according to the requirements in the display product, and the fabricated light-emitting chips can be transferred and utilized as a whole. The light-emitting chip can be fabricated into a front-mounted or flip-chip structure, or a vertical structure.

[0077] This embodiment also provides a light-emitting chip, which includes the above-mentioned epitaxial layer of the light-emitting chip, a first electrode, and a second electrode. Among them, the first electrode is connected to the first semiconductor layer 1, and the second electrode is connected to the second semiconductor layer 3. The light-emitting chip in this embodiment can be a Micro LED chip, and in some examples, it can also be a Mini LED chip, etc. See Figure 6As shown, an example of a vertical - structure light - emitting chip is presented, which sequentially includes an N - type electrode 41, an N - type semiconductor layer disposed on the N - type electrode 41, an active layer 2, a P - type semiconductor layer disposed on the active layer 2, and a P - type electrode 42 connected to the P - type semiconductor layer. In some examples, the light - emitting chip includes an ohmic - contact layer. The ohmic - contact layer can be disposed between the N - type electrode 41 and the N - type semiconductor layer, or between the P - type electrode 42 and the P - type semiconductor layer, or ohmic - contact layers are disposed at both places. The material of the ohmic - contact layer includes but is not limited to transparent conductive materials such as ITO (indium tin oxide). For the light - emitting chip of this embodiment, by designing the ohmic - contact resistance of the ohmic - contact layer, it can have a predetermined current under a predetermined driving voltage, thereby achieving a predetermined emission wavelength. For each light - emitting chip formed by the epitaxial layer of the light - emitting chip, different ohmic - contact resistances can be formed, so that the light - emitting chips fabricated from the same epitaxial layer of the light - emitting chip can directly achieve two different emission wavelengths under the same driving voltage. In practical applications, the light - emitting chip can be fabricated separately and then transferred to the circuit board, or the epitaxial layer of the light - emitting chip of this application can be directly transferred to the circuit board, and the light - emitting chip can be directly fabricated on the circuit board. This application does not limit this.

[0078] See Figure 7 As shown, this embodiment also provides a method for fabricating an epitaxial layer of a light - emitting chip, and its steps include but are not limited to:

[0079] S101. Set a first semiconductor layer on a substrate;

[0080] S102. Set an active layer on the first semiconductor layer. The active layer is configured to have a quantum - confined Stark effect, and the quantum - confined Stark effect causes the emission wavelength of the active layer to have a wavelength shift of more than 60 nanometers at different currents;

[0081] S103. Set a second semiconductor layer on the active layer;

[0082] The epitaxial layer of the light - emitting chip fabricated by the above - mentioned method for fabricating an epitaxial layer of a light - emitting chip can be the epitaxial layer of the light - emitting chip described above in this embodiment. The first semiconductor layer 1 is an N - type semiconductor layer or a P - type semiconductor layer, and the second semiconductor layer 3 has a different conductivity type from the first semiconductor layer 1. In some examples, the N - type semiconductor layer can be grown first, that is, the first semiconductor layer 1 is an N - type semiconductor layer. In other examples, the P - type semiconductor layer can also be grown first, then the first semiconductor layer 1 is a P - type semiconductor layer.

[0083] In this embodiment, the N-type semiconductor layer includes a Stark effect enhancement layer 11 configured to enhance the quantum-confined Stark effect of the active layer 2. The Stark effect enhancement layer 11 includes a plurality of periods of low-barrier sub-layers 101 and high-barrier sub-layers 102 stacked alternately, and the high-barrier sub-layer 102 closer to the active layer 2 has a higher barrier height. Taking the first semiconductor layer 1 as an N-type semiconductor layer as an example, the process of growing the first semiconductor layer 1 includes growing the Stark effect enhancement layer 11. Similarly, if the second semiconductor layer 3 is an N-type semiconductor layer, the process of growing the second semiconductor layer 3 includes growing the Stark effect enhancement layer 11.

[0084] In some embodiments, the pressure range for setting the Stark effect enhancement layer 11 is 50 mbar to 400 mbar, and the temperature range is 900 °C to 1100 °C; see Figure 8 , and the steps for setting the low-barrier sub-layer 101 and the high-barrier sub-layer 102 in a single period include:

[0085] S201. Grow GaN to form a low-barrier sub-layer;

[0086] S202. Grow AlN or AlGaN to form a high-barrier sub-layer;

[0087] Among them, the high-barrier sub-layer 102 closer to the active layer 2 is configured with a higher Al component content.

[0088] In some embodiments, when setting the N-type semiconductor layer, it further includes: setting an electron aggregation layer 12, the electron aggregation layer 12 is disposed on the side of the Stark effect enhancement layer 11 closer to the active layer 2, and during the setting process of the electron aggregation layer 12, the input amount of the doping source is controlled to alternate between high and low multiple times.

[0089] In some embodiments, the pressure range for setting the electron aggregation layer 12 is 300 mbar to 500 mbar, the temperature range is 600 °C to 800 °C, and the steps for setting the electron aggregation layer 12 include: growing GaN to form the electron aggregation layer 12.

[0090] The active layer 2 of the light-emitting chip epitaxial layer fabricated by the above method for fabricating a light-emitting chip epitaxial layer has a wavelength shift of more than 60 nm in the emission wavelength at different currents. For a light-emitting chip fabricated using this light-emitting chip epitaxial layer, the desired emission color can be obtained by controlling the magnitude of the current under its driving voltage; or different driving voltages can be directly supplied to different light-emitting chips during driving, so that the light-emitting chips formed from the same light-emitting chip epitaxial layer emit different emission colors. Moreover, the barrier height of the high-barrier sub-layer 102 gradually increases in the direction approaching the active layer 2, enabling the current to have a better lateral expansion effect during the process of passing through the Stark effect enhancement layer 11. This further ensures the light efficiency, enabling the active layer 2 to emit light normally under a stronger quantum-confined Stark effect. In some implementation processes, the number of times of transferring the light-emitting chips required for manufacturing display products is also reduced, which is beneficial to production efficiency and yield; in some implementation processes, the number of times of setting up the color conversion layer is reduced, simplifying the manufacturing process.

[0091] See Figure 9 , this embodiment also provides a specific structure of a light-emitting chip epitaxial layer. The light-emitting chip epitaxial layer in this example realizes dual-color display of blue and green. The following is an explanation in combination with its manufacturing process. The manufacturing process of the light-emitting chip epitaxial layer in this example includes but is not limited to:

[0092] S301. See Figure 9 of (a), provide a substrate 5. The material of the light-emitting chip epitaxial layer in this example is mainly GaN, and the substrate 5 can be made of materials such as Al2O3, SiC, Si, or GaN.

[0093] S302. See Figure 9 of (b), grow an undoped GaN buffer layer 13 on the substrate 5. The GaN buffer layer 13 is used to relieve the stress and defects caused by lattice mismatch. Exemplarily, the thickness range of the GaN buffer layer 13 can be 1.8 μm to 2.3 μm, such as 1.9 μm, 2 μm, 2.1 μm, 2.2 μm, etc.

[0094] S303. See Figure 9 of (c), grow an N-type doped GaN layer 14 on the GaN buffer layer 13. In this example, silicon is used as the N-type doping source for GaN, and its doping concentration range can be 1E 19 atoms per cubic centimeter to 2.5E 19 atoms per cubic centimeter, such as 1.3E 19 atoms per cubic centimeter, 1.5E 19 atoms per cubic centimeter, 1.7E 19 atoms per cubic centimeter, 1.9E 19 atoms per cubic centimeter, 2.1E 19 atoms per cubic centimeter, 2.3E19 per cubic centimeter of atoms, etc. The thickness of the N-type doped GaN layer 14 can range from 1 μm to 1.5 μm, such as 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, etc.

[0095] S304, see Figure 9 (d) of, grow a Stark effect enhancement layer 11 on the N-type doped GaN layer 14. In this example, the Stark effect enhancement layer 11 includes a plurality of periods of low-barrier sub-layers 101 and high-barrier sub-layers 102 stacked alternately. The number of set periods ranges from 5 to 20, which strongly weakens the kinetic energy of electrons and enhances the quantum-confined Stark effect of the active layer 2; the total thickness range can be controlled within 50 nm to 150 nm, and controlling its total thickness will not be too high to avoid significantly increasing the total thickness of the epitaxial layer of the light-emitting chip, facilitating the production in the subsequent process.

[0096] The following also exemplifies a specific structure of the Stark effect enhancement layer 11 and its manufacturing process, which includes but is not limited to:

[0097] S401, grow a low-barrier sub-layer 101, the material of which can be N-type doped GaN. During the growth process, turn off the Al source and turn on the Si source. As in the previous example of this embodiment, its thickness range can be set from 0.5 nm to 5 nm, and the doping concentration range is 1E 18 atoms per cubic centimeter to 9E 18 atoms per cubic centimeter. When growing a gallium-containing structure such as the low-barrier sub-layer 101, trimethylgallium (TMGa) can be used as the gallium source, but it is not limited thereto.

[0098] S402, grow a high-barrier sub-layer 102, the material of which can be undoped AlN or AlGaN. When the high-barrier sub-layer 102 uses AlN, turn off the Ga source and the Si source and turn on the Al source; when the high-barrier sub-layer 102 uses AlGaN, switch the flow rate of the Ga source to a smaller flow rate, turn off the Si source, and turn on the Al source. Among them, the Al source can use trimethylaluminum (TMAl), but it is not limited thereto.

[0099] The above steps S401 to S402 illustrate the manufacturing process of the low-barrier sub-layer 101 and the high-barrier sub-layer 102 in a single cycle. Repeat the above steps 5 to 20 times to complete the manufacturing of the Stark effect enhancement layer 11. And during this process, each time the high-barrier sub-layer 102 is grown, the Al component content increases layer by layer. As exemplified in the foregoing of this embodiment, it increases from a value in the range of 1% to 7% to a value in the range of 7% to 20%. Exemplarily, the pressure range during the growth of the Stark effect enhancement layer 11 can be configured as 50 mbar to 400 mbar, such as 100 mbar, 150 mbar, 200 mbar, 250 mbar, 300 mbar, 350 mbar, etc.; the temperature range is 900 °C to 1100 °C, such as 950 °C, 1000 °C, 1050 °C, etc. The growth pressure and growth temperature of the low-barrier sub-layer 101 and the high-barrier sub-layer 102 can be the same or different.

[0100] S305. Refer to Figure 9 (e) of, grow the electron aggregation layer 12 on the Stark effect enhancement layer 11. In this example, the electron aggregation layer 12 uses a GaN material with a lower doping concentration. As exemplified in the foregoing of this embodiment, its thickness range can be configured as 20 nanometers to 100 nanometers; the lower limit range of the doping concentration is 1E 17 atoms per cubic centimeter to 5E 17 atoms per cubic centimeter, and the upper limit range is 6E 17 atoms per cubic centimeter to 9E 17 atoms per cubic centimeter. During the growth of the electron aggregation layer 12, the Ga source is turned on and its flow rate is maintained constant, the Si source is turned on, and its flow rate size changes repeatedly between the lower limit and the upper limit of the doping concentration, so as to realize the alternating change of the doping concentration along the growth direction. Exemplarily, the pressure range during the growth of the electron aggregation layer 12 can be configured as 300 mbar to 500 mbar, such as 350 mbar, 400 mbar, 450 mbar, etc.; the temperature range is 600 °C to 800 °C, such as 650 °C, 700 °C, 750 °C, etc. Setting the electron aggregation layer 12 with a relatively low doping concentration between the stress release layer 15 and the Stark effect enhancement layer 11 with a relatively high N-type doping concentration can further enhance the quantum-confined Stark effect while covering the rough interface of the high doping, which is beneficial to ensuring the growth quality of the subsequent structure.

[0101] S306. Refer to Figure 9 (f) of, grow the stress release layer 15 on the low-doped GaN layer; refer to Figure 10 , in this example, the stress release layer 15 includes multiple alternating cycles of InxGa1 -xN层151 and GaN layer 152. Exemplarily, the value range of x is 0.01 to 0.08, such as 0.03, 0.05, 0.07, etc. The range of the number of set periods can be 3 to 9, such as 5, 6, 8, etc. Among them, InxGa1 -xN层 The thickness range of 151 can be 0.5 nanometers to 1.5 nanometers, such as 0.7 nanometers, 1 nanometer, 1.3 nanometers, etc.; in some examples, InxGa1 -xN层 The thickness range of 151 can also be 0.5 nanometers to 3 nanometers, such as 1.7 nanometers, 2 nanometers, 2.5 nanometers, etc. The thickness range of GaN layer 152 can be 1.5 nanometers to 4.5 nanometers, such as 2 nanometers, 3 nanometers, 4 nanometers, etc.; in some examples, the thickness range of GaN layer 152 can also be 1.5 nanometers to 5 nanometers. In this example, the quantum well layer 22 of the active layer 2 will also use In y Ga 1-y N material, where the value range of y can be 0.06 to 0.18, such as 0.08, 0.1, 0.12, 0.14, 0.16, etc. The In component content in the stress relaxation layer 15 is lower than that in the quantum well layer 22. The growth stress is relieved through the stress relaxation layer 15. When the active layer 2 is grown, a higher concentration of In component is more likely to be injected.

[0102] S307. Refer to Figure 9 (g), grow the active layer 2 on the stress relaxation layer 15. In this example, the active layer 2 includes a plurality of alternately arranged periods of quantum barrier layers 21 (the material includes GaN) and quantum well layers 22 (the material includes In y Ga 1-y N). Exemplarily, the value of y is 0.12, and the range of the number of set periods can be 15 to 20. In this example, the thickness range of each quantum barrier layer 21 can be 5 nanometers to 15 nanometers, such as 7 nanometers, 9 nanometers, 11 nanometers, 13 nanometers, etc.; the thickness range of each quantum well layer 22 can be 1.5 nanometers to 3.5 nanometers, such as 2 nanometers, 2.5 nanometers, 3 nanometers, etc. Compared with about 10 periods in the traditional active layer 2, the number of periods of the quantum barrier layer 21 and the quantum well layer 22 is increased in this example, and the region where the wave functions of electron-hole pairs overlap is larger. In some implementation processes, cooperating with the Stark effect enhancement layer 11 to weaken the electron kinetic energy, it can make the wave functions of electron-hole pairs overlap well in the last 4 to 5 pairs of quantum well layers 22, further enhancing the quantum-confined Stark effect. The active layer 2 of this example can have a corresponding green emission wavelength, and the strong quantum-confined Stark effect enables it to have a wavelength shift of more than 60 nanometers under different currents; as the current increases, affected by the quantum-confined Stark effect, its emission wavelength can be blue-shifted to the blue range, realizing two-color emission.

[0103] S308. Refer to Figure 9 (h) thereof. A hole-accumulating layer 31 is grown on the active layer 2. In this example, the hole-accumulating layer 31 includes a GaN material, and the set thickness range thereof can be 60 nanometers to 80 nanometers, such as 65 nanometers, 70 nanometers, 75 nanometers, etc.; the hole-accumulating layer 31 is doped with a P-type doping source. In this example, Mg is used as the P-type doping source, and its doping concentration is greater than 1E 19 atoms per cubic centimeter. For example, it can be 2E 19 atoms per cubic centimeter, 3E 19 atoms per cubic centimeter, 4E 19 atoms per cubic centimeter, etc.

[0104] S309. Refer to Figure 9 (i) thereof. A P-type doped GaN layer 32 is grown on the hole-accumulating layer 31. In this example, Mg is used as the P-type doping source for GaN, and the doping concentration range thereof can be 3E 19 atoms per cubic centimeter to 1E 20 atoms per cubic centimeter. For example, it can be 4E 19 atoms per cubic centimeter, 6E 19 atoms per cubic centimeter, 8E 19 atoms per cubic centimeter, etc. The thickness range of the P-type doped GaN layer 32 can be 100 nanometers to 140 nanometers, such as 110 nanometers, 120 nanometers, 130 nanometers, etc.

[0105] S310. Refer to Figure 9 (j) thereof. A P-type doped ohmic contact layer 33 is grown on the P-type doped GaN layer 32. Its material includes GaN, and Mg is used as the P-type doping source therein, and the doping concentration is greater than 1E 20 atoms per cubic centimeter. For example, it can be 2E 20 atoms per cubic centimeter, 3E 20 atoms per cubic centimeter, 4E 20 atoms per cubic centimeter, etc. A higher doping concentration can achieve better ohmic contact. The thickness range thereof can be 10 nanometers to 20 nanometers, such as 12 nanometers, 14 nanometers, 16 nanometers, 18 nanometers, etc.

[0106] In this example, the total thickness range of the light-emitting chip epitaxial layer can be controlled at about 3.8 μm, and exemplarily it is 3.6 μm to 4 μm, such as 3.7 μm, 3.8 μm, 3.9 μm, etc. Micro LED chips with a pixel size of about 2 μm or even smaller can be fabricated. The relatively thin thickness also facilitates the subsequent manufacturing process and leaves more space for setting other structures such as microlenses.

[0107] For the epitaxial layer of the light-emitting chip in the above example, by providing a larger number of Stark effect enhancement layers 11 to reduce the kinetic energy of electrons and increasing the setting period of the active layer 2, the overlapping region of the wave functions of electron-hole pairs is made larger, so that a strong quantum-confined Stark effect is achieved, and the emission wavelength shift exceeds 60 nm at different currents. This enables the light-emitting chip to exhibit different emission colors by simply configuring different drive currents, without the need for complex design in the subsequent process, making the production of dual-color integrated display products simpler. Moreover, structures such as the stress release layer 15 and the hole accumulation layer 31 also ensure the quality of the epitaxial layer of the light-emitting chip during fabrication, and have a positive effect on achieving a strong quantum-confined Stark effect.

[0108] It should be understood that the application of the present application is not limited to the above examples. For those of ordinary skill in the art, improvements or transformations can be made according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present application.

Claims

1. A light-emitting chip epitaxial layer, characterized in that, Comprising: A first semiconductor layer; An active layer disposed on the first semiconductor layer; And A second semiconductor layer disposed on a side of the active layer away from the first semiconductor layer; Wherein, the first semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer, and the second semiconductor layer has a different conductivity type from the first semiconductor layer; the N-type semiconductor layer includes a Stark effect enhancement layer configured to enhance the quantum-confined Stark effect of the active layer; the Stark effect enhancement layer includes a plurality of periods of alternately stacked low-barrier sub-layers and high-barrier sub-layers, and the high-barrier sub-layer closer to the active layer has a larger barrier height; the active layer is configured to have a quantum-confined Stark effect, and the quantum-confined Stark effect causes the emission wavelength of the active layer at different currents to have a wavelength shift of more than 60 nm.

2. The epitaxial layer of the light-emitting chip according to claim 1, wherein The low-barrier sub-layer includes GaN, the high-barrier sub-layer includes AlN or AlGaN, and the high-barrier sub-layer closer to the active layer has a higher Al component content.

3. The epitaxial layer of the light-emitting chip according to claim 2, wherein, In a single high-barrier sub-layer, the Al component content is constant; wherein, the Al component content range of the high-barrier sub-layer furthest from the active layer is 1% to 7%, and the Al component content range of the high-barrier sub-layer closest to the active layer is 7% to 20%.

4. The epitaxial layer of the light-emitting chip according to claim 2, wherein, The range of the number of periods of the low-barrier sub-layers and the high-barrier sub-layers is 5 to 20.

5. The epitaxial layer of the light-emitting chip according to claim 2, characterized in that The doping concentration range of the low-barrier sub-layer is 1E 18 atoms per cubic centimeter to 9E 18 atoms per cubic centimeter, and the high-barrier sub-layer is undoped; the thickness range of a single low-barrier sub-layer is 0.5 nm to 5 nm, and the thickness range of a single high-barrier sub-layer is 0.2 nm to 3 nm.

6. The epitaxial layer of the light-emitting chip according to claim 1, characterized in that, The N-type semiconductor layer further includes an electron accumulation layer disposed on a side of the Stark effect enhancement layer close to the active layer, and the doping concentration of the electron accumulation layer alternately changes between high and low levels multiple times along the growth direction.

7. The epitaxial layer of the light-emitting chip according to claim 6, wherein The electron accumulation layer includes GaN and satisfies at least one of the following conditions: The lower limit range of the doping concentration of the electron aggregation layer is 1E 17 atoms per cubic centimeter to 5E 17 atoms per cubic centimeter, and the upper limit range is 6E 17 atoms per cubic centimeter to 9E 17 atoms per cubic centimeter; The range of the number of periods of the change in the doping concentration of the electron accumulation layer is 20 to 30; The thickness range of the electron accumulation layer is 20 nm to 100 nm.

8. The epitaxial layer of the light-emitting chip according to any one of claims 1-7, characterized in that The active layer includes alternately arranged quantum barrier layers and quantum well layers, and the number of periods of the quantum barrier layers and the quantum well layers is not less than 15.

9. A method for fabricating an epitaxial layer of a light-emitting chip, characterized in that Comprising: Setting a first semiconductor layer on a substrate; Setting an active layer on the first semiconductor layer; And Setting a second semiconductor layer on the active layer; Wherein, the first semiconductor layer is an N-type semiconductor layer or a P-type semiconductor layer, and the second semiconductor layer has a different conductivity type from the first semiconductor layer; the N-type semiconductor layer includes a Stark effect enhancement layer configured to enhance the quantum-confined Stark effect of the active layer; the Stark effect enhancement layer includes a plurality of periods of alternately stacked low-barrier sub-layers and high-barrier sub-layers, and the high-barrier sub-layer closer to the active layer has a larger barrier height; the active layer is configured to have a quantum-confined Stark effect, and the quantum-confined Stark effect causes the emission wavelength of the active layer at different currents to have a wavelength shift of more than 60 nm.

10. The manufacturing method of the light-emitting chip epitaxial layer according to claim 9, wherein, The pressure range when setting the Stark effect enhancement layer is 50 mbar to 400 mbar, and the temperature range is 900 °C to 1100 °C; the setting steps of the low-barrier sub-layer and the high-barrier sub-layer in a single period include: Growing GaN to form the low-barrier sub-layer; Growing AlN or AlGaN to form the high-barrier sublayer; Among them, the high-barrier sublayer closer to the active layer is configured with a higher Al component content.

11. The manufacturing method of the light-emitting chip epitaxial layer according to claim 9, characterized in that, When setting the N-type semiconductor layer, it further includes: Setting an electron accumulation layer, the electron accumulation layer is disposed on one side of the Stark effect enhancement layer closer to the active layer, and during the setting process of the electron accumulation layer, the introduction amount of the doping source is controlled to alternately change between high and low multiple times.

12. The manufacturing method of the light-emitting chip epitaxial layer according to claim 11, characterized in that, The pressure range for setting the electron accumulation layer is 300 mbar to 500 mbar, and the temperature range is 600 °C to 800 °C. The step of setting the electron accumulation layer includes: Growing GaN to form the electron accumulation layer.

13. A light-emitting chip, characterized in that, Including: The light-emitting chip epitaxial layer according to any one of claims 1-8; A first electrode connected to the first semiconductor layer; And A second electrode connected to the second semiconductor layer.

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