Antenna switch module, radio frequency front end and communication device

Abstract

The invention discloses an antenna switch module, a radio frequency front end and a communication device, relates to the field of wireless communication, and is used for avoiding connection conflicts between ports on two sides of an ASM through independent decoupling of control logics of two groups of ports of the ASM without increasing insertion loss. The antenna switch module comprises a first group of ports, a second group of ports, a control circuit, a switch circuit and a register, the first group of ports are coupled with the second group of ports through the switching circuit; the register stores a first parameter and a second parameter of the first virtual common node, the first parameter is used for indicating which port of the first group of ports is conducted with the first virtual common node, and the second parameter is used for indicating which port of the second group of ports is conducted with the first virtual common node; and the control circuit controls the switching circuit to conduct the ports in the first group of ports and the ports in the second group of ports according to the result of AND after the first parameter and the second parameter of the first virtual common node are decoded.

Description

Antenna switch modules, RF front ends, and communication devices

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on April 21, 2023, with application number 202310459358.X and invention name “Antenna switch module, RF front end and communication device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of wireless communications, and in particular to an antenna switch module, a radio frequency front end, and a communication device. Background Art

[0003] Multiple channels in a communication device (e.g., a transmit channel and a receive channel, or two receive channels) are coupled to multiple antennas via an antenna switch module (ASM). Specifically, the first set of ports of the ASM is used to couple to multiple channels, while the second set of ports is used to couple to multiple antennas. Switches connected in series along the RF signal transmission path can result in significant insertion loss, impacting the transmission efficiency and receive sensitivity of the RF signal. Therefore, the fewer switches connected in series along the transmission path, the better. Therefore, within the ASM, a single port in the first set of ports is typically coupled to a single port in the second set of ports via a switch. When this switch is closed, a channel is connected to a single antenna, enabling one channel to occupy one antenna. When multiple channels occupy multiple antennas, switching between different channels and antennas is required. For example, connecting the same antenna to different channels, or vice versa, involves controlling the on and off of multiple switches. Consequently, the control logic of the switches is complex, and control logic conflicts are prone to occur during use. For example, multiple channels may be connected to a single antenna simultaneously, or multiple antennas may be connected to a single channel simultaneously. If more switches are connected in series to the ASM ports to further constrain the control logic for the conduction between multiple channels and multiple antennas to avoid control logic conflicts, the insertion loss of the transmission path will increase.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide an antenna switch module, a radio frequency front end, and a communication device, which independently decouple the control logic of the two groups of ASM ports to avoid conflicts in the conduction between the two groups of ASM ports without increasing insertion loss.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, an antenna switch module is provided, comprising: a first group of ports, a second group of ports, a control circuit, a switching circuit, and a register; the first group of ports is coupled to the second group of ports via the switching circuit; the first group of ports is coupled to multiple channels, and the second group of ports is coupled to multiple antennas. The register is configured to store a first parameter and a second parameter of a first virtual public node; the first parameter of the first virtual public node is configured to indicate which port in the first group of ports is electrically conductive with the first virtual public node, and the second parameter of the first virtual public node is configured to indicate which port in the second group of ports is electrically conductive with the first virtual public node; the control circuit is configured to control the switching circuit to electrically conductively connect a port in the first group of ports to a port in the second group of ports based on a decoded AND result of the first and second parameters of the first virtual public node.

[0008] The antenna switch module, radio frequency front end and communication device provided by the embodiment of the present application establish a virtual public node in the ASM, which is an intermediate node connected between the first group of ports and the second group of ports. The first parameter and the second parameter of the virtual public node are configured in the register in the ASM. The first parameter indicates which port in the first group of ports is connected to the virtual public node, and the first parameter is equivalent to controlling the first single-pole multi-throw switch between the first group of ports and the virtual public node; the second parameter indicates which port in the second group of ports is connected to the virtual public node, and the second parameter is equivalent to controlling the second single-pole multi-throw switch between the second group of ports and the virtual public node. The control circuit controls the switch circuit to connect the ports in the first group of ports with the ports in the second group of ports according to the first parameter and the second parameter, which is equivalent to connecting the ports in the first group of ports with the ports in the second group of ports through the virtual public node. By independently decoupling the control logic of the two groups of ports of the ASM, the conflict of conduction between the two groups of ports of the ASM is avoided. And because no physical switch is added, but the control logic of the switch in the ASM is constrained, the insertion loss will not be increased.

[0009] In one possible embodiment, the multiple channels include a transmit channel and a first receive channel, the multiple antennas include a first antenna and a second antenna, the first group of ports includes a transmit port and a first receive port, the transmit port is used to couple to the transmit channel, the first receive port is used to couple to the first receive channel, the second group of ports includes a first antenna port, a second antenna port, and a sounding reference signal (SRS) output port, the first antenna port is used to couple to the first antenna, the second antenna port is used to couple to the second antenna, and the SRS output port is used to couple to other RF modules; the switching circuit includes: a first switch, a second switch, a fourth switch, and a seventh switch; the transmit port is coupled to the first antenna port via the first switch, the transmit port is coupled to the second antenna port via the fourth switch, and the transmit port is coupled to the SRS output port via the seventh switch; the first receive port is coupled to the first antenna port via the second switch. This embodiment discloses the connection method between the switch and each port in the switching circuit.

[0010] In one possible embodiment, the control circuit is specifically configured to control the switch circuit to conduct the ports in the first group of ports with the ports in the second group of ports based on the result of the decoded AND operation of the first parameter and the second parameter of the first virtual common node. The control circuit performs an AND operation based on the decoded first parameter and the second parameter, which is equivalent to the aforementioned first single-pole multi-throw switch and the second single-pole multi-throw switch being connected in series via the virtual common node, with the virtual common node serving as the only common node for the two virtual groups of ports. The result of the AND operation is used to control the switch circuit to conduct the ports in the first group of ports with the ports in the second group of ports, which is equivalent to conducting the ports in the first group of ports with the ports in the second group of ports via the virtual common node. By independently decoupling the control logic of the two groups of ASM ports, conflicts in the conduction between the two groups of ASM ports are avoided.

[0011] In one possible embodiment, the control circuit includes a first decoder, a second decoder, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate; an input end of the first decoder is used to input a first parameter of the first virtual common node; an input end of the second decoder is used to input a second parameter of the first virtual common node; a first output end of the first decoder and a first output end of the second decoder are respectively coupled to two input ends of the first AND gate, and the output end of the first AND gate is used to control the on and off of the first switch; the second output end of the first decoder and the first output end of the second decoder are respectively coupled to two input ends of a fourth AND gate, and the output end of the fourth AND gate is used to control the on and off of the second switch; the first output end of the first decoder and the second output end of the second decoder are respectively coupled to two input ends of the second AND gate, and the output end of the second AND gate is used to control the on and off of the fourth switch; the third output end of the second decoder is coupled to two input ends of the third AND gate, and the output end of the third AND gate is used to control the on and off of the seventh switch. The AND gate is used to perform an AND operation on the decoded results of the first parameter and the second parameter. The AND gate outputs the operation result to control the on and off of the switch. Different decoding results of the first parameter represent different ports in the first group of ports, and different decoding results of the second parameter represent different ports in the second group of ports.

[0012] In one possible implementation, the multiple channels further include a second receive channel, the first group of ports further includes a second receive port, the second receive port is configured to be coupled to the second receive channel, and the switching circuit further includes a fifth switch, the second receive port being coupled to the second antenna port via the fifth switch. When the first antenna port is occupied, the second receive port can be connected to the second antenna port via the fifth switch, thereby occupying the second antenna port.

[0013] In one possible implementation, the control circuit further includes a third decoder, wherein an input terminal of the third decoder is used to input a third parameter, and an output terminal of the third decoder is used to control the on and off of the fifth switch. The third parameter is used to control direct connection between one of the first group of ports and one of the second group of ports without passing through the virtual common node.

[0014] In one possible embodiment, the register is further used to store a first parameter and a second parameter of a second virtual public node, the first parameter of the second virtual public node being used to indicate which port in the first group of ports is connected to the second virtual public node, and the second parameter of the second virtual public node being used to indicate which port in the second group of ports is connected to the second virtual public node; the control circuit is used to control the switch circuit to connect a port in the first group of ports to a port in the second group of ports based on a decoded AND result of the first parameter and the second parameter of the first virtual public node, or based on a decoded AND result of the first parameter and the second parameter of the second virtual public node. The second virtual public node and the first virtual public node are equivalent and can be interchanged reciprocally. The two antenna ports respectively coupled to the two virtual public nodes can both serve as primary transceiver ports, without being restricted by layout and wiring, and providing greater flexibility in use.

[0015] In one possible implementation, the multiple channels include a transmit channel, a first receive channel, and a second receive channel; the multiple antennas include a first antenna and a second antenna; a first group of ports includes a transmit port, a first receive port, and a second receive port, the transmit port being coupled to the transmit channel, the first receive port being coupled to the first receive channel, and the second receive port being coupled to the second receive channel; a second group of ports includes a first antenna port, a second antenna port, and an SRS output port, the first antenna port being coupled to the first antenna, the second antenna port being coupled to the second antenna, and the SRS output port being coupled to other RF modules; a switching circuit includes a first switch, a second switch, a fourth switch, a fifth switch, and a seventh switch; the transmit port is coupled to the first antenna port via the first switch, the transmit port is coupled to the second antenna port via the fourth switch, and the transmit port is coupled to the SRS output port via the seventh switch; the first receive port is coupled to the first antenna port via the second switch, and the second receive port is coupled to the second antenna port via the fifth switch. The antenna switch module supports one transmit channel and two receive channels, and the two receive channels are equivalent.

[0016] In one possible implementation, the control circuit includes a first decoder, a second decoder, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a third decoder, a fifth decoder, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a first OR gate, a second OR gate, and a third OR gate; the input end of the first decoder is used to input the first parameter of the first virtual public node; the input end of the second decoder is used to input the second parameter of the first virtual public node; the input end of the fifth decoder is used to input the first parameter of the second virtual public node; the input end of the third decoder is used to input the second The first output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to the two input terminals of the first AND gate, and the output terminal of the first AND gate is used to control the conduction and shutoff of the first switch; the second output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to the two input terminals of the fourth AND gate, and the output terminal of the fourth AND gate is used to control the conduction and shutoff of the second switch; the first output terminal of the first decoder and the second output terminal of the second decoder are respectively coupled to the two input terminals of the second AND gate, and the output terminal of the second AND gate is used to control the conduction and shutoff of the fourth switch. The third output terminal of the second decoder is coupled to the two input terminals of the third AND gate, and the output terminal of the third AND gate is used to control the conduction and shutoff of the seventh switch; the first output terminal of the fifth decoder and the first output terminal of the third decoder are respectively coupled to the two input terminals of the fifth AND gate, the output terminal of the fifth AND gate and the output terminal of the first AND gate are respectively coupled to the two input terminals of the first OR gate, and the output terminal of the first OR gate is used to control the conduction and shutoff of the first switch; the second output terminal of the fifth decoder and the first output terminal of the third decoder are respectively coupled to the two input terminals of the eighth AND gate, and the input terminal of the eighth AND gate is respectively coupled to the two input terminals of the eighth AND gate. The output terminal is used to control the conduction and shutoff of the fifth switch; the first output terminal of the fifth decoder and the second output terminal of the third decoder are respectively coupled to the two input terminals of the sixth AND gate, the output terminal of the sixth AND gate and the output terminal of the second AND gate are respectively coupled to the two input terminals of the second OR gate, and the output terminal of the second OR gate is used to control the conduction and shutoff of the fourth switch; the third output terminal of the third decoder is coupled to the two input terminals of the seventh AND gate, the output terminal of the seventh AND gate and the output terminal of the third AND gate are respectively coupled to the two input terminals of the third OR gate, and the output terminal of the third OR gate is used to control the conduction and shutoff of the seventh switch. The first antenna port and the second antenna port are equivalent and can both serve as primary transceiver ports. When the first antenna port serves as the primary transceiver port, it is coupled to one of the ports in the first group through the first virtual common node; when the second antenna port serves as the primary transceiver port, it is coupled to one of the ports in the first group through the second virtual common node.

[0017] In one possible implementation, the first group of ports further includes an SRS input port, which is used to couple to other RF modules. The switching circuit further includes a third switch and a sixth switch. The SRS input port is coupled to the first antenna port via the third switch, and the SRS input port is coupled to the second antenna port via the sixth switch. SRS signals are input from other RF modules of the communication device via the SRS input port and transmitted through the first antenna port or the second antenna port.

[0018] In one possible implementation, the control circuit further includes a fourth decoder, an input terminal of the fourth decoder being used to input a fourth parameter, a first output terminal of the fourth decoder being used to control the on / off state of the third switch, and a second output terminal of the fourth decoder being used to control the on / off state of the sixth switch. The fourth parameter is used to control direct conduction between one of the first group of ports and one of the second group of ports without passing through a virtual common node.

[0019] In a possible implementation, the first parameter and the second parameter of the same virtual public node are stored in one or two registers. When the parameters are stored in one register, hardware cost and circuit board area can be saved.

[0020] In a second aspect, a radio frequency front end is provided, including a power amplifier, a first linear amplifier, a second linear amplifier, a first filter, a second filter, a third filter, and an antenna switch module as described in the first aspect and any embodiment thereof, wherein the power amplifier is coupled to the transmitting port of the antenna switch module through the first filter, the first linear amplifier is coupled to the first receiving port of the antenna switch module through the second filter, and the second linear amplifier is coupled to the second receiving port of the antenna switch module through the third filter.

[0021] In a third aspect, a communication device is provided, comprising a radio frequency front end, a first antenna, and a second antenna as described in the second aspect, wherein the first antenna is coupled to a first antenna port of an antenna switch module in the radio frequency front end, and the second antenna is coupled to a second antenna port of the antenna switch module in the radio frequency front end.

[0022] The technical effects of the second to third aspects refer to the technical effects of the first aspect and any of its embodiments, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic structural diagram of a communication device provided in an embodiment of the present application;

[0024] FIG2 is a schematic structural diagram of a radio frequency front end provided in an embodiment of the present application;

[0025] FIG3 is a schematic diagram of a transmitting channel and a receiving channel in a radio frequency front end provided in an embodiment of the present application;

[0026] FIG4 is a schematic structural diagram of another radio frequency front end provided in an embodiment of the present application;

[0027] FIG5 is a schematic diagram of a transmitting channel and a receiving channel in another radio frequency front end provided in an embodiment of the present application;

[0028] FIG6 is a schematic diagram of the structure of a virtual ASM provided in an embodiment of the present application;

[0029] FIG7 is a schematic diagram of the structure of another virtual ASM provided in an embodiment of the present application;

[0030] FIG8 is a schematic structural diagram of an ASM provided in an embodiment of the present application;

[0031] FIG9 is a schematic structural diagram of a control circuit provided in an embodiment of the present application;

[0032] FIG10 is a schematic structural diagram of another control circuit provided in an embodiment of the present application;

[0033] FIG11 is a schematic diagram of an actual path provided in an embodiment of the present application;

[0034] FIG12 is a schematic diagram of another practical path provided in an embodiment of the present application;

[0035] FIG13 is a schematic diagram of an equivalent path of Scenario 1 provided in an embodiment of the present application;

[0036] FIG14 is a schematic diagram of an actual path of Scenario 1 provided in an embodiment of the present application;

[0037] FIG15 is a schematic diagram of an equivalent path for scenario 2 provided in an embodiment of the present application;

[0038] FIG16 is a schematic diagram of an actual path of Scenario 2 provided in an embodiment of the present application;

[0039] FIG17 is a schematic diagram of an equivalent path for scenario 3 provided in an embodiment of the present application;

[0040] FIG18 is a schematic diagram of an actual path of Scenario 3 provided in an embodiment of the present application;

[0041] FIG19 is a schematic diagram of an equivalent path for scenario 4 provided in an embodiment of the present application;

[0042] FIG20 is a schematic diagram of an actual path of scenario 4 provided in an embodiment of the present application;

[0043] FIG21 is a schematic diagram of an equivalent path of scenario 5 provided in an embodiment of the present application;

[0044] FIG22 is a schematic diagram of an actual path of a scenario 5 provided in an embodiment of the present application;

[0045] FIG23 is a schematic diagram of an equivalent path for scenario 6 provided in an embodiment of the present application;

[0046] FIG24 is a schematic diagram of an actual path of scenario 6 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0047] First, some concepts involved in this application are described.

[0048] The terms "first", "second", etc. involved in the embodiments of the present application are only used to distinguish features of the same type and cannot be understood as indicating relative importance, quantity, order, etc.

[0049] The terms "exemplary" or "for example" in the embodiments of this application are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0050] The terms "coupling" and "connection" involved in the embodiments of this application should be understood in a broad sense. For example, they may refer to a physical direct connection, or an indirect connection achieved through electronic devices, such as a connection achieved through resistors, inductors, capacitors or other electronic devices.

[0051] As shown in FIG1 , an embodiment of the present application provides a communication device 10 , including a baseband chip 11 , a transceiver 12 , a radio frequency front end 13 , and multiple antennas 14 .

[0052] Multiple antennas 14 can achieve both transmit diversity and receive diversity. For example, when transmitting a signal, transmitting the same signal (e.g., the sounding reference signal (SRS) signal discussed later) through different antennas can achieve transmit diversity. When receiving RF signals, receiving signals through different antennas can achieve receive diversity, where the RF signal received by one antenna is the primary receive (PRX) signal, and the RF signals received by the other antennas are the secondary receive (SRX) signals.

[0053] The baseband chip 11 is used for digital domain signal processing, for example, modulating the transmitted signal and demodulating the received signal in the digital domain. The transceiver 12 is used to perform digital-to-analog conversion on the transmitted signal, shifting the transmitted signal from baseband to the intermediate frequency (IF) and from the IF to the radio frequency (RF). The transceiver 12 is also used to shift the received signal from the radio frequency to the intermediate frequency (IF) and from the IF to the baseband, and then perform analog-to-digital conversion on the received signal. The RF front end 13 is a series of components between the transceiver and the antenna, primarily including a power amplifier (PA) for the transmit channel, a low-noise amplifier (LNA) for the receive channel, filters for both the transmit and receive channels, an ASM shared by both channels, and optionally, a SP2T switch (or duplexer) shared by both channels. The PA amplifies the transmit signal from the transceiver 12. The LNA amplifies the receive signal received by the antenna 14. The SP2T switch is used to send received signals to the LNA during receive timeslots and to feed transmit signals from the PA to the antenna 14 during transmit timeslots. The ASM switches the conduction state between multiple antennas 14 and multiple channels (e.g., a transmit channel and a receive channel, or two receive channels). During transmit timeslots, the transmit channel uses the ASM to transmit a sounding reference signal (SRS) to multiple antennas in turn. During receive timeslots, the receive channel uses the ASM to receive signals from multiple antennas. Therefore, the ASM can be considered a multi-pole, multi-throw switch.

[0054] In a possible implementation of the RF front end, as shown in FIG2 , the RF front end 13 includes a PA 21 , a first LNA 22 , a second LNA 23 , an ASM 24 , a first filter 25 , a second filter 26 , and an SP2T switch 27 .

[0055] The ASM 24 includes a first group of ports (transmitting / receiving port TX / RX1, a second receiving port RX2, and an SRS input port SRSIN) on the left side of the figure, a second group of ports (a first antenna port ANT1, a second antenna port ANT2, and an SRS output port SRSOUT) on the right side of the figure, a plurality of switches represented by thick solid lines, a control circuit 241, and a register 242.

[0056] The transmit / receive port TX / RX1 is respectively coupled to the transmit channel (the channel where the PA 21 is located) and the receive channel (the channel where the first LNA 22 is located) through the first filter 25 and the SP2T switch 27 connected in series. The second receive port RX2 is used to couple to the receive channel. The SRS input port SRSIN is used to input SRS signals from other RF modules of this communication device (not shown in the figure). The SRS output port SRSOUT is used to output SRS signals to other RF modules of this communication device (not shown in the figure). The first antenna port ANT1 is used to couple to a first antenna (not shown in the figure), and the second antenna port ANT2 is used to couple to a second antenna (not shown in the figure).

[0057] The first and second groups of ports are coupled via multiple switches (represented by thick solid lines in the figure). To reduce insertion loss, a single port in the first group is coupled to a single port in the second group via a single switch. When the switch is closed, a channel is connected to an antenna, allowing each channel to occupy a single antenna.

[0058] For time division duplexing (TDD), the transmit channel PA 21 and the receive channel's first LNA 22 time-share the first filter 25 via an SP2T switch 27. During transmit timeslots, the SP2T switch 27 connects the PA 21 to the first filter 25; during receive timeslots, the SP2T switch 27 connects the first LNA 22 to the first filter 25. The control circuit 241 in the ASM 24 parses the control parameters stored in the register 242 and, based on the parsed control parameters, controls the connection and disconnection between the first and second groups of ports by turning on and off a switch (indicated by a thick solid line in the figure), thereby achieving different connection states between multiple channels and multiple antennas. For example, the transmit / receive port TX / RX1 is controlled to be connected or disconnected with the first antenna port ANT1, the second antenna port ANT2, and the SRS output port SRSOUT, respectively; the second receive port RX2 is controlled to be connected or disconnected with the second antenna port ANT2; and the SRS input port SRSIN is controlled to be connected or disconnected with the first antenna port ANT1 and the second antenna port ANT2, respectively. For example, Table 1 shows the meaning of the control parameters stored in register 242 in ASM 24.

[0059] Table 1

[0060] As can be seen, the above control parameters define the function of each bit from the perspective of the second group of ports. That is, based on a port in the second group, the connection between that port and the first group of ports is determined. For example, bits [7:6] are used to control the connection between the first antenna port ANT1 and the first group of ports, bits [5:4] are used to control the connection between the second antenna port ANT2 and the first group of ports, and bits [3:2] are used to control the connection between the SRS output port SRSOUT and the first group of ports.

[0061] It should be noted that, in order to simplify the drawings, the registers, control circuits and switches represented by thick solid lines in the ASM are omitted in the drawings related to the ASM below.

[0062] As shown in Figure 3, the solid arrow indicates the transmit channel (the channel where the PA is located), and the dotted arrow indicates the receive channel (the channel where the LNA is located). When the transmit / receive port TX / RX1 of the ASM 24 is connected to the first antenna port ANT1, it can transmit the main transmit signal PTX or the first SRS signal SRS1, or receive the main receive signal PRX. When the transmit / receive port TX / RX1 is connected to the second antenna port ANT2, it can transmit the second SRS signal SRS2. When the transmit / receive port TX / RX1 is connected to the SRS output port SRSOUT, it can transmit the third SRS signal SRS3. When the second receive port RX2 is connected to the second antenna port ANT2, it can receive the second receive signal SRX. When the SRS input port SRSIN is connected to the first antenna port ANT1 and the second antenna port ANT2, respectively, it can transmit SRS signals from other RF modules to the first antenna port ANT1 and the second antenna port ANT2.

[0063] When multiple channels occupy multiple antennas, switching between channels and antennas is required. For example, connecting the same antenna to different channels, or vice versa, involves controlling the on and off of multiple switches. This complicates the control logic of these switches and can easily lead to control logic conflicts during use. Therefore, the system requires a unique common node (such as common node X in Figure 3) between multiple channels (such as the transmit and receive channels) and multiple antennas in the RF front-end. This allows all channels to connect to multiple antennas through this common node. This decouples switching between channels and antennas, facilitating independent control of switching between channels and antennas. Hardware constraints are implemented to control the connection between multiple channels and antennas. For example, this allows for controlling a channel to connect to only one antenna at a time. This prevents developer misconfiguration that could cause connection conflicts between two groups of ASM ports. For example, multiple channels could connect to a single antenna simultaneously, or multiple antennas could connect to a single channel simultaneously.

[0064] ASM 24 can control the transmit / receive port TX / RX1 to connect to the first antenna port ANT1, the second antenna port ANT2, or the SRS output port SRSOUT, respectively, thereby transmitting SRS signals from different antennas to achieve SRS signal transmit diversity. The transmit / receive port TX / RX1 is equivalent to the common node (referred to as the first common node) of the first antenna port ANT1, the second antenna port ANT2, and the SRS output port SRSOUT. The SP2T switch 27 can control the transmit channel (the channel where PA 21 is located) or the receive channel (the channel where first LNA 22 is located) to connect to the transmit / receive port TX / RX1. The right port of SP2T switch 27 is equivalent to the common node (referred to as the second common node) of the transmit and receive channels. Since the first filter 25 is a passive component not controlled by the switch, there is no mutual exclusion issue with the switch control logic. Therefore, the left and right sides of the first filter 25 are equivalent. Therefore, the first common node and the second common node essentially overlap. That is, the common node X shown in the figure is the only common node between multiple channels (e.g., the transmit channel and the receive channel) and multiple antennas.

[0065] By separately controlling the connection or disconnection between multiple ports (equivalent to multiple antennas) or multiple channels (transmitting channels or receiving channels) on both sides of the common node X and the common node X, conflict in the control logic on both sides of the common node X is avoided. For example, the connection or disconnection between multiple channels and the transmit / receive port TX / RX1 can be controlled by the SP2T switch 27.

[0066] However, the aforementioned RF front-end defines the function of each bit from the perspective of the second group of ports. In a multi-SIM scenario, the connectivity between the two groups of ASM ports may still conflict. For example, in dual SIM dual active (DSDA) scenarios, each port of ASM 24 is required to be independently controlled, and a fixed antenna port is configured for each SIM card. As shown in Figure 3, assuming that SIM card 1 and SIM card 2 time-share the same transmit channel but have different receive channels, the first antenna port ANT1 is configured for both the receive and transmit channels of SIM card 1, while the second antenna port ANT2 is configured for both the receive and transmit channels of SIM card 2. During the receive timeslot, SIM card 1's receive channel occupies the transmit / receive port TX / RX1 and the first antenna port ANT1, i.e., bits [7:6] of register A are configured to 01. SIM card 2's receive channel occupies the second receive port RX2 and the second antenna port ANT2, i.e., bits [5:4] of register A are configured to 10. When switching from the receive time slot to the transmit time slot, SIM card 2 will occupy the transmit / receive port TX / RX1 and the second antenna port ANT2, that is, configure bits [5:4] of register A to 01, while SIM card 1 is still occupying the transmit / receive port TX / RX1 and the first antenna port ANT1. That is, the transmit / receive port TX / RX1 is simultaneously connected to the first antenna port ANT1 and the second antenna port ANT2, causing a conflict between the two groups of ASM ports.

[0067] In addition, the SP2T switch 27 in the above-mentioned RF front end will bring large insertion loss to the transmitting channel and the receiving channel, affecting the transmission efficiency of the transmitting channel and the receiving sensitivity of the receiving channel.

[0068] In another possible embodiment of the RF front-end, as shown in Figure 4, the RF front-end 13 does not include the SP2T switch 27 shown in Figure 2 to reduce insertion loss. A third filter 28 is added, and the transmit / receive port TX / RX1 of the ASM 24 becomes a transmit port TX. A first receive port RX1 is added. The first LNA 22 is coupled to the first receive port RX1 of the ASM 24 via the third filter 28. As shown in Figure 5, the solid arrows indicate the transmit path, and the dashed arrows indicate the receive path. When the transmit port TX is connected to the first antenna port ANT1, it can transmit the primary transmit signal PTX or the first SRS signal SRS1. When the first receive port RX1 is connected to the first antenna port ANT1, it can receive the primary receive signal PRX. When the transmit port TX is connected to the second antenna port ANT2, it can transmit the second SRS signal SRS2. When the transmit port TX is connected to the SRS output port SRSOUT, it can transmit the third SRS signal SRS3. When the second receive port RX2 is connected to the second antenna port ANT2, it can receive the slave receive signal SRX. When the SRS input port SRSIN is connected to the first antenna port ANT1 or the second antenna port ANT2 respectively, the SRS signal can be transmitted to other radio frequency modules.

[0069] The transmit port TX can be connected to the first antenna port ANT1, the second antenna port ANT2, or the SRS output port SRSOUT, respectively, to output SRS signals to different antennas, thus implementing SRS signal polling. The transmit port TX acts as the common node for the SRS signal (referred to as the first common node X1). The first antenna port ANT1 can be connected to the transmit port TX or the first receive port RX1, respectively. Therefore, the first antenna port ANT1 acts as the common node for the transmit and receive channels (referred to as the second common node X2). The first common node X1 and the second common node X2 do not overlap, meaning there is no common node between multiple channels and multiple antennas. Therefore, when multiple channels occupy multiple antennas, the connection between the two groups of ASM ports may conflict. This is explained below.

[0070] For example, Table 2 shows the meanings of the control parameters stored in the registers of the ASM 24 .

[0071] Table 2

[0072] As can be seen, similar to Table 1, the above control parameters also define the functions of each bit from the perspective of the second group of ports. The first antenna port ANT1 is the primary transceiver port. When the first antenna port ANT1 outputs the first SRS signal SRS1 or the primary transmit signal PTX, bits [7:6] are set to 01 (connecting the first antenna port ANT1 to the transmit port TX). When the second antenna port ANT2 outputs the second SRS signal SRS2, bits [5:4] are set to 01 (connecting the second antenna port ANT2 to the transmit port TX), and bits [7:6] are set to 00 (disabling the first antenna port ANT1). When the third antenna port ANT3 outputs the third SRS signal SRS3, bits [3:2] are set to 01 (connecting the SRS output port SRSOUT to the transmit port TX), and bits [7:6] are set to 00 (disabling the first antenna port ANT1). In other words, transmitting RF signals involves controlling the first antenna port ANT1. When receiving the main receive signal PRX through the first antenna port ANT1, bits [7:6] must be set to 10 (connecting the first antenna port ANT1 to the first receive port RX1). In other words, receiving RF signals also involves controlling the first antenna port ANT1. Therefore, when switching between multiple channels, regardless of whether multiple antennas are switched, the first antenna port ANT1 must be adaptively configured. If the configuration is inappropriate, multiple channels may be connected to one antenna at the same time, or multiple antennas may be connected to one channel at the same time, resulting in a control logic conflict. Failure to decouple switching between different channels and switching between different antennas does not meet system requirements.

[0073] That is to say, although the RF front-end shown in Figures 4 and 5 does not have an SP2T switch, eliminating the insertion loss caused by the SP2T switch, which can improve the transmission efficiency of the transmitting channel and the receiving sensitivity of the receiving channel, since the first common node and the second common node do not overlap, when multiple channels occupy multiple antennas, the conduction between the two groups of ASM ports will cause conflicts.

[0074] An embodiment of the present application provides another ASM, which improves the ASM shown in Figures 4 and 5 and is applied to the RF front end shown in Figures 4 and 5. The first group of ports in the ASM is used to couple to multiple channels, and the second group of ports in the ASM is used to couple to multiple antennas, and the first group of ports is coupled to the second group of ports through a switching circuit. When multiple channels occupy multiple antennas, for switches in the switching circuit that may cause a control logic conflict between the conduction of the two groups of ports, a virtual common node is established for the ASM, and a register in the ASM configures a first parameter and a second parameter of the virtual common node, wherein the first parameter indicates which port in the first group of ports (i.e., the left port) is connected to the virtual common node, and the second parameter indicates which port in the second group of ports (i.e., the right port) is connected to the virtual common node. The control circuit implements a decoded phase AND operation of the first parameter and the second parameter to control the conduction of the above-mentioned switch, thereby connecting the ports in the first group of ports to the ports in the second group of ports. This is equivalent to connecting the ports in the first group of ports to the ports in the second group of ports through the virtual common node. That is, the virtual common node adds constraints to the conduction between the channel and the antenna, avoiding conflicts in the conduction between the two groups of ports of the ASM when multiple channels occupy multiple antennas.

[0075] Similarly, more virtual public nodes (for example, two virtual public nodes in total) may be added, and two ports in the first group of ports are connected to two ports in the second group of ports through the two virtual public nodes respectively.

[0076] This ASM can be equivalent to the ASM shown in Figures 2 and 3, with the addition of a single virtual SP2T switch as shown in Figure 6 (i.e., adding a first virtual common node TRX1). The control circuit implements a decoded phase AND operation of the first and second parameters, thereby realizing the series connection of the virtual SP2T (SP2T consisting of the transmit port TX, the first receive port RX1, and the first virtual common node TRX1) and the SP3T (SP3T consisting of the first antenna port ANT1, the second antenna port ANT2, the SRS output port SRSOUT, and the first virtual common node TRX1). Alternatively, two virtual SP2T switches can be added as shown in Figure 7 (i.e., adding a first virtual common node TRX1 and a second virtual common node TRX2). The ASM shown in Figure 6 uses the first antenna port ANT1 as the main transceiver port and is coupled to the left port via the first virtual common node TRX1. The first antenna port ANT1 and the second antenna port ANT2 of the ASM shown in Figure 7 are equivalent and can each function as a primary transceiver port. When the first antenna port ANT1 functions as the primary transceiver port, it is coupled to one of the first group of ports via the first virtual public node TRX1. When the second antenna port ANT2 functions as the primary transceiver port, it is coupled to one of the first group of ports via the second virtual public node TRX2. The second virtual public node TRX2 and the first virtual public node TRX1 are equivalent and can be interchanged. Both antenna ports coupled to these two virtual public nodes can function as primary transceiver ports, free from layout and routing restrictions and offering greater flexibility.

[0077] The actual structure of the ASM is described below.

[0078] As shown in Figure 8, the ASM includes a first group of ports 81 (i.e., the left-side ports described above), a second group of ports 82 (i.e., the right-side ports described above), a switch circuit 83, a control circuit 84, and a register 85. The number of ports in the first group of ports and the number of ports in the second group of ports are both greater than two. The first group of ports 81 is coupled to the second group of ports 82 via the switch circuit 83. The embodiments of the present application do not limit the uses of the first and second groups of ports. For example, the first group of ports 81 includes a transmit port TX, a first receive port RX1, a second receive port RX2, and an SRS input port SRSIN. The second group of ports 82 includes a first antenna port ANT1, a second antenna port ANT2, and an SRS output port SRSOUT. The transmit port TX is used to couple to a transmit channel, the first receive port RX1 and the second receive port RX2 are used to couple to two receive channels, respectively, the first antenna port ANT1 is used to couple to a first antenna (not shown in the figure), and the second antenna port ANT2 is used to couple to a second antenna (not shown in the figure). The SRS input port SRSIN is used to input SRS signals from other RF modules (not shown in the figure) of this communication device, and the SRS output port SRSOUT is used to output SRS signals to other RF modules (not shown in the figure) of this communication device. It should be noted that the ASM forwarding SRS signals from other RF modules and the ASM being occupied by the transmit channel or receive channel are two different operating modes and are mutually exclusive.

[0079] As shown in FIG8 , the switch circuit 83 includes a first switch S1 , a second switch S2 , a third switch S3 , a fourth switch S4 , a fifth switch S5 , a sixth switch S6 , and a seventh switch S7 .

[0080] The transmit port TX is coupled to the first antenna port ANT1 via a first switch S1, coupled to the second antenna port ANT2 via a fourth switch S4, and coupled to the SRS output port SRSOUT via a seventh switch S7. The first receive port RX1 is coupled to the first antenna port ANT1 via a second switch S2. The second receive port RX2 is coupled to the second antenna port ANT2 via a fifth switch S5. The SRS input port SRSIN is coupled to the first antenna port ANT1 via a third switch S3, and coupled to the second antenna port ANT2 via a sixth switch S6.

[0081] Register 85 is used to store control parameters for switch circuit 83. The control parameters include a first parameter and a second parameter of the virtual common node. The first parameter indicates which port in the first group of ports 81 is electrically conductive with the virtual common node, and the second parameter indicates which port in the second group of ports 82 is electrically conductive with the virtual common node. In other words, different decoding results of the first parameter represent different ports in the first group of ports, and different decoding results of the second parameter represent different ports in the second group of ports. Register 85 may include the two registers (register A and register B) shown in Tables 3 and 5, or may include a single register (register A) shown in Table 4.

[0082] The first and second parameters of the virtual common node are suitable for controlling switches in the switch circuit 83 that may cause control logic conflicts between the conduction between the two groups of ports. These switches can control the conduction of multiple switches in the first group of ports and multiple switches in the second group of ports. For example, in the description of Figures 4 and 5 above, it is mentioned that the transmit port TX can be connected to the first antenna port ANT1, the second antenna port ANT2, or the SRS output port SRSOUT, respectively, while the first antenna port ANT1 can be connected to the transmit port TX or the first receive port RX1, respectively. This may result in multiple channels occupying multiple antennas, and improper configuration will cause control logic conflicts. The switches involved in these conduction relationships are the first switch S1, the second switch S2, the fourth switch S4, and the seventh switch S7 in Figure 8. Therefore, the first and second parameters of the virtual common node can be configured for these switches, and the conduction and shutdown of these switches can be controlled based on the decoded and AND results of the first and second parameters of the virtual common node.

[0083] In addition to the first and second parameters of the virtual common node, the control parameters of the switch circuit 83 also include other parameters for controlling direct connection between one port in the first group of ports 81 and one port in the second group of ports 82 without passing through the virtual common node, namely the third and fourth parameters mentioned below.

[0084] The third and fourth parameters discussed below are applicable to controlling switches in the switch circuit 83 that do not cause control logic conflicts between the two groups of ports. For example, the ASM inputs SRS signals from other RF modules via the SRS input port SRSIN and transmits them via the first antenna port ANT1 or the second antenna port ANT2. This only involves the control of the third switch S3 and the sixth switch S6 in FIG8 , and there is no need to configure the first and second parameters of the virtual common node for these switches.

[0085] For example, Tables 3 to 5 show the control parameters stored in register 85 in ASM 24. Tables 3 and 4 are applied to a scenario with a single virtual public node (e.g., a first virtual public node), and the first and second parameters of the first virtual public node in Table 3 are located in two registers, while the first and second parameters of the first virtual public node in Table 4 are located in one register, to save hardware cost and reduce circuit board area. Table 5 is applied to a scenario with two virtual public nodes (e.g., a first virtual public node and a second virtual public node). Bits [7:6] of register A in Tables 3 to 5 represent the second parameter of the first virtual public node TRX1, bits [7:4] of register B in Tables 3 and 5, and bits [1:0] of register A in Table 4 represent the first parameter of the first virtual public node TRX1. Bits [5:4] of register A in Table 5 represent the second parameter of the second virtual public node TRX2, and bits [3:0] of register B in Table 5 represent the first parameter of the second virtual public node TRX2.

[0086] Table 3

[0087] Table 4

[0088] Table 5

[0089] The control circuit 84 is configured to control the switch circuit 83 to connect the ports in the first group of ports 81 to the ports in the second group of ports 82 based on the decoded result of the control parameter stored in the register. For example, the control circuit 84 controls the switch circuit 83 to connect the ports in the first group of ports 81 to the ports in the second group of ports 82 based on the decoded AND result of the first parameter and the second parameter of the first virtual public node, or based on the decoded AND result of the first parameter and the second parameter of the second virtual public node. Different decoding results of the first parameter indicate different ports in the first group of ports, and different decoding results of the second parameter indicate different ports in the second group of ports.

[0090] Taking the DSDA scenario as an example, as shown in Figure 6 and Table 3, assume that SIM card 1 and SIM card 2 time-share the same transmit channel. SIM card 1 and SIM card 2 have different receive channels. The first antenna port ANT1 is configured for both the receive and transmit channels of SIM card 1, while the second antenna port ANT2 is configured for both the receive and transmit channels of SIM card 2. During receive timeslots, receive channel 1 of SIM card 1 occupies the first receive port RX1 and the first antenna port ANT1. Specifically, bits [7:6] of register A are configured to 01, and bits [7:4] of register B are configured to 0010. Receive channel 2 of SIM card 2 occupies the second receive port RX2 and the second antenna port ANT2. Specifically, bits [5:4] of register A are configured to 01. When switching from a receive timeslot to a transmit timeslot, SIM card 2 preempts the transmit port TX and the second antenna port ANT2. Specifically, bits [7:6] of register A are configured from 01 to 10, and bits [7:4] of register B are configured from 0010 to 0001. Since the values ​​01 and 10 of the bit positions [7:6] of register A are mutually exclusive, and the values ​​0010 and 0001 of the bit positions [7:4] of register B are also mutually exclusive, there will be no situation where the first common node is simultaneously connected to the transmitting port TX and the first receiving port RX1, nor will there be a situation where the first common node is simultaneously connected to the first antenna port ANT1 and the second antenna port. This is equivalent to one port in the first group of ports only being connected to one port in the second group of ports, and there will be no conflict between the conduction of the two groups of ports of ASM. Therefore, the present invention is suitable for DSDA scenarios.

[0091] Taking the control parameters shown in Table 3 as an example, as shown in FIG9 , the control circuit 84 includes a first decoder D1 , a second decoder D2 , a third decoder D3 , a fourth decoder D4 , a first AND gate AND1 , a second AND gate AND2 , a third AND gate AND3 , and a fourth AND gate AND4 .

[0092] The input end of the first decoder D1 is used to input B[7:4] (bits [7:4] of register B, i.e., the first parameter of the first virtual public node TRX1); the input end of the second decoder D2 is used to input A[7:6] (bits [7:6] of register A, i.e., the second parameter of the first virtual public node TRX1); the input end of the third decoder D3 is used to input A[5:4] (bits [5:4] of register A, i.e., the third parameter); the input end of the fourth decoder D4 is used to input A[3:2] (bits [3:2] of register A, i.e., the fourth parameter).

[0093] The first output of the first decoder D1 (decoding B[7:4] to 0001) and the first output of the second decoder D2 (decoding A[7:6] to 01) are respectively coupled to the two inputs of the first AND gate AND1. The output of the first AND gate AND1 is used to control the on and off of the first switch S1 shown in Figure 8. When the first decoder D1 decodes B[7:4] to 0001 and the second decoder decodes A[7:6] to 01, the first switch S1 is turned on, connecting the transmit port TX to the first antenna port ANT1. Other decoding results of A[7:6] and B[7:4] will cause the first switch S1 to be turned off.

[0094] The second output of the first decoder D1 (decoding B[7:4] to 0010) and the first output of the second decoder D2 (decoding A[7:6] to 01) are coupled to the two inputs of a fourth AND gate AND4. The output of the fourth AND gate AND4 is used to control the on and off state of the second switch S2 shown in Figure 8. When the first decoder D1 decodes B[7:4] to 0010 and the second decoder decodes A[7:6] to 01, the second switch S2 turns on, connecting the first antenna port ANT1 to the first receive port RX1. Other decoding results for A[7:6] and B[7:4] cause the second switch S2 to turn off.

[0095] The first output of the first decoder D1 (decoding B[7:4] to 0001) and the second output of the second decoder D2 (decoding A[7:6] to 10) are respectively coupled to the two inputs of a second AND gate AND2. The output of the second AND gate AND2 is used to control the on and off of the fourth switch S4 shown in Figure 8. When the first decoder D1 decodes B[7:4] to 0001 and the second decoder decodes A[7:6] to 10, the fourth switch S4 turns on, connecting the transmit port TX to the second antenna port ANT2. Other decoding results for A[7:6] and B[7:4] cause the fourth switch S4 to turn off.

[0096] The third output of the second decoder D2 (decoding A[7:6] to obtain 11) is coupled to the two inputs of a third AND gate AND3. The output of the third AND gate AND3 is used to control the on / off state of the seventh switch S7 shown in Figure 8. When the second decoder decodes A[7:6] to obtain 11, the seventh switch S7 turns on, connecting the transmit port TX to the SRS output port SRSOUT. Other decoding results for A[7:6] cause the seventh switch S7 to turn off.

[0097] The third output of the third decoder D3 (decoding A[5:4] to 01) is used to control the on / off state of the fifth switch S5 shown in FIG8 . When the third decoder D3 decodes A[5:4] to 01, the fifth switch S5 turns on, connecting the second receive port RX2 to the second antenna port ANT2. Other decoding results for A[5:4] cause the fifth switch S5 to turn off.

[0098] The first output of the fourth decoder D4 (decoding A[3:2] to 01) is used to control the on / off switching of the third switch S3 shown in FIG8 , and the second output of the fourth decoder D4 (decoding A[3:2] to 10) is used to control the on / off switching of the sixth switch S6 shown in FIG8 . As shown in FIG11 , when the fourth decoder D4 decodes A[3:2] to 01, the third switch S3 is turned on, connecting the SRS input port SRSIN to the first antenna port ANT1, and the ASM 24 transmits the RF signals from the other RF modules through the first antenna port ANT1. As shown in FIG12 , when the fourth decoder D4 decodes A[3:2] to 10, the sixth switch S6 is turned on, connecting the SRS input port SRSIN to the second antenna port ANT2, and the ASM 24 transmits the RF signals from the other RF modules through the second antenna port ANT2. Other decoding results of A[3:2] will cause the third switch S3 and the sixth switch S6 to be turned off.

[0099] Optionally, taking the control parameters shown in Table 5 as an example, as shown in FIG10 , based on the control circuit 84 shown in FIG9 , the control circuit 84 further includes a fifth decoder D5, a fifth AND gate AND5, a sixth AND gate AND6, a seventh AND gate AND7, an eighth AND gate AND8, a first OR gate OR1, a second OR gate OR2, and a third OR gate OR3. The conditions for the two inputs of the OR gate are equivalent, as long as any one of the conditions is met.

[0100] The input end of the fifth decoder D5 is used to input B[3:0] (bits [3:0] of register B, i.e., the first parameter of the second virtual public node TRX2), and the input end of the third decoder D3 is used to input A[5:4] (bits [5:4] of register A, i.e., the second parameter of the second virtual public node TRX2).

[0101] The first output of the fifth decoder D5 (decoding B[3:0] to 0001) and the first output of the third decoder D3 (decoding A[5:4] to 01) are coupled to the two inputs of a fifth AND gate AND5, respectively. The output of the fifth AND gate AND5 and the output of the first AND gate AND1 are coupled to the two inputs of a first OR gate OR1, respectively. The output of the first OR gate OR1 is used to control the on and off state of the first switch S1 shown in FIG8. When the first decoder D1 decodes B[7:4] to 0001 and the second decoder decodes A[7:6] to 01, or when the fifth decoder D5 decodes B[3:0] to 0001 and the third decoder D3 decodes A[5:4] to 01, the first switch S1 is turned on, connecting the transmit port TX to the first antenna port ANT1. Other decoding results of A[7:6], B[7:4], A[5:4], and B[3:0] will cause the first switch S1 to be turned off.

[0102] The second output of the fifth decoder D5 (decoding B[3:0] to 0010) and the first output of the third decoder D3 (decoding A[5:4] to 01) are respectively coupled to the two inputs of an eighth AND gate AND8. The output of the eighth AND gate AND8 is used to control the on and off state of the fifth switch S5 shown in FIG8 . When the fifth decoder D5 decodes B[3:0] to 0010 and the third decoder D3 decodes A[5:4] to 01, the fifth switch S5 turns on, connecting the second antenna port ANT2 to the second receive port RX2. Other decoding results for A[5:4] and B[3:0] will cause the fifth switch S5 to turn off.

[0103] The first output of the fifth decoder D5 (decoding B[3:0] to obtain 0001) and the second output of the third decoder D3 (decoding A[5:4] to obtain 10) are respectively coupled to the two inputs of a sixth AND gate AND6. The output of the sixth AND gate AND6 and the output of the second AND gate AND2 are respectively coupled to the two inputs of a second OR gate OR2. The output of the second OR gate OR2 is used to control the on and off state of the fourth switch S4 shown in FIG8. When the first decoder D1 decodes B[7:4] to obtain 0001 and the second decoder decodes A[7:6] to obtain 10, or when the fifth decoder D5 decodes B[3:0] to obtain 0001 and the third decoder decodes A[5:4] to obtain 10, the fourth switch S4 is turned on, connecting the transmit port TX to the second antenna port ANT2. Other decoding results of A[7:6], B[7:4], A[5:4] and B[3:0] will cause the fourth switch S4 to be turned off.

[0104] The third output of the third decoder D3 (decoding A[5:4] to obtain 11) is coupled to the two inputs of the seventh AND gate AND7. The output of the seventh AND gate AND7 and the output of the third AND gate AND3 are respectively coupled to the two inputs of the third OR gate OR3. The output of the third OR gate OR3 is used to control the on and off of the seventh switch S7 shown in Figure 8. When the second decoder decodes A[7:6] to obtain 11, or when the third decoder D3 decodes A[5:4] to obtain 11, the seventh switch S7 is turned on, connecting the transmit port TX to the SRS output port SRSOUT. Other decoding results of A[7:6] and A[5:4] will cause the seventh switch S7 to be turned off.

[0105] For other contents of FIG10 , please refer to the above description of FIG9 , which will not be repeated here.

[0106] Taking the first antenna port ANT1 as the main transceiver port as an example, Table 6 shows how to configure the control parameters in the register so as to avoid control logic conflicts.

[0107] Table 6

[0108] In conjunction with Table 6, Figures 13 to 24 show the equivalent paths and actual paths in various scenarios. Among them, Figure 13 shows the equivalent path of the virtual public node of Scenario 1, and Figure 14 shows the actual path of Scenario 1. Figure 15 shows the equivalent path of the virtual public node of Scenario 2, and Figure 16 shows the actual path of Scenario 2. Figure 17 shows the equivalent path of the virtual public node of Scenario 3, and Figure 18 shows the actual path of Scenario 3. Figure 19 shows the equivalent path of the virtual public node of Scenario 4, and Figure 20 shows the actual path of Scenario 4. Figure 21 shows the equivalent path of the virtual public node of Scenario 5, and Figure 22 shows the actual path of Scenario 5. Figure 23 shows the equivalent path of the virtual public node of Scenario 6, and Figure 24 shows the actual path of Scenario 6. For the meaning of each scenario, please refer to the contents in Table 6.

[0109] It should be noted that although Figures 13 to 20 and scenarios 1 to 4 are described using two virtual public nodes as an example, they are also applicable to the case of one virtual public node.

[0110] The antenna switch module, radio frequency front end, and communication device provided by the embodiments of the present application establish a virtual common node in an ASM. The virtual common node is an intermediate node connecting a first group of ports to a second group of ports. A register in the ASM configures a first parameter and a second parameter of the virtual common node. The first parameter indicates which port in the first group of ports is connected to the virtual common node, and the first parameter is equivalent to controlling a first single-pole multi-throw switch between the first group of ports and the virtual common node; the second parameter indicates which port in the second group of ports is connected to the virtual common node, and the second parameter is equivalent to controlling a second single-pole multi-throw switch between the second group of ports and the virtual common node. A control circuit implements a phase AND operation after decoding the first and second parameters, which is equivalent to connecting the first and second single-pole multi-throw switches in series via the virtual common node, with the virtual common node serving as the only common node between the two virtual groups of ports. The result of the AND operation is used to control the switch circuit to connect the ports in the first group of ports to the ports in the second group of ports. This is equivalent to connecting the ports in the first group of ports to the ports in the second group of ports through the virtual common node. By independently decoupling the control logic of the two groups of ASM ports, conflicts between the two groups of ASM ports are avoided. Furthermore, because no physical switches are added, and instead the control logic of the switches in the ASM is constrained, insertion loss is not increased.

[0111] Those skilled in the art will appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0112] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and modules described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0113] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0114] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located on a single device or distributed across multiple devices. Some or all of the modules may be selected to achieve the purpose of the present embodiment as needed.

[0115] In addition, the functional modules in the various embodiments of the present application may be integrated into one device, or each module may exist physically separately, or two or more modules may be integrated into one device.

[0116] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0117] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An antenna switch module, It is characterized in that include: A first group of ports, a second group of ports, a control circuit, a switch circuit, and a register; the first group of ports is coupled to the second group of ports through the switch circuit; The first group of ports is used to couple to a plurality of channels, and the second group of ports is used to couple to a plurality of antennas; The register is used to store a first parameter and a second parameter of a first virtual public node, wherein the first parameter of the first virtual public node is used to indicate which port in the first group of ports is connected to the first virtual public node, and the second parameter of the first virtual public node is used to indicate which port in the second group of ports is connected to the first virtual public node; The control circuit is used for controlling the switch circuit to connect the ports in the first group of ports to the ports in the second group of ports according to the first parameter and the second parameter of the first virtual public node.

2. The antenna switch module according to claim 1, It is characterized in that The multiple channels include a transmit channel and a first receive channel, the multiple antennas include a first antenna and a second antenna, the first group of ports include a transmit port and a first receive port, the transmit port is used to couple to the transmit channel, the first receive port is used to couple to the first receive channel, the second group of ports includes a first antenna port, a second antenna port and a sounding reference signal SRS output port, the first antenna port is used to couple to the first antenna, the second antenna port is used to couple to the second antenna, and the SRS output port is used to couple to other radio frequency modules; The switch circuit comprises: a first switch, a second switch, a fourth switch and a seventh switch; The transmit port is coupled to the first antenna port through the first switch, the transmit port is coupled to the second antenna port through the fourth switch, the transmit port is coupled to the SRS output port through the seventh switch; the first receive port is coupled to the first antenna port through the second switch.

3. The antenna switch module according to claim 2, It is characterized in that The control circuit is specifically used to control the switch circuit to connect the ports in the first group of ports with the ports in the second group of ports according to the result of the AND operation between the first parameter and the second parameter of the first virtual public node after decoding.

4. The antenna switch module according to claim 3, It is characterized in that The control circuit includes a first decoder, a second decoder, a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate; the input end of the first decoder is used to input a first parameter of the first virtual public node; the input end of the second decoder is used to input a second parameter of the first virtual public node; The first output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to two input terminals of the first AND gate, and the output terminal of the first AND gate is used to control the on and off of the first switch; The second output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to two input terminals of the fourth AND gate, and the output terminal of the fourth AND gate is used to control the on and off of the second switch; The first output terminal of the first decoder and the second output terminal of the second decoder are respectively coupled to two input terminals of the second AND gate, and the output terminal of the second AND gate is used to control the on and off of the fourth switch; The third output terminal of the second decoder is coupled to two input terminals of the third AND gate, and the output terminal of the third AND gate is used to control the on and off of the seventh switch.

5. The antenna switch module according to claim 4, It is characterized in that The multiple channels further include a second receiving channel, the first group of ports further include a second receiving port, the second receiving port is used to couple to the second receiving channel, the switching circuit further includes a fifth switch, and the second receiving port is coupled to the second antenna port through the fifth switch.

6. The antenna switch module according to claim 5, It is characterized in that The control circuit further includes a third decoder, an input end of the third decoder is used to input a third parameter, and an output end of the third decoder is used to control the on and off of the fifth switch.

7. The antenna switch module according to claim 1, It is characterized in that The register is further used to store a first parameter and a second parameter of a second virtual public node, wherein the first parameter of the second virtual public node is used to indicate which port in the first group of ports is connected to the second virtual public node, and the second parameter of the second virtual public node is used to indicate which port in the second group of ports is connected to the second virtual public node; The control circuit is used to control the switch circuit to connect the ports in the first group of ports to the ports in the second group of ports according to the result of the AND operation of the first parameter and the second parameter of the first virtual public node after decoding, or according to the result of the AND operation of the first parameter and the second parameter of the second virtual public node after decoding.

8. The antenna switch module according to claim 7, It is characterized in that The multiple channels include a transmitting channel, a first receiving channel, and a second receiving channel, and the multiple antennas include a first antenna and a second antenna; the first group of ports includes a transmitting port, a first receiving port, and a second receiving port, the transmitting port is used to couple to the transmitting channel, the first receiving port is used to couple to the first receiving channel, and the second receiving port is used to couple to the second receiving channel; The second group of ports includes a first antenna port, a second antenna port and an SRS output port, the first antenna port is used to couple to the first antenna, the second antenna port is used to couple to the second antenna, and the SRS output port is used to couple to other radio frequency modules; The switch circuit includes a first switch, a second switch, a fourth switch, a fifth switch and a seventh switch; The transmit port is coupled to the first antenna port through the first switch, the transmit port is coupled to the second antenna port through the fourth switch, and the transmit port is coupled to the SRS output port through the seventh switch; The first receiving port is coupled to the first antenna port via the second switch; The second receiving port is coupled to the second antenna port through the fifth switch.

9. The antenna switch module according to claim 8, It is characterized in that The control circuit includes a first decoder, a second decoder, a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a third decoder, a fifth decoder, a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a first OR gate, a second OR gate and a third OR gate; an input end of the first decoder is used to input a first parameter of the first virtual public node; an input end of the second decoder is used to input a second parameter of the first virtual public node; an input end of the fifth decoder is used to input a first parameter of the second virtual public node; an input end of the third decoder is used to input a second parameter of the second virtual public node; The first output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to two input terminals of the first AND gate, and the output terminal of the first AND gate is used to control the on and off of the first switch; The second output terminal of the first decoder and the first output terminal of the second decoder are respectively coupled to two input terminals of the fourth AND gate, and the output terminal of the fourth AND gate is used to control the on and off of the second switch; The first output terminal of the first decoder and the second output terminal of the second decoder are respectively coupled to two input terminals of the second AND gate, and the output terminal of the second AND gate is used to control the on and off of the fourth switch; The third output terminal of the second decoder is coupled to two input terminals of the third AND gate, and the output terminal of the third AND gate is used to control the on and off of the seventh switch; The first output end of the fifth decoder and the first output end of the third decoder are respectively coupled to the two input ends of the fifth AND gate, the output end of the fifth AND gate and the output end of the first AND gate are respectively coupled to the two input ends of the first OR gate, and the output end of the first OR gate is used to control the on and off of the first switch; The second output terminal of the fifth decoder and the first output terminal of the third decoder are respectively coupled to two input terminals of the eighth AND gate, and the output terminal of the eighth AND gate is used to control the on and off of the fifth switch; The first output end of the fifth decoder and the second output end of the third decoder are respectively coupled to the two input ends of the sixth AND gate, the output end of the sixth AND gate and the output end of the second AND gate are respectively coupled to the two input ends of the second OR gate, and the output end of the second OR gate is used to control the on and off of the fourth switch; The third output end of the third decoder is coupled to the two input ends of the seventh AND gate, the output end of the seventh AND gate and the output end of the third AND gate are respectively coupled to the two input ends of the third OR gate, and the output end of the third OR gate is used to control the on and off of the seventh switch.

10. The antenna switch module according to any one of claims 2 to 9, It is characterized in that The first group of ports also includes an SRS input port, and the SRS input port is used to couple to other RF modules. The switch circuit also includes: a third switch and a sixth switch; The SRS input port is coupled to the first antenna port through the third switch, and the SRS input port is coupled to the second antenna port through the sixth switch.

11. The antenna switch module according to claim 10, It is characterized in that The control circuit also includes a fourth decoder, an input end of the fourth decoder is used to input a fourth parameter, a first output end of the fourth decoder is used to control the on and off of the third switch, and a second output end of the fourth decoder is used to control the on and off of the sixth switch.

12. The antenna switch module according to any one of claims 1 to 11, It is characterized in that The first parameter and the second parameter of the same virtual public node are stored in one or two registers.

13. A radio frequency front end, It is characterized in that It includes a power amplifier, a first linear amplifier, a second linear amplifier, a first filter, a second filter, a third filter and an antenna switch module as described in any one of claims 1 to 12, wherein the power amplifier is coupled to the transmitting port of the antenna switch module through the first filter, the first linear amplifier is coupled to the first receiving port of the antenna switch module through the second filter, and the second linear amplifier is coupled to the second receiving port of the antenna switch module through the third filter.

14. A communication device, It is characterized in that The invention comprises a radio frequency front end as claimed in claim 13 and a plurality of antennas, wherein the radio frequency front end is coupled to the plurality of antennas.

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