Silicon wafer multi-wire cutting method based on steel wire operation cycle and loop ratio optimization

Abstract

The invention provides a silicon wafer multi-wire cutting method based on steel wire operation cycle and loop ratio optimization, and relates to the technical field of semiconductor wafer manufacturing, and the silicon wafer multi-wire cutting method comprises the following steps: dividing a cutting process into three stages of a cutting initial stage, a cutting middle stage and a cutting final stage according to cutting time; cutting is conducted according to first preset steel wire parameters in the initial cutting stage, so that the cutting fluid permeation efficiency is improved; cutting according to a second preset steel wire parameter in the middle stage of cutting so as to balance the wire abrasion, the edge stress of the silicon wafer and the amount of the cutting liquid entering the cutting seam of the crystal bar; cutting is conducted according to third preset steel wire parameters at the last stage of cutting, so that the wire breaking risk is reduced; wherein the first preset steel wire parameter, the second preset steel wire parameter and the third preset steel wire parameter respectively comprise a wire operation period and a return wire ratio. According to the scheme, proflie fluctuation of the silicon wafer can be reduced, and the surface appearance of the cut silicon wafer is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor wafer manufacturing, and particularly relates to a multi-wire cutting method for silicon wafers based on optimizing the wire running cycle and return wire ratio. Background Art

[0002] As the core substrate of semiconductor devices and photovoltaic cells, the processing quality of silicon wafers directly affects the performance of chips and the conversion efficiency of solar cells. With the development of the photovoltaic industry towards higher efficiency and lower cost, and the evolution of semiconductor devices towards miniaturization and high integration, the demand for thinning and high-precision cutting of silicon wafers is becoming increasingly urgent. With the advantages of high efficiency, low loss, and batch production, multi-wire cutting technology has become the mainstream process for silicon wafer cutting and is widely used in the processing of single-crystalline silicon, polycrystalline silicon, and third-generation semiconductor materials.

[0003] When cutting silicon wafers, the cutting accuracy and surface quality of the silicon wafers directly determine the yield of subsequent processes and the performance of end products. For example, uneven thickness of the silicon wafer will easily cause fragmentation during battery coating and welding, and surface defects will reduce the light absorption efficiency; if the flatness of the silicon wafer is insufficient, it will cause lithography alignment deviation, and microcracks will expand during chip packaging, resulting in failure; moreover, low-quality silicon wafers require additional polishing or rework, increasing the manufacturing cost and hindering the process of photovoltaic parity and the demand for semiconductor cost reduction.

[0004] However, when the current wire cutting machine cuts the ingot with a wire mesh of steel wire moving at high speed reciprocally and carrying slurry, there are problems of insufficient penetration of the cutting fluid or improper wire speed matching, which in turn leads to relatively abnormal fluctuations in the profile of the silicon wafer and poor morphology of the cut silicon wafer. Summary of the Invention

[0005] In view of this, in order to address the above deficiencies, it is necessary to propose a multi-wire cutting method for silicon wafers based on optimizing the wire running cycle and return wire ratio to reduce the profile fluctuations of the silicon wafers and improve the surface morphology of the cut silicon wafers.

[0006] The present invention provides a multi-wire cutting method for silicon wafers based on optimizing the wire running cycle and return wire ratio, including: dividing the cutting process into three stages: the initial cutting stage, the middle cutting stage, and the final cutting stage according to the cutting time; cutting according to the first preset wire parameters in the initial cutting stage to improve the penetration efficiency of the cutting fluid; cutting according to the second preset wire parameters in the middle cutting stage to balance wire wear, silicon wafer edge stress, and the amount of cutting fluid entering the cutting seam of the ingot; cutting according to the third preset wire parameters in the final cutting stage to reduce the risk of wire breakage; wherein, the first preset wire parameters, the second preset wire parameters, and the third preset wire parameters all include the wire running cycle and the return wire ratio.

[0007] Preferably, for a 12-inch silicon wafer, the initial cutting stage corresponds to a cutting time of 0 - 8 hours, the middle cutting stage corresponds to a cutting time of 8 - 16 hours, and the final cutting stage corresponds to a cutting time of 16 - 20 hours.

[0008] Preferably, the wire running cycle corresponding to the first preset wire parameters is 70 - 190 seconds, and the return wire ratio is 1.3 - 1.7:1; the wire running cycle corresponding to the second preset wire parameters is 110 - 230 seconds, and the return wire ratio is 1.4 - 2:1; the wire running cycle corresponding to the third preset wire parameters is 70 - 190 seconds, and the return wire ratio is 1.1 - 1.7:1.

[0009] Preferably, the wire running cycle corresponding to the first preset wire parameters is 130 seconds, and the return wire ratio is 1.5; the wire running cycle corresponding to the second preset wire parameters is 170 seconds, and the return wire ratio is 1.7; the wire running cycle corresponding to the third preset wire parameters is 130 seconds, and the return wire ratio is 1.4.

[0010] Preferably, the wire diameter of the wire is 160 ± 5 microns.

[0011] Preferably, the initial tension of the wire is 30 ± 2 N.

[0012] Preferably, the flow rate of the cutting fluid during the cutting process is 90 ± 2 L / min.

[0013] Preferably, the wire usage is 90 - 100 km.

[0014] Preferably, the wire speed of the wire is 12 ± 0.1 m / s, and the acceleration is 3 ± 0.2 m / s 2 。

[0015] Preferably, after the cutting of the previous batch of silicon wafers is completed, the thickness of the cut silicon wafers and the wear degree of the wire are detected, and the return wire ratio is reduced when the wire wears faster.

[0016] As can be seen from the above technical solutions, in the multi-wire cutting method for silicon wafers based on the optimization of the running cycle and return wire ratio of the steel wire, it is considered to divide the cutting process into three stages: the initial cutting stage, the middle cutting stage, and the final cutting stage according to the cutting time. Then, at the initial cutting stage, cutting is performed according to the first preset steel wire parameters to improve the penetration efficiency of the cutting fluid. At the middle cutting stage, cutting is performed according to the second preset steel wire parameters to balance wire wear, the edge stress of the silicon wafer, and the amount of cutting fluid entering the cutting seam of the ingot. Further, at the final cutting stage, cutting is performed according to the third preset steel wire parameters to reduce the risk of wire breakage. Compared with the traditional wire cutting method that uses a single fixed return wire ratio, this solution performs cutting control on the three stages respectively by using the corresponding running cycle and return wire ratio of the steel wire, which can reduce the profile fluctuation of the silicon wafer, thereby achieving the purpose of improving the surface morphology of the cut silicon wafer. Moreover, this solution takes into account the effects of both the return wire ratio and the wire running cycle on improving the silicon wafer morphology, and can improve the silicon wafer morphology through the synergistic effect of the return wire ratio and the wire running cycle, while also being able to improve the service life of the steel wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the silicon wafer morphology diagram obtained based on the comparative example.

[0018] Figure 2 is the silicon wafer morphology diagram obtained based on Example 1.

[0019] Figure 3 is the silicon wafer morphology diagram obtained based on Example 2.

[0020] Figure 4 is the silicon wafer morphology diagram obtained based on Example 3.

[0021] Figure 5 is the silicon wafer morphology diagram obtained based on Example 4.

[0022] Figure 6 is the silicon wafer morphology diagram obtained based on Example 5.

[0023] Figure 7 is the silicon wafer morphology diagram obtained based on Example 6.

[0024] Figure 8 is the silicon wafer morphology diagram obtained based on Example 7.

[0025] Figure 9 is the silicon wafer morphology diagram obtained based on Example 8.

[0026] Figure 10 is the silicon wafer morphology diagram obtained based on Example 9.

[0027] Figure 11 is the silicon wafer morphology diagram obtained based on Example 10.

[0028] Figure 12 It is the topographic map of the silicon wafer obtained based on Example 11.

[0029] Figure 13 It is the topographic map of the silicon wafer obtained based on Example 12.

[0030] Figure 14 It is the topographic map of the silicon wafer obtained based on Example 13. Detailed implementation manners

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other accompanying drawings can be obtained based on these drawings without creative efforts.

[0032] For the wire running cycle WRC, it refers to the sum of the forward movement time and the reverse movement time of the wire. For the return wire ratio RR, it refers to the ratio of the forward movement length of the wire to the reverse movement length of the wire. In the existing multi-wire cutting solutions, the wire running cycle and the return wire ratio are usually optimized independently. For example, a fixed return wire ratio of 1:0.8 is adopted to reduce the wire vibration; or the wire running cycle is shortened to reduce the risk of wire breakage and the change in cutting ability caused by the frequent acceleration and deceleration of the steel wire. However, the synergistic effect of the return wire ratio and the wire running cycle on the silicon wafer topography is not considered, resulting in it being difficult to balance the cutting quality and the wire life. Accordingly, this solution provides a multi-wire cutting method for silicon wafers based on the optimization of the steel wire running cycle and the return wire ratio, including: dividing the cutting process into three stages: the initial cutting stage, the middle cutting stage, and the final cutting stage according to the cutting time; performing cutting according to the first preset steel wire parameters in the initial cutting stage to improve the penetration efficiency of the cutting fluid; performing cutting according to the second preset steel wire parameters in the middle cutting stage to balance the wire wear, the silicon wafer edge stress, and the amount of cutting fluid entering the cutting seam of the ingot; performing cutting according to the third preset steel wire parameters in the final cutting stage to reduce the risk of wire breakage; wherein, the first preset steel wire parameters, the second preset steel wire parameters, and the third preset steel wire parameters all include the wire running cycle and the return wire ratio.

[0033] In this embodiment, the cutting process is considered to be divided into three stages: the initial cutting stage, the middle cutting stage, and the final cutting stage according to the cutting time. Then, at the initial cutting stage, cutting is performed according to the first preset wire parameters to improve the penetration efficiency of the cutting fluid. At the middle cutting stage, cutting is performed according to the second preset wire parameters to balance wire wear, silicon wafer edge stress, and the amount of cutting fluid entering the cutting seam of the ingot. Further, at the final cutting stage, cutting is performed according to the third preset wire parameters to reduce the risk of wire breakage. Compared with the traditional wire cutting scheme that uses a single fixed return wire ratio, this scheme controls the cutting by using the corresponding wire running cycle and return wire ratio for each of the three stages, which can reduce the profile fluctuation of the silicon wafer, thereby achieving the purpose of improving the surface morphology of the cut silicon wafer. Moreover, this scheme takes into account the effects of both the return wire ratio and the wire running cycle on improving the silicon wafer morphology, can improve the silicon wafer morphology through the synergistic effect of the return wire ratio and the wire running cycle, and can also extend the service life of the wire.

[0034] Using the cutting method provided by this scheme, the average value of warp-bf of the cut silicon wafer is less than 5 microns, the total thickness variation (TTV) is no more than 10 microns, the wire consumption is reduced by 50% compared with the traditional fixed scheme, and the cutting cost is reduced by 10%.

[0035] When dividing the cutting stage in this embodiment, it is considered to be divided according to the cutting time. For example, for a 12-inch silicon wafer, the initial cutting stage corresponds to a cutting time of 0 - 8 hours, the middle cutting stage corresponds to a cutting time of 8 - 16 hours, and the final cutting stage corresponds to a cutting time of 16 - 20 hours. Of course, for silicon wafers of different sizes, they can also be divided according to the cutting time in the same way. The division standard can be based on manual experience or according to a certain proportion of the total cutting time. For example, the total cutting time is divided into the initial cutting stage, the middle cutting stage, and the final cutting stage according to a ratio of 2:2:1.

[0036] In one embodiment, at the initial cutting stage of 0 - 8 hours, the wire running cycle corresponding to the first preset wire parameters can be 70 - 190 seconds, and the return wire ratio can be 1.3 - 1.7:1. In this way, the penetration rate of the cutting fluid can be improved by extending the forward stroke of the wire; at the middle cutting stage of 8 - 16 hours, the wire running cycle corresponding to the second preset wire parameters can be 110 - 230 seconds, and the return wire ratio can be 1.4 - 2:1. In this way, the wire wear, silicon wafer edge stress, and the amount of mortar entering the cutting seam of the ingot can be balanced; at the final cutting stage of 16 - 20 hours, the wire running cycle corresponding to the third preset wire parameters can be 70 - 190 seconds, and the return wire ratio can be 1.1 - 1.7:1. In this way, the risk of wire breakage can be reduced by shortening the stroke.

[0037] In a more optimal embodiment, the wire running cycle corresponding to the first preset wire parameters is 130 seconds, and the wire return ratio is 1.5; the wire running cycle corresponding to the second preset wire parameters is 170 seconds, and the wire return ratio is 1.7; the wire running cycle corresponding to the third preset wire parameters is 130 seconds, and the wire return ratio is 1.4.

[0038] In one embodiment, the wire diameter of the wire is 160 ± 5 microns, the initial tension of the wire is 30 ± 2 N, the flow rate of the cutting fluid during the cutting process is 90 ± 2 L / min, the wire usage is 90 - 100 km, the wire speed of the wire is 12 ± 0.1 m / s, and the acceleration is 3 ± 0.2 m / s 2 。

[0039] In one embodiment, in order to further improve the quality of the silicon wafers after cutting, it is considered to detect the thickness of the cut silicon wafers and the wear degree of the wire after the cutting of the previous batch of silicon wafers is completed, and reduce the wire return ratio when the wire wears faster for the cutting of the next batch of silicon wafers.

[0040] The following further illustrates the effects of the present solution with each embodiment.

[0041] The comparative example adopts single-stage constant parameter control, and each embodiment adopts three-stage control in the initial cutting stage, the middle cutting stage, and the final cutting stage. The ingot parameters and cutting conditions of each comparative example and embodiment are the same, specifically: Ingot parameters: semiconductor-grade single-crystal silicon, with a diameter of 301.5 mm and a length of 430 mm; Cutting conditions: wire diameter is 160 microns, initial tension is 30 N, slurry flow rate is 90 L / min, the variable condition of the frame temperature is 22.5 - 23 °C, the wire speed of the wire is 12 m / s, and the acceleration is 3 m / s 2 。

[0042] Comparative example: The parameters are constant throughout the cutting process, the adopted wire return ratio is 1.8:1, and the wire running cycle is 130 s; Embodiment 1: The wire return ratio in the initial cutting stage is 1.5:1, and the wire running cycle is 130 s; the wire return ratio in the middle cutting stage is 1.7:1, and the wire running cycle is 170 s; the wire return ratio in the final cutting stage is 1.4:1, and the wire running cycle is 130 s; Embodiment 2: The wire return ratio in the initial cutting stage is 1.3:1, and the wire running cycle is 130 s; the wire return ratio in the middle cutting stage is 1.7:1, and the wire running cycle is 170 s; the wire return ratio in the final cutting stage is 1.4:1, and the wire running cycle is 130 s; Example 3: The loop ratio at the initial stage of cutting is 1.7:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 4: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 2:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 5: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.4:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 6: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.1:1, and the wire running period is 130 s; Example 7: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.7:1, and the wire running period is 130 s; Example 8: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 70 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 9: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 190 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 10: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 110 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 11: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 230 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 130 s; Example 12: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running period is 130 s; the loop ratio in the middle stage of cutting is 1.7:1, and the wire running period is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running period is 70 s; Example 13: The loop ratio at the initial stage of cutting is 1.5:1, and the wire running cycle is 130 s; the loop ratio at the middle stage of cutting is 1.7:1, and the wire running cycle is 170 s; the loop ratio at the final stage of cutting is 1.4:1, and the wire running cycle is 190 s; As Figures 1-14 are the silicon wafer morphology diagrams corresponding to the comparative example and Examples 1-13 respectively. The abscissa of the silicon wafer morphology diagram is the cutting amount, with the unit of mm, and the ordinate is the profile value, that is, the value obtained by dividing the thickness of the silicon wafer by 2. The results in each figure are the results obtained by sampling every 25 wafers in the silicon wafers obtained under the corresponding conditions.

[0043] As Figure 1 shown, the profile value of the silicon wafer obtained by the traditional solution fluctuates greatly, while for each embodiment provided by this solution, the profile fluctuation of the silicon wafer is significantly reduced. Therefore, adopting this solution can effectively improve the morphology of the surface of the cut silicon wafer, especially in Example 1 (see Figure 2 ), whose profile value is maintained between 435-438, and the fluctuation of the profile value is significantly reduced, which greatly improves the appearance morphology of the silicon wafer.

[0044] By analyzing Examples 1 to 7 (see Figures 2-8 ), it can be known that adopting a loop ratio of 1.5:1 at the initial stage of cutting, a loop ratio of 1.7:1 at the middle stage of cutting, and a loop ratio of 1.4:1 at the final stage of cutting can obtain better profile values. For example, by comparing Example 1, Example 2, and Example 3, it can be seen that further increasing or further decreasing the loop ratio at the initial stage of cutting will result in greater fluctuations in the profile value. Similarly, by comparing Example 1, Example 4, and Example 5, it can be seen that further increasing or further decreasing the loop ratio at the middle stage of cutting will result in greater fluctuations in the profile value. Similarly, by comparing Example 1, Example 6, and Example 7, it can be seen that further increasing or further decreasing the loop ratio at the final stage of cutting will result in greater fluctuations in the profile value.

[0045] By analyzing Example 1 and Examples 8-13 (see Figure 2 and 9As can be seen from (0)-14), a wire running cycle of 130 seconds in the initial stage of cutting, a wire running cycle of 170 seconds in the middle stage of cutting, and a wire running cycle of 130 seconds in the final stage of cutting can obtain a better profile value with less fluctuation of the profile value. As can be seen by comparing Example 1, Example 8, and Example 9, further increasing or decreasing the wire running cycle in the initial stage of cutting will result in greater fluctuation of the profile value. Similarly, as can be seen by comparing Example 1, Example 10, and Example 11, further increasing or decreasing the wire running cycle in the middle stage of cutting will result in greater fluctuation of the profile value. Similarly, as can be seen by comparing Example 1, Example 12, and Example 13, further increasing or decreasing the wire running cycle in the final stage of cutting will result in greater fluctuation of the profile value.

[0046] In summary, neither simply adjusting the loop-back ratio nor simply adjusting the wire running cycle can achieve the optimal adjustment effect. There is a synergistic relationship between the adjustment of the loop-back ratio and the wire running cycle. Only by synergistically adjusting the loop-back ratio and the wire running cycle through this solution can the fluctuation of the profile be significantly reduced and the morphology of the silicon wafer be effectively improved.

[0047] The modules or units in the device of the embodiment of the present invention can be combined, divided, and deleted according to actual needs. The above-disclosed is only the preferred embodiment of the present invention. Of course, it cannot be used to limit the scope of the rights of the present invention. Those of ordinary skill in the art can understand the entire or part of the process of implementing the above embodiments, and the equivalent changes made according to the claims of the present invention still fall within the scope covered by the invention.

Claims

1. A multi-wire cutting method for silicon wafers based on optimizing the running cycle and return wire ratio of steel wires, characterized in that, Including: Dividing the cutting process into three stages: the initial cutting stage, the middle cutting stage, and the final cutting stage according to the cutting time; Cutting according to the first preset wire parameters in the initial cutting stage to improve the penetration efficiency of the cutting fluid; Cutting according to the second preset wire parameters in the middle cutting stage to balance wire wear, silicon wafer edge stress, and the amount of cutting fluid entering the cutting seam of the ingot; Cutting according to the third preset wire parameters in the final cutting stage to reduce the risk of wire breakage; wherein, the first preset wire parameters, the second preset wire parameters, and the third preset wire parameters all include the wire running cycle and the return wire ratio.

2. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 1, wherein For 12-inch silicon wafers, the initial cutting stage corresponds to a cutting time of 0 - 8 hours, the middle cutting stage corresponds to a cutting time of 8 - 16 hours, and the final cutting stage corresponds to a cutting time of 16 - 20 hours.

3. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop-back ratio of steel wires according to claim 2, wherein, The wire running cycle corresponding to the first preset wire parameters is 70 - 190 seconds, and the return wire ratio is 1.3 - 1.7:1; the wire running cycle corresponding to the second preset wire parameters is 110 - 230 seconds, and the return wire ratio is 1.4 - 2:1; the wire running cycle corresponding to the third preset wire parameters is 70 - 190 seconds, and the return wire ratio is 1.1 - 1.7:

1.

4. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 3, characterized in that, The wire running cycle corresponding to the first preset wire parameters is 130 seconds, and the return wire ratio is 1.5; the wire running cycle corresponding to the second preset wire parameters is 170 seconds, and the return wire ratio is 1.7; the wire running cycle corresponding to the third preset wire parameters is 130 seconds, and the return wire ratio is 1.

4.

5. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 1, characterized in that, The wire diameter of the wire is 160 ± 5 microns.

6. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 1, characterized in that, The initial tension of the wire is 30 ± 2N.

7. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 1, wherein The flow rate of the cutting fluid during the cutting process is 90 ± 2L / min.

8. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop-back ratio of steel wires according to claim 1, wherein The wire usage is 90 - 100km.

9. The multi-wire cutting method for silicon wafers optimized based on the running cycle and loop ratio of steel wires according to claim 1, characterized in that The linear velocity of the steel wire is 12 ± 0.1 m / s, and the acceleration is 3 ± 0.2 m / s 2 .

10. The multi-wire cutting method for silicon wafers optimized based on the running cycle and return wire ratio of steel wires according to claim 1, wherein, After the cutting of the previous batch of silicon wafers is completed, detect the thickness of the cut silicon wafers and the wear degree of the wire, and reduce the return wire ratio when the wire wears faster.

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