Silicon carbide wafer and method for forming same
By combining potassium hydroxide etching and photoexcitation, the temperature gradient of silicon carbide crystal growth is controlled, and the problem of incomplete defect analysis of silicon carbide wafers in the prior art is solved, and the chip quality and yield are improved.
Patent Information
- Application Number
- CN202510011256.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-01-10
- Filing Date
- 2025-01-03
- Publication Date
- 2025-07-11
AI Technical Summary
In the prior art, it is difficult to comprehensively analyze defects such as through spiral difference rows (TSD), through edge difference rows (TED) and base surface difference rows (BPD) in silicon carbide crystals, which affect the quality and yield of wafers.
By combining potassium hydroxide (KOH) etching and photoluminescence detection, the base surface difference row (BPD) and base surface difference row (PL-BPD) density of silicon carbide wafers were analyzed respectively, and the axial and radial temperature gradients of silicon carbide crystal growth were controlled to form low-defect silicon carbide wafers.
A more comprehensive quality analysis of silicon carbide wafers is achieved, the defect density of base surface difference rows and through spiral difference rows is reduced, and the geometric yield and epitaxial quality of the wafer are improved.
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Figure CN120291210A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a silicon carbide wafer, and more particularly to a silicon carbide wafer and a method for forming the same. Background Art
[0002] Silicon carbide (SiC) is a wide-band-gap semiconductor material. Silicon carbide has many remarkable physical properties, making it a major component for high-power, high-temperature, and high-frequency electronics today.
[0003] The crystal growth of silicon carbide is not easy, and defects will seriously affect the performance of silicon carbide components. In the prior art, some of the main defects in silicon carbide (SiC) include threading screw dislocations (TSD), threading edge dislocations (TED), and basal plane dislocations (BPD) detected by etching methods. However, only considering the defects of TSD, TED, and BPD cannot fully obtain good quality, which will in turn affect the yield.
[0004] In addition to considering TSD, TED, and BPD, how to comprehensively analyze the quality of silicon carbide crystals and wafers is an urgent problem to be solved at present. Summary of the Invention
[0005] The present invention provides a silicon carbide wafer and a method for forming the same. By further considering the density of basal plane dislocations (PL-BPD) detected by photoluminescence, a more comprehensive quality analysis of silicon carbide crystals and wafers can be provided.
[0006] The silicon carbide wafer of the present invention has a seed end and a round top end opposite to the seed end. In the silicon carbide wafer, the density of basal plane dislocations (BPD) detected by potassium hydroxide (KOH) etching is less than 550 / cm at both the seed end and the round top end 2 , and the density of basal plane dislocations (PL-BPD) detected by photoluminescence is less than 2000 / cm at both the seed end and the round top end 2 .
[0007] In some embodiments, for the basal plane dislocation (BPD) density detected by the potassium hydroxide (KOH) etching method, the difference ratio D between the first basal plane dislocation density BPD1 at the seed end and the second basal plane dislocation density BPD2 at the circular top end needs to satisfy the following formula (1):
[0008] .
[0009] In some embodiments, for the basal plane dislocation (PL-BPD) density detected by the photoluminescence method, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the circular top end needs to satisfy the following formula (2):
[0010] .
[0011] In some embodiments, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the circular top end is 14% or less.
[0012] In some embodiments, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the circular top end is 12% or less.
[0013] In some embodiments, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the circular top end is 10% or less.
[0014] In some embodiments, the basal plane dislocation (BPD) density detected by the potassium hydroxide (KOH) etching method is less than 200 per cm at both the seed end and the circular top end 2 .
[0015] In some embodiments, the basal plane dislocation (PL-BPD) density detected by the photoluminescence method is less than 1000 per cm at both the seed end and the circular top end 2 .
[0016] In some embodiments, the wafer diameter of the silicon carbide wafer is 150 mm, 200 mm, or 300 mm.
[0017] In some embodiments, the threading screw dislocation (TSD) density of the silicon carbide wafer is 5 per cm 2 or less, the basal stacking fault (BSF) density is 5 per wafer or less, and the stacking fault (SF) density is 5 per wafer or less.
[0018] In some embodiments, the warp of the silicon carbide wafer is less than 40 µm, the bow is in the range of + / - 20 µm, and the triangle defect density is less than 0.1 per cm 2 .
[0019] A method for forming a silicon carbide wafer provided by the present invention includes the following steps. Provide a raw material containing carbon and silicon elements and a seed crystal above the raw material in a reactor. Perform a silicon carbide crystal growth process, wherein the growth process includes heating the reactor and the raw material to form a silicon carbide crystal on the seed crystal, and in the growth process, the axial temperature gradient (ΔTz) of the silicon carbide crystal is controlled within the range of 20 °C / cm to 150 °C / cm, and the radial temperature gradient (ΔTx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 100 °C / cm. Slice and polish the silicon carbide crystal to obtain a silicon carbide wafer.
[0020] In some embodiments, in the growth process, the axial temperature gradient (ΔTz) of the silicon carbide crystal is controlled within the range of 20 °C / cm to 100 °C / cm, and the radial temperature gradient (ΔTx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 80 °C / cm.
[0021] In some embodiments, the temperature gradient difference (ΔTz - ΔTx) between the axial temperature gradient and the radial temperature gradient of the silicon carbide crystal is within the range of 10 °C / cm to 50 °C / cm.
[0022] Based on the above, by considering the density of basal plane dislocations (PL-BPD) detected by photoluminescence and the density of basal plane dislocations (BPD) detected by potassium hydroxide (KOH) etching, the quality of silicon carbide crystals and wafers can be comprehensively analyzed, and silicon carbide crystals and wafers with extremely low defects can be selected, thereby obtaining a better epitaxial quality yield. Description of the Drawings
[0023] Figure 1 is a schematic diagram of a crystal growth apparatus according to an embodiment of the present invention;
[0024] Figures 2A to 2C is a cross-sectional schematic diagram of a method for forming a silicon carbide wafer according to some embodiments of the present invention;
[0025] Figure 3 is a flowchart of a method for forming a silicon carbide wafer according to an embodiment of the present invention.
[0026] Description of the Reference Numerals in the Drawings
[0027] 102: Reactor
[0028] 104: Induction coil
[0029] 106: Seed crystal
[0030] 108: Silicon carbide crystal
[0031] 108A: First surface
[0032] 108B: Second surface
[0033] 108W: Silicon carbide wafer
[0034] 110: Raw material
[0035] D1: First direction
[0036] S10, S20, S22, S30: Steps
[0037] Tx: Radial temperature gradient
[0038] Tz: Axial temperature gradient Detailed implementation manners
[0039] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same component symbols are used in the drawings and the description to denote the same or similar parts.
[0040] Figure 1 is a schematic diagram of a crystal growth apparatus according to an embodiment of the present invention. Figures 2A to 2C is a cross-sectional schematic diagram of a method for forming a silicon carbide wafer according to some embodiments of the present invention. Figure 3 is a flowchart of a method for forming a silicon carbide wafer according to an embodiment of the present invention. Hereinafter, reference will be made to Figure 1 the crystal growth apparatus shown in Figures 2A to 2C in conjunction with the cross-sectional schematic diagram of Figure 3 and the flowchart of
[0041] As shown in Figure 1 and Figure 3As shown in step S10, in the method for forming a silicon carbide crystal according to an embodiment of the present invention, a raw material 110 containing carbon and silicon elements and a seed crystal 106 located above the raw material 110 are provided in a reactor 102. For example, the raw material 110 is, for example, silicon carbide powder, which is placed at the bottom of the reactor 102 as a solid sublimation source. The seed crystal 106 is disposed at the top of the reactor 102. In some embodiments, the seed crystal 106 can be fixed to a seed crystal carrier (not shown) through an adhesive layer. The material of the seed crystal 106 includes silicon carbide. For example, the seed crystal 106 is 6H silicon carbide or 4H silicon carbide. In other embodiments, the seed crystal 106 is a combination of 6H silicon carbide and 4H silicon carbide.
[0042] As Figure 1 well as Figure 3 shown in step S20, a silicon carbide crystal growth process is performed to form a silicon carbide crystal 108 as Figure 2A shown. For example, the growth process includes heating the reactor 102 and the raw material 100 to form a silicon carbide crystal 108 on the seed crystal 106. In some embodiments, the growth process further includes performing step S22 to control the axial temperature gradient (ΔTz) of the silicon carbide crystal 108 within a range of 20°C / cm to 150°C / cm, and controlling the radial temperature gradient (ΔTx) of the silicon carbide crystal within a range of 10°C / cm to 100°C / cm to form the silicon carbide crystal 108.
[0043] In the above steps S20 and S22, a silicon carbide crystal 108 is formed on the seed crystal 106 by physical vapor transport (PVT). In some embodiments, an induction coil 104 is used to heat the reactor 102 and the raw material 110 to form a silicon carbide crystal 108 on the seed crystal 106. In the above process, the seed crystal 106 will receive the raw material 110 (silicon carbide powder) solidified from the gas state and slowly grow a semiconductor crystal on the seed crystal 106 until a silicon carbide crystal 108 with an expected size is obtained. Then, after the silicon carbide crystal 108 grows to the expected size, the reactor 102 and the raw material 110 are cooled to obtain a silicon carbide ingot composed of the silicon carbide crystal 108. In some embodiments, the formed ingot may have different crystal structures depending on the crystal orientation of the single crystal seed used. For example, the silicon carbide ingot includes 4H-silicon carbide, 6H-silicon carbide, etc. Both 4H-silicon carbide and 6H-silicon carbide belong to the hexagonal crystal system.
[0044] In the above embodiments, when heating the reactor 102 and the raw material 110 to form the silicon carbide crystal 108, the axial temperature gradient (ΔTz) refers to the temperature gradient of the silicon carbide crystal 108 in the thickness direction, and the radial temperature gradient (ΔTx) refers to the temperature gradient of the silicon carbide crystal 108 in the horizontal direction perpendicular to the thickness direction. For example, by measuring the temperature change within the entire axial (thickness) range or the temperature change within the entire radial (width or radius direction) range, the value of "temperature / per unit length" (such as °C / cm) in the axial or radial direction can be obtained. In some embodiments, existing methods such as infrared thermography can be used to measure the axial and axial temperature gradients. And, in some embodiments, the difference in growth rates of each crystal orientation is utilized to adjust the difference in temperature between the axial and radial directions to control the axial temperature gradient and the radial temperature gradient within a specific range. For example, the growth rate of the <11-20> crystal orientation and the growth rate of the <1-100> crystal orientation can be controlled so that the crystals in each axial / radial direction have a certain growth rate to adjust the axial temperature gradient (ΔTz) and the radial temperature gradient (ΔTx).
[0045] As mentioned in step S22, in the crystal growth process, the axial temperature gradient (ΔTz) of the silicon carbide crystal 108 is controlled within the range of 20 °C / cm to 150 °C / cm, and the radial temperature gradient (ΔTx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 100 °C / cm. In a specific embodiment, the axial temperature gradient (ΔTz) of the silicon carbide crystal is controlled within the range of 20 °C / cm to 100 °C / cm, and the radial temperature gradient (ΔTx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 80 °C / cm. In addition, in some embodiments, the temperature gradient difference (ΔTz - ΔTx) between the axial temperature gradient (ΔTz) and the radial temperature gradient (ΔTx) of the silicon carbide crystal 108 in the growth process is within the range of 10 °C / cm to 50 °C / cm. When the axial temperature gradient (ΔTz), the radial temperature gradient (ΔTx), and the temperature gradient difference (ΔTz - ΔTx) are controlled within the above ranges, the formed silicon carbide crystal 108 can have fewer defects and better epitaxial quality yield.
[0046] Next, referring to Figure 3 step S30 of Figure 2A and as Figure 2B shown, the silicon carbide ingot (silicon carbide crystal 108) obtained through the crystal growth process is processed, such as cutting, grinding, and polishing, to form a silicon carbide wafer 108W. As Figure 2AAs shown, the silicon carbide crystal 108 can be taken out from the reactor 102. The thickness of the formed silicon carbide crystal 108 ranges from 10 mm to 100 mm, for example, in the range of 80 mm to 100 mm, or in the range of 20 mm to 60 mm. The silicon carbide crystal 108 includes a first surface 108A and a second surface 108B opposite to the first surface 108A. The first surface 108A is, for example, a carbon surface (or round top), and the second surface 108B is, for example, a silicon surface (or seed crystal end).
[0047] Next, as Figure 2B shown, the silicon carbide crystal 108 is processed. For example, the silicon carbide crystal 108 is cut and rounded into an equal-diameter cylinder to prevent the corners of the crystal from cracking due to collision and to facilitate subsequent processes. Next, the silicon carbide crystal 108 is sliced along the first direction D1 to cut and separate a plurality of wafers. The slicing method of the silicon carbide crystal 108 includes cutting with a tool or wire in cooperation with abrasive grains (such as diamond grains), or laser cutting technology can also be used. After slicing and grinding and polishing the silicon carbide crystal 108, a plurality of silicon carbide wafers 108W as Figure 2C shown can be obtained. The silicon carbide wafer 108W also has a first surface 108A (carbon surface or round top) and a second surface 108B (silicon surface or seed crystal end) opposite to the first surface 108A. In addition, the wafer diameter of the silicon carbide wafer 108W obtained by the above method is greater than 150 mm, and is, for example, 150 mm, 200 mm or 300 mm.
[0048] After obtaining the silicon carbide wafer 108W, the analysis is performed on its basal plane dislocation (BPD) density, photoluminescence basal plane dislocation (PL-BPD) density, threading screw dislocation (TSD) density, basal stacking fault (BSF) density, and stacking fault (SF) density.
[0049] In the embodiment of the present invention, the analysis of the basal plane dislocation (BPD) density is a destructive analysis using an etching method. In some embodiments, potassium hydroxide (KOH) is used to etch the wafer at 500°C, and then an instrument such as Automated Optical Inspection (AOI) is used to calculate the BPD number density. In some embodiments, the basal plane dislocation (BPD) density detected by the potassium hydroxide (KOH) etching method is less than 550 per cm at both the seed crystal end (second surface 108B) and the round top (first surface 108A) of the silicon carbide wafer 108W 2。In a specific embodiment, the basal plane dislocation (BPD) density detected by potassium hydroxide (KOH) etching is less than 200 per cm² at both the seed end (second surface 108B) and the circular top end (first surface 108A). 2 。
[0050] In addition, for the difference ratio D between the first basal plane dislocation density BPD1 at the seed end (second surface 108B) and the second basal plane dislocation density BPD2 at the circular top end (first surface 108A) of the silicon carbide wafer 108W, as detected by potassium hydroxide (KOH) etching, the following formula (1) should be satisfied:
[0051] 。
[0052] In some embodiments, the difference ratio D between the first basal plane dislocation density BPD1 at the seed end (second surface 108B) and the second basal plane dislocation density BPD2 at the circular top end (first surface 108A) is 26% or less, and for example, it is 3% to 26% or 10% to 20%.
[0053] In the embodiments of the present invention, the analysis of the basal plane dislocation (PL-BPD) density by photoluminescence is a non-destructive analysis detected by the photoluminescence method. For example, after irradiating the wafer with UV light to excite fluorescence, the detector receives the fluorescence amount and then converts it into the numerical value of the number density of PL-BPD. For example, the UV light wavelength of photoluminescence is 313 nm, 316 nm, 350 nm, 365 nm, or 385 nm. In a specific embodiment, the UV light wavelength is 316 nm or 365 nm.
[0054] In some embodiments, the basal plane dislocation (PL-BPD) density detected by the photoluminescence method is less than 2000 per cm² at both the seed end (second surface 108B) and the circular top end (first surface 108A) of the silicon carbide wafer 108W 2 。In a specific embodiment, the basal plane dislocation (PL-BPD) density detected by the photoluminescence method is less than 1000 per cm² at both the seed end (second surface 108B) and the circular top end (first surface 108A) of the silicon carbide wafer 108W 2 。
[0055] In addition, the difference ratio PL-D between the basal plane dislocation (PL-BPD) density detected by photoluminescence, i.e., the basal plane dislocation density PL-BPD1 at the seed end (the second surface 108B) of the silicon carbide wafer 108W and the second basal plane dislocation density PL-BPD2 at the circular top end (the first surface 108A), needs to satisfy the following formula (2):
[0056] .
[0057] In some embodiments, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end (the second surface 108B) and the second basal plane dislocation density PL-BPD2 at the circular top end (the first surface 108A) is 16% or less, and for example, it is 3% to 15% or 3% to 10%. In a specific embodiment, the difference ratio PL-D is 15% or less, 14% or less, 12% or less, or 10% or less.
[0058] In the embodiment of the present invention, the threading screw dislocation (TSD) density of the obtained silicon carbide wafer 108W is 5 per cm 2 or less, the basal stacking fault (BSF) density is 5 per wafer or less, and the stacking fault (SF) density is 5 per wafer or less.
[0059] When controlling the formation method of the silicon carbide wafer 108W such that the basal plane dislocation (BPD) density, the basal plane dislocation (PL-BPD) density of photoluminescence, the threading screw dislocation (TSD) density, the basal stacking fault (BSF) density, and the stacking fault (SF) density are all controlled within the above ranges, the silicon carbide wafer 108W can have better quality and a better epitaxial growth quality yield. For example, in the wafer geometric yield analysis, the warp of the silicon carbide wafer 108W is less than 40 µm, the bow is in the range of + / -20 µm, and the triangular defect density of the epitaxial chip is less than 0.1 per cm 2 .
[0060] Embodiment
[0061] To prove the importance of additionally considering the basal plane dislocation (PL-BPD) density defect of photoluminescence in addition to considering the BPD, TSD, BSF, and SF defects in the silicon carbide wafer 108W, the following embodiments are specifically used for illustration.
[0062] In this embodiment, it is as described above Figures 1 to 3The steps shown, and control the axial temperature gradient (△Tz), radial temperature gradient (△Tx), and temperature gradient difference (△Tz - △Tx) in the crystal growth process as shown in Table 1 below to form a silicon carbide crystal with a specific crystal thickness (in the range of 10 mm to 100 mm). Then, after slicing the silicon carbide crystal and grinding and polishing to obtain a silicon carbide wafer, analyze the defects of BPD, TSD, BSF, SF, and PL-BPD in the silicon carbide wafer respectively, and confirm their influence on the geometric yield of the wafer. In this embodiment, the wafer diameters of the obtained silicon carbide wafers are all 200 mm. The detailed experimental results are shown in Table 1 below.
[0063] Table 1:
[0064]
[0065] As shown in the experimental results of Table 1, when controlling the axial temperature gradient (△Tz) in the range of 20 °C / cm to 150 °C / cm, the radial temperature gradient (△Tx) in the range of 10 °C / cm to 100 °C / cm, and the temperature gradient difference (△Tz - △Tx) in the range of 10 °C / cm to 50 °C / cm, as shown in Examples 1 to 6, the silicon carbide wafer can have extremely low defects and obtain a better epitaxial quality yield. Among them, as the experimental results in Examples 1 to 6, when the BPD density at the seed end and the round top end of the wafer is less than 550 / cm 2 , and the PL-BPD density is less than 2000 / cm 2 , and the TSD density is 5 / cm 2 Below, the BSF density is 5 or less per wafer, and the SF density is 5 or less per wafer, the evaluation of the geometric yield of the formed silicon carbide wafer is all good (G). That is, the warp of the silicon carbide wafer can be less than 40 µm, the bow can be in the range of + / - 20 µm, and the triangle defect density can be less than 0.1 / cm 2 .
[0066] In contrast, referring to Control Group 1 and Control Group 2, even if the BPD density at the seed end and the round top end of the wafer is in the range of less than 550 / cm 2 , if the PL-BPD density at the seed end and the round top end is not simultaneously controlled to be less than 2000 / cm 2 , the evaluation of the geometric yield of the wafer will still be poor (NG). That is, the warp, bow, and triangle defect density of the silicon carbide wafer cannot be controlled within the ideal range.
[0067] In addition, referring to Control Group 3, even if the density of the through-spiral screw dislocation (TSD) is controlled to be 5 per cm 2 Hereinafter, the density of the columnar stacking fault (BSF) is controlled to be 5 or less per wafer, and the density of the stacking fault (SF) is controlled to be 5 or less per wafer. If the PL-BPD density at the seed end and the round top end is not simultaneously controlled to be less than 2000 per cm 2 When this is the case, the evaluation of the wafer geometric yield will still be poor (NG). That is, the warp, bow, and triangle defect density of the silicon carbide wafer still cannot be controlled within the ideal range.
[0068] In summary, by further considering the basal plane dislocation (PL-BPD) density detected by the photoluminescence method, a more complete quality analysis of the silicon carbide crystal and wafer can be provided. It is confirmed which silicon carbide crystal and wafer can have extremely low defects, enabling the wafer to have a better wafer geometric yield. More specifically, through the formation method of the present invention, the silicon carbide wafer screened by the complete analysis method of the silicon carbide wafer defects of the present invention has an epitaxial quality yield of more than 98%.
[0069] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A silicon carbide wafer, characterized in that, The silicon carbide wafer has a seed end and a round top end opposite to the seed end, wherein, The dislocation density on the basal plane detected by the potassium hydroxide etching method is less than 550 / cm at both the seed end and the round top end. 2 and The basal plane dislocation density detected by means of optically excited luminescence is less than 2000 / cm at both the seed end and the round top end 2 .
2. The silicon carbide wafer according to claim 1, wherein, For the basal plane dislocation density detected by the potassium hydroxide etching method, the difference ratio D between the first basal plane dislocation density BPD1 at the seed end and the second basal plane dislocation density BPD2 at the round top end needs to satisfy the following formula (1): 。 3. The silicon carbide wafer according to claim 1, wherein, For the basal plane dislocation density detected by the photoexcited luminescence method, the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the round top end needs to satisfy the following formula (2): 。 4. The silicon carbide wafer according to claim 3, wherein the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the round top end is 14% or less.
5. The silicon carbide wafer according to claim 3, wherein the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the round top end is 12% or less.
6. The silicon carbide wafer according to claim 3, wherein the difference ratio PL-D between the basal plane dislocation density PL-BPD1 at the seed end and the second basal plane dislocation density PL-BPD2 at the round top end is 10% or less.
7. The silicon carbide wafer according to claim 1, wherein The basal plane dislocation density detected by the potassium hydroxide etching method is less than 200 / cm at both the seed crystal end and the circular top end 2 .
8. The silicon carbide wafer according to claim 1, wherein, The basal plane dislocation density detected by the above-described optically stimulated luminescence method is less than 1000 / cm at both the seed end and the round top end. 2 .
9. The silicon carbide wafer according to claim 1, wherein, The wafer diameter of the silicon carbide wafer is 150 mm, 200 mm or 300 mm.
10. The silicon carbide wafer according to claim 1, wherein, The screw dislocation density of the silicon carbide wafer is 5 / cm 2 Hereinafter, the columnar stacking fault density is 5 or less per wafer, and the stacking fault defect density is 5 or less per wafer.
11. The silicon carbide wafer according to claim 1, wherein, The bow of the silicon carbide wafer is less than 40 µm, the warp is in the range of + / - 20 µm, and the triangular defect density is less than 0.1 per cm 2 .
12. A method for forming a silicon carbide wafer, characterized in that, The method includes: Providing a raw material containing carbon element and silicon element and a seed crystal above the raw material in a reactor; Performing a growth process of a silicon carbide crystal, wherein the growth process includes heating the reactor and the raw material to form a silicon carbide crystal on the seed crystal, And in the growth process, the axial temperature gradient (△Tz) of the silicon carbide crystal is controlled within the range of 20 °C / cm to 150 °C / cm, and the radial temperature gradient (△Tx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 100 °C / cm; and Slicing and polishing the silicon carbide crystal to obtain a silicon carbide wafer.
13. The method according to claim 12, wherein in the growth process, the axial temperature gradient (△Tz) of the silicon carbide crystal is controlled within the range of 20 °C / cm to 100 °C / cm, and the radial temperature gradient (△Tx) of the silicon carbide crystal is controlled within the range of 10 °C / cm to 80 °C / cm.
14. The method according to claim 12, wherein the temperature gradient difference (△Tz-△Tx) between the axial temperature gradient and the radial temperature gradient of the silicon carbide crystal is within the range of 10 °C / cm to 50 °C / cm.