Electronic device and manufacturing method thereof

Abstract

The invention provides an electronic device which is characterized by comprising a first substrate, a signal line, an insulating layer, a conductor layer and a connecting layer. The signal line is arranged on the first substrate. The insulating layer is arranged on the signal line and comprises a first open hole and a second open hole, and the signal line is exposed out of the first open hole and the second open hole. The conductor layer is arranged in the first opening and the second opening and is located on the signal line. The connecting layer extends from the first hole to the second hole and is electrically connected with the signal line through the conductor layer. The invention further provides a manufacturing method of the electronic device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an electronic device and a manufacturing method thereof, and particularly to an electronic device for avoiding disconnection and a manufacturing method thereof. Background Art

[0002] Signal lines of an electronic device (such as scan lines, data lines, power lines, signal driving lines, etc.) may be broken due to particles, substrate warping, or other manufacturing problems. Therefore, it is necessary to repair the signal lines to eliminate the above problems. Summary of the Invention

[0003] One aspect of the present disclosure relates to an electronic device, which includes: a first substrate; a signal line disposed on the first substrate; an insulating layer disposed on the signal line, including a first opening and a second opening, wherein the first opening and the second opening expose the signal line; a conductor layer disposed in the first opening and the second opening and on the signal line; and a connection layer extending from the first opening to the second opening and electrically connecting the signal line through the conductor layer.

[0004] Another aspect of the present disclosure relates to a manufacturing method of an electronic device, which includes: providing a first substrate; forming a signal line on the first substrate; forming an insulating layer on the signal line; patterning the insulating layer to form a first opening and a second opening, wherein the first opening and the second opening expose the signal line; forming a conductor layer in the first opening and the second opening and on the signal line; and forming a connection layer, the connection layer extending from the first opening to the second opening and electrically connecting the signal line through the conductor layer. Brief Description of the Drawings

[0005] The various aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, according to standard practices in the industry, various components are not drawn to scale and are only used for illustration. In fact, the dimensions of the components can be arbitrarily enlarged or reduced to clearly show the components of the embodiments of the present disclosure. It should also be noted that the accompanying drawings only illustrate typical embodiments of the present disclosure and should not be considered as limiting its scope. The present disclosure is equally applicable to other embodiments.

[0006] Figures 1 to 6 It is a cross-sectional view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0007] Figure 7 It is a top view of an electronic device in an intermediate manufacturing stage according to some embodiments of the present disclosure.

[0008] Figure 8 and Figure 9 According to some other embodiments of the present disclosure, a cross-sectional view of the electronic device in an intermediate manufacturing stage is shown.

[0009]

Symbol Description

[0010] 100 / 100’: Electronic device

[0011] 102: First substrate

[0012] 104: Signal line

[0013] 104T: Top surface

[0014] 106: Insulating layer

[0015] 108: First opening

[0016] 108B: Bottom surface

[0017] 110: Second opening

[0018] 110B: Bottom surface

[0019] 112: Conductor layer

[0020] 112B: Bottom surface

[0021] 114: Connection layer

[0022] 202: Second substrate

[0023] 204: Spacer

[0024] 302: Driving structure

[0025] 304: Common electrode

[0026] 306: Scan line

[0027] 308: Data line

[0028] θ: Tilt angle

[0029] H1: Thickness

[0030] H2: Height

[0031] H3: Depth

[0032] L: First length

[0033] W: First width Detailed implementation manners

[0034] A detailed description of the electronic device according to the embodiments of the present disclosure is provided below. It should be understood that the following description provides many different embodiments for implementing different aspects of some embodiments of the present disclosure. The specific components and arrangements described below are only for simply and clearly describing some embodiments of the present disclosure. Of course, these are only for illustration and not for limitation of the present disclosure. In addition, similar and / or corresponding reference numerals may be used in different embodiments to label similar and / or corresponding components to clearly describe the present disclosure. However, the use of these similar and / or corresponding reference numerals is only for simply and clearly describing some embodiments of the present disclosure, and does not represent any association between the different embodiments and / or structures discussed.

[0035] It should be understood that relative terms may be used in the embodiments, such as "lower" or "bottom" or "higher" or "top", to describe the relative relationship of one component of the drawings to another component. It can be understood that if the device of the drawings is turned upside down, the component described on the "lower" side will become the component on the "higher" side. The embodiments of the present disclosure can be combined with the attached Figure 1 And it is understood that the drawings of the present disclosure are also regarded as part of the disclosure description. It should be understood that the drawings of the present disclosure are not drawn to scale. In fact, the sizes of the components may be arbitrarily enlarged or reduced to clearly show the features of the present disclosure.

[0036] Furthermore, when it is mentioned that a first material layer is on or above a second material layer, it may include the case where the first material layer is in direct contact with the second material layer or the first material layer and the second material layer may not be in direct contact, that is, there may be one or more other material layers between the first material layer and the second material layer. However, when the first material layer is directly on the second material layer, it means that the first material layer and the second material layer are in direct contact.

[0037] In addition, it should be understood that the ordinal numbers used in the specification and the claims, such as "first", "second", etc., are used to modify the components, and they do not themselves imply and represent that the component(s) have any previous ordinal numbers, nor do they represent the order of one component and another component, or the order in the manufacturing method. The use of these ordinal numbers is only to clearly distinguish a component with a certain name from another component with the same name. The same terms may not be used in the claims and the specification. For example, the first component in the specification may be the second component in the claim.

[0038] In some embodiments of the present disclosure, terms related to joining and connection, such as "connect" and "interconnect", unless specifically defined, may mean that two structures are in direct contact, or may also mean that two structures are not in direct contact, with other structures disposed therebetween. And such terms related to joining and connection may also include cases where both structures are movable, or both structures are fixed. In addition, the term "electrically connected" or "coupled" includes any direct and indirect means of electrical connection.

[0039] In the text, terms such as "about", "substantially", and "substantially" generally mean within 10%, or 5%, or 3%, or 2%, or 1%, or 0.5% of a given value or range. Unless otherwise specified, the term "ranging from a first value to a second value" means that the range includes the first value, the second value, and other values therebetween. Furthermore, there may be a certain error between any two values or directions being compared. If the first value is equal to the second value, it implies that there may be an error of about 10% between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may range from 80 degrees to 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may range from 0 degrees to 10 degrees.

[0040] Furthermore, according to embodiments of the present disclosure, an optical microscope (OM), a scanning electron microscope (SEM), an α-step, an ellipsometer, or other suitable means can be used to measure the thickness, length, width of each component, or the distance and angle between components. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional image of the structure and measure the thickness, length, width of each component, or the distance and angle between components.

[0041] Throughout the specification of the present disclosure and the appended claims, certain terms will be used to refer to specific components. Those skilled in the art should understand that electronic device manufacturers may use different names to refer to the same component. This document does not intend to distinguish components with the same function but different names. In the following specification and claims, words such as "comprise", "include", and "have" are open-ended words, and thus should be interpreted as meaning "including but not limited to...". Therefore, when the description of the present disclosure uses the terms "comprise", "include", and / or "have", it specifies the existence of corresponding features, regions, steps, operations, and / or components, but does not exclude the existence of one or more corresponding features, regions, steps, operations, and / or components.

[0042] It should be understood that, without departing from the spirit of the present disclosure, features in several different embodiments can be replaced, recombined, and combined to complete other embodiments. As long as the features between the embodiments do not violate the spirit of the invention or conflict with each other, they can be arbitrarily combined and used.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the technical field to which the present disclosure belongs. It can be understood that these terms, for example, when defining terms in a commonly used dictionary, should be interpreted as having a meaning consistent with the related technology and the background or context of the present disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the present disclosure.

[0044] The electrical connections or couplings described in the present disclosure can all refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by a conductor line segment. In the case of an indirect connection, there are switches, diodes, capacitors, inductors, other suitable components, or a combination of the above components between the endpoints of the components on two circuits, but not limited thereto.

[0045] Generally speaking, when a signal line on a circuit board breaks somewhere and causes an open circuit, the connection layer can be used to repair the broken signal line to make it conduct again, thereby improving the reliability of the electronic device.

[0046] The present disclosure provides an electronic device for avoiding disconnection of a connection layer (or a repair line) and a manufacturing method thereof. The manufacturing method of the electronic device referred to in the present disclosure can be, for example, a repair method, which can repair defective products or solve the problem of open circuits. According to an embodiment of the present disclosure, the insulating layer can be pre-patterned to leave openings in the signal line. In the repair process, the steps of digging a hole (digging through to the substrate) and coating the hole can be omitted, and the coating and wire drawing can be directly carried out. Since the opening depth is relatively shallow, the coating thickness of the connection layer can be reduced to reduce the process time. Furthermore, according to an embodiment of the present disclosure, a conductor layer can be provided in the opening to protect the exposed surface of the signal line, so that the electronic device has better reliability.

[0047] The electronic device of the present disclosure may include, but is not limited to, a display device, a backlight device, an antenna device, a sensing device, or a splicing device. The electronic device may be a bendable or flexible electronic device. The display device may be a non-self-emitting display device or a self-emitting display device. The antenna device may be a liquid crystal type antenna device or a non-liquid crystal type antenna device. The sensing device may be a sensing device for sensing capacitance, light, heat, or ultrasonic waves, but is not limited thereto. The electronic components may include passive components and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. The diode may include a light emitting diode or a photodiode. The light emitting diode may include, for example, an organic light emitting diode (OLED), a mini light emitting diode (mini LED), a micro light emitting diode (micro LED), or a quantum dot light emitting diode (quantum dot LED), but is not limited thereto. The splicing device may be, for example, a display splicing device or an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any permutation and combination of the foregoing, but is not limited thereto. The concepts or principles of the present disclosure may also be applied to a non-self-emitting liquid crystal display (LCD) or a thin-film transistor liquid crystal display (TFT LCD), but is not limited thereto. Hereinafter, the display device will be used as the electronic device or the splicing device to illustrate the present disclosure, but the present disclosure is not limited thereto.

[0048] Figures 1 to 6 FIG. 4 is a cross-sectional view showing the electronic device 100 at an intermediate manufacturing stage according to some embodiments of the present disclosure. It should be understood that, for clarity of illustration, some components of the electronic device 100 may be omitted in the drawings, and only some components are schematically shown. According to some embodiments, additional features may be added to the electronic device 100 described below.

[0049] Reference Figure 1, in one embodiment, a first substrate 102 is first provided. In some embodiments, the first substrate 102 may include an array substrate, a polarizer, a thin film transistor (TFT) substrate, a storage capacitor, a driving integrated circuit (IC), an indium-tin oxide (ITO) pixel electrode, or a combination of the foregoing, but not limited thereto. The first substrate 102 referred to in the present disclosure includes a rigid substrate, a flexible substrate, or a combination of the foregoing. For example, the material of the first substrate 102 may include glass, quartz, sapphire, acrylic resin, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable transparent materials, or a combination of the foregoing, but not limited thereto.

[0050] In one embodiment, a signal line 104 is formed on the first substrate 102. In some embodiments, the signal line 104 may include a current signal line, a voltage signal line, a high-frequency signal line, a low-frequency signal line, and the signal line may transmit a component operating voltage (VDD), a ground terminal voltage (VSS), or a driving component terminal voltage, but not limited thereto. In some embodiments, the material of the signal line 104 may include copper (Cu), aluminum (Al), indium (In), ruthenium (Ru), tin (Sn), gold (Au), platinum (Pt), molybdenum (Mo), zinc (Zn), silver (Ag), titanium (Ti), lead (Pb), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), magnesium (Mg), palladium (Pd), lithium (Li), calcium (Ca), alloys of the foregoing metals, other suitable metal materials, or a combination of the foregoing, but not limited thereto.

[0051] Reference Figure 2, in one embodiment, an insulating layer 106 is formed on the signal line 104. In some embodiments, the material of the insulating layer 106 may include inorganic insulating materials, organic insulating materials, combinations of the foregoing, or any suitable insulating materials, but is not limited thereto. According to some embodiments, the inorganic materials may include silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, other suitable materials, or combinations of the foregoing, but are not limited thereto. According to some embodiments, the organic materials may include epoxy resins, silicone resins, acrylic resins (such as polymethyl methacrylate (PMMA)), benzocyclobutene (BCB), polyimide, polyester, polydimethylsiloxane (PDMS), perfluoroalkoxy alkane (PFA), other suitable materials, or combinations of the foregoing, but are not limited thereto. In some embodiments, the insulating layer may be a single-layer structure or a multi-layer structure.

[0052] Reference Figure 3 , in one embodiment, the insulating layer 106 is patterned to form a first opening 108 and a second opening 110, wherein the first opening 108 and the second opening 110 expose the signal line 104. It should be noted that although Figure 3 the first opening 108 and the second opening 110 are shown corresponding to their respective signal lines 104 in the figure, it is not limited thereto. In other embodiments, the first opening 108 and the second opening 110 may respectively correspond to a common electrode, a scan line, or a data line, but are not limited thereto. In some embodiments, the first opening 108 and the second opening 110 may have a tapered cross-sectional shape towards the first substrate 102, but are not limited thereto. In some embodiments, the inclination angle θ of the sidewalls of the first opening 108 and the second opening 110 is in the range of 30° to 50° (for example: 35°, 40°, or 45°). The above inclination angle θ refers to the angle between the sidewall surface of the opening and the normal of the first substrate 102. An inclination angle θ in the range of 30° to 50° can result in better coating quality in subsequent processes.

[0053] The patterning process of the first opening 108 and the second opening 110 may include a photolithography-etching step using a photomask to define a photoresist pattern on the unpatterned insulating layer 106, and then etching the insulating layer 106 using this photoresist pattern as a mask to form the first opening 108 and the second opening 110. According to some embodiments, the photolithography process may include, but is not limited to, photoresist coating (such as spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying. The etching process may include a dry etching process or a wet etching process, but is not limited thereto. The process conditions of the etching step need to remove the insulating layer 106 above the signal line 104 to expose the signal line 104.

[0054] Reference Figure 4 , in one embodiment, a conductor layer 112 is formed in the first opening 108 and the second opening 110 and on the signal line 104. In some embodiments, the conductor layer 112 is conformally formed in the first opening 108 and the second opening 110 and covers the exposed surface of the signal line 104. The conductor layer 112 is used to protect the surface of the signal line 104 exposed by the first opening 108 and the second opening 110 to prevent the signal line 104 from being oxidized or corroded during other processes before the repair process, which may affect the electrical connection between the signal line 104 and the connection layer 114 ( Figure 5 ). As shown in the figure, the conductor layer 112 conformally covers the bottom and sidewalls of the first opening 108 and the second opening 110 and extends to the top surface of the insulating layer 106, but is not limited thereto. In other embodiments, the conductor layer 112 may not extend to the top surface of the insulating layer 106 or may not be conformally formed in the opening, as long as the conductor layer 112 can cover the surface of the signal line 104 to provide protection.

[0055] In some embodiments, the conductor layer 112 may include a metal conductive material (such as copper, aluminum, silver, gold), a transparent conductive material (such as indium-tin oxide (ITO), indium gallium zinc oxide (IGZO), or aluminum zinc oxide (AZO)), other suitable types of conductive materials, or a combination of the foregoing materials, but is not limited thereto. In some embodiments, the conductor layer 112 is a single-layer structure and directly contacts the signal line 104, but is not limited thereto. In some embodiments, the thickness of the conductor layer 112 is to (for example: to to or to ), the thickness of the conductor layer 112 is to enable the electronic device 100 to have better reliability.

[0056] In some embodiments, a deposition process may be used to form a conductor material layer (not shown), and then a photolithography process and an etching process may be used to pattern the conductor material layer to form the conductor layer 112. In some embodiments, the deposition process may include coating methods such as evaporation coating, sputtering coating, ion beam evaporation coating, etc., but is not limited thereto. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning, and drying, etc., but is not limited thereto. The etching process may include a dry etching process or a wet etching process, but is not limited thereto.

[0057] Referring to Figure 5 , in one embodiment, the connection layer 114 is formed. The connection layer 114 extends from the first opening 108 to the second opening 110 and electrically connects the signal line 104 through the conductor layer 112. In some embodiments, when the signal line 104 on the first substrate 102 is broken at a certain location and causes an open circuit, the connection layer 114 can be used to electrically connect the two signal lines 104 through the conductor layer 112 to make it conduct again, improving the reliability of the electronic device.

[0058] It should be noted that in some embodiments of this case, by pre-patterning the insulating layer 106 to retain the first opening 108 and the second opening 110 on the signal line 104, coating wire drawing can be directly performed in the subsequent repair process. And because the depths of the first opening 108 and the second opening 110 are relatively shallow, the thickness of the connection layer 114 can be reduced in the subsequent repair process to reduce the process time. In some embodiments, when applied to a display, the problem that the connection layer 114 is damaged by the spacer 204 ( Figure 6 ) can be avoided.

[0059] In one embodiment, the thickness H1 of the connection layer 114 is from 0.3 micrometers (μm) to 0.5 micrometers (e.g., 0.4 micrometers), which can enable the connection layer 114 to have better electrical performance. In some embodiments, the connection layer 114 may include a metal mixed material such as nickel tetracarbonyl (Ni(CO)4), iron pentacarbonyl (Fe(CO)5), chromium hexacarbonyl (Cr(CO)6), molybdenum hexacarbonyl (Mo(CO)6), or tungsten hexacarbonyl (W(CO)6), or other suitable materials formed by laser chemical vapor deposition (LCVD) process technology, or formed by a conductive adhesive (the conductive adhesive is composed of a conductive substance and a substrate, the conductive substance is usually metal powder, carbon black or a conductive polymer, and the substrate can be a polymer, rubber or any composite material), but not limited thereto. In one embodiment, the connection layer 114 may be a tungsten metal layer (not shown) formed by using tungsten hexacarbonyl (W(CO)6) as a source gas through LCVD process technology. In some embodiments, the metal mixed material may be patterned by a photolithography process and an etching process to form the connection layer 114. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, hard baking, mask alignment, exposure, post-exposure baking, photoresist development, cleaning and drying, etc., but not limited thereto. The etching process may include a dry etching process or a wet etching process, but not limited thereto.

[0060] As Figure 5 shown, in one embodiment, the electronic device 100 of the present disclosure includes: a first substrate 102, a signal line 104 disposed on the first substrate 102, an insulating layer 106 disposed on the signal line 104, which includes a first opening 108 and a second opening 110 exposing the signal line 104, a conductor layer 112 disposed in the first opening 108 and the second opening 110 and on the signal line 104, and a connection layer 114 extending from the first opening 108 to the second opening 110 and electrically connecting the signal line 104 through the conductor layer 112.

[0061] Please refer to Figure 6, in one embodiment, the electronic device 100 further includes a second substrate 202 disposed opposite to the first substrate 102 and at least one spacer 204 disposed on the second substrate 202 and located between the first substrate 102 and the second substrate 202. In some embodiments, the spacer 204 is used to support the first substrate 102 and the second substrate 202. In this embodiment, the first substrate 102 may include a thin film transistor substrate, and the second substrate 202 may include a color filter array substrate (COA). The spacer 204 is used to ensure sufficient gap height and uniformity between the first substrate 102 and the second substrate 202, thereby forming a space for accommodating the liquid crystal (not shown) between the first substrate 102 and the second substrate 202. However, this is not limited thereto. In other embodiments, the spacer 204 is used to support the second substrate 202 to prevent the second substrate 202 from skewing.

[0062] In some embodiments, the material of the spacer 204 may include photoresist (i.e., photo spacer), polymer (i.e., polymer pattern), metal (i.e., metal pattern), film, tape, glue, or underfill, but is not limited thereto. In some embodiments, the shape of the spacer 204 may include spherical, columnar, trapezoidal, inverted trapezoidal, etc., but is not limited thereto. In some embodiments, the spacers 204 may be distributed regularly or irregularly in the electronic device 100. It should be noted that although Figure 6 only one spacer 204 is shown and it is columnar, the present disclosure is not limited thereto. In other embodiments, any size, arrangement, and number of spacers 204 may be provided in the electronic device 100.

[0063] In one embodiment, at least one spacer 204 overlaps the first opening 108, that is, the spacer 204 may overlap the first opening 108 or the second opening 110, or two spacers 204 may overlap the first opening 108 and the second opening 110 respectively.

[0064] By the manufacturing method of the electronic device 100 provided by the present disclosure, coating wire drawing can be directly performed in the repair process. In some embodiments, when applied to a display, the problem that the connection layer 114 is damaged by the spacer 204 can be avoided, thereby improving the yield and reliability of the product.

[0065] In one embodiment, in a cross-sectional view, the first opening 108 has a first width W in a direction normal to the first substrate 102. In some embodiments, the first width W may refer to, for example, the width of the opening on the lower surface of the insulating layer 106, or the width of the signal line 104 exposed by the first opening 108. The conductor layer 112 has a first length L in a direction normal to the first substrate 102. The above-mentioned first width W and first length L can be measured, for example, in a cross-sectional view using an optical microscope (OM) or a scanning electron microscope (SEM). Specifically, the first width W is the width of the surface of the signal line 104 exposed by the first opening 108 or the second opening 110, and the first length L is the maximum length of the conductor layer 112 in the cross-sectional view. In one embodiment, the ratio of the first length L to the first width W is greater than or equal to 1.5 and less than or equal to 2 (2≥L / W≥1.5) to ensure that the conductor layer 112 covers the surface of the signal line 104 exposed by the first opening 108 or the second opening 110, so that the electronic device 100 has better reliability.

[0066] Figure 7 FIG. is a top view showing the electronic device 100 in an intermediate manufacturing stage according to an embodiment of the present disclosure. The foregoing Figures 1 to 6 is according to Figure 7 the reference section A-A shown in

[0067] Referring to Figure 7 , in some embodiments, the electronic device 100 further includes a driving structure 302, a common electrode 304, a scanning line 306, a data line 308, but is not limited thereto. In some embodiments, the driving structure 302 may include active components, passive components, or a combination of the foregoing, but is not limited thereto. In the present embodiment, the driving structure 302 may include a thin film transistor (TFT). In some embodiments, the thin film transistor may include a switching transistor, a driving transistor, a reset transistor, a transistor amplifier, or other suitable thin film transistors, but is not limited thereto.

[0068] In one embodiment, in a top view, the first opening 108 and the second opening 110 are arranged adjacent to each other. The term "adjacent" herein refers to the two closest openings, and there are no other openings between the two openings. In one embodiment, in a top view, the first opening 108 and the second opening 110 are arranged between two adjacent driving structures 302.

[0069] It should be understood that after the first substrate 102 and the second substrate 202 are aligned, subsequent processes can be carried out according to actual requirements to complete the manufacture of the electronic device 100. Since this is not the focus of the present disclosure, it will not be elaborated here.

[0070] The following will refer to Figure 8 and Figure 9 to illustrate some other embodiments of the present disclosure. Figure 8 and Figure 9 is a cross-sectional view showing the electronic device 100' at an intermediate manufacturing stage according to another embodiment of the present disclosure. It should be noted that as long as the features between the embodiments do not violate the spirit of the present disclosure or conflict with each other, they can be arbitrarily mixed and used.

[0071] In some other embodiments, Figure 8 subsequent to Figure 2 the process of Figure 8 the electronic device 100' in Figure 3 is similar to the electronic device 100 in Figure 3 , except that the bottom surfaces 108B / 110B of the first opening 108 and the second opening 110 are lower than the top surface 104T of the signal line 104. Specifically, in this embodiment, during the process of forming the first opening 108 and the second opening 110 in the patterned insulating layer 106, over etching is performed to ensure that the insulating layer in the first opening 108 and the second opening 110 is completely removed. Therefore, during the over etching process, part of the signal line 104 may be recessed, resulting in a concave top surface. Specifically, the signal line 104 may have a height H2 in the normal direction of the first substrate 102, and the concave top surface has a depth H3. The height H2 and the depth H3 may satisfy the following proportional relationship: 20% ≥ H3 / H2 ≥ 5%, so as to ensure better reliability of the electronic device.

[0072] Referring to Figure 9 , in some embodiments, after the signal line 104 is recessed, a conductor layer 112 and a connection layer 114 are formed. The conductor layer 112 is formed not only in the first opening 108 and the second opening 110, but also on the exposed surface of the signal line 104 after being recessed. As shown in the figure, the conductor layer 112 conformally covers the bottom (the exposed surface of the signal line 104 after being recessed) and the side walls of the first opening 108 and the second opening 110, and extends to the top surface of the insulating layer 106, but is not limited thereto. In some embodiments, after the conductor layer 112 is formed, a connection layer 114 is formed. The connection layer 114 extends from the first opening 108 to the second opening 110 and electrically connects the signal line 104 through the conductor layer 112. In one embodiment, the bottom surface 112B of the conductor layer 112 is lower than the top surface 104T of the signal line 104. The remaining process details are as described above, so they will not be elaborated here.

[0073] In summary, the present disclosure provides an electronic device for avoiding disconnection of a connection layer (or repair line) and a manufacturing method thereof. According to an embodiment of the present disclosure, an insulating layer can be pre-patterned to reserve openings for signal lines. During the repair process, coating and wire drawing can be directly performed. Since the opening depth is relatively shallow, the coating thickness of the connection layer can be reduced to shorten the process time. Furthermore, according to an embodiment of the present disclosure, a conductor layer can be disposed in the opening to protect the exposed surface of the signal line, preventing the signal line from being oxidized or corroded during other processes before the repair process, thereby affecting the electrical connection between the signal line and the connection layer, and enabling the electronic device to have better reliability.

[0074] The foregoing outlines components of several embodiments so that those skilled in the art to which the present disclosure pertains can more readily understand the viewpoints of the embodiments of the present disclosure. Those skilled in the art to which the present disclosure pertains should understand that they can, based on the embodiments of the present disclosure, design or modify other processes and structures to achieve the same purposes and / or advantages as those introduced in the embodiments herein. Those skilled in the art to which the present disclosure pertains should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

Claims

1. An electronic device, characterized in that, Comprising: A first substrate; A signal line disposed on the first substrate; An insulating layer disposed on the signal line, including a first opening and a second opening, wherein the first opening and the second opening expose the signal line; A conductor layer disposed in the first opening and the second opening and on the signal line; And A connection layer extending from the first opening to the second opening and electrically connecting the signal line through the conductor layer.

2. The electronic device according to claim 1, wherein The conductor layer is indium tin oxide.

3. The electronic device according to claim 1, wherein The thickness of the connection layer 114 is 0.3 to 0.5 um.

4. The electronic device according to claim 1, wherein Further comprising: A second substrate disposed opposite to the first substrate; and At least one spacer disposed on the second substrate and between the first substrate and the second substrate.

5. The electronic device according to claim 4, characterized in that, The at least one spacer overlaps the first opening.

6. The electronic device according to claim 1, wherein In a cross-sectional view, the first opening has a first width in a normal direction perpendicular to the first substrate, the conductor layer has a first length in the normal direction perpendicular to the first substrate, and a ratio of the first length to the first width is greater than or equal to 1.5 and less than or equal to 2.

7. The electronic device according to claim 1, characterized in that In a top view, the first opening and the second opening are disposed adjacent to each other.

8. The electronic device according to claim 1, characterized in that, In a top view, the first opening and the second opening are disposed between adjacent driving structures.

9. The electronic device according to claim 1, wherein The bottom surface of the conductor layer is lower than the top surface of the signal line.

10. A manufacturing method of an electronic device, characterized in that, Comprising: Providing a first substrate; Forming a signal line on the first substrate; Forming an insulating layer on the signal line; Patterning the insulating layer to form a first opening and a second opening, wherein the first opening and the second opening expose the signal line; Forming a conductor layer in the first opening and the second opening and on the signal line; And Forming a connection layer, the connection layer extending from the first opening to the second opening and electrically connecting the signal line through the conductor layer.

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