Semiconductor structure and forming method thereof
By using etching processes of sacrificial layers and anti-reflective coatings in semiconductor structures, the morphological problems caused by the lithography process are solved, and the electrical performance and layer morphological quality are improved.
Patent Information
- Application Number
- CN202510449894.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-07-11
AI Technical Summary
When the existing lithography process patterning the film layer, the semiconductor structure has poor morphology and affects electrical properties.
By forming a sacrificial layer and an anti-reflective coating on the substrate, the sacrificial layer is used as a mask for etching, combined with multiple etching processes, the damage to the stacked structure is reduced, the morphological quality of the stacked structure is improved, and the target layer is protected when the sacrificial layer is removed, forming the target layer.
The electrical performance of the semiconductor structure is improved, the damage to the target layer is reduced, the side wall flatness of the stacked structure is improved, and the layer morphology that meets the process requirements is met.
Smart Images
Figure CN120299996A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same. Background Art
[0002] With the rapid development of semiconductor technology, the integration degree of semiconductor devices is getting higher and higher, and the size of a single device is getting smaller and smaller.
[0003] However, due to the limitations of the lithography process, when patterning some film layers, the morphology of the formed structure is poor, and the electrical performance of the semiconductor structure deteriorates. Summary of the Invention
[0004] In view of this, embodiments of the present invention provide a semiconductor structure and a method for forming the same, which can improve the electrical performance of the semiconductor structure.
[0005] Embodiments of the present invention provide a method for forming a semiconductor structure, including: providing a substrate, forming a layer to be processed on the substrate, and a stacked structure on the layer to be processed; forming a sacrificial layer on the stacked structure; forming an anti-reflection coating, the anti-reflection coating exposing a part of the surface of the sacrificial layer; using the anti-reflection coating as a mask, etching the sacrificial layer and the stacked structure in sequence to expose a part of the surface of the layer to be processed; using the sacrificial layer as a mask, etching the layer to be processed to form a target layer; removing the sacrificial layer.
[0006] Optionally, the step of forming the anti-reflection coating includes:
[0007] forming an anti-reflection coating material layer on the sacrificial layer;
[0008] forming a photoresist on the anti-reflection coating material layer, the photoresist exposing a part of the surface of the anti-reflection coating material layer;
[0009] using the photoresist as a mask, adopting at least two etching processes to remove the anti-reflection coating material layer exposed by the photoresist, and the remaining anti-reflection coating material layer is used as the anti-reflection coating;
[0010] wherein, in each etching process, the etching selectivity ratio is different, and after exposing a part of the layer to be processed and before forming the target layer, the photoresist is also removed.
[0011] Optionally, the at least two etching processes include a first etching process and a second etching process;
[0012] when using the first etching process to remove the anti-reflection coating material layer, the anti-reflection coating and the photoresist have a first etching selectivity ratio;
[0013] In the process of removing the anti-reflection coating material layer by using the second etching process, the anti-reflection coating and the sacrificial layer have a second etching selectivity ratio.
[0014] Optionally, one or more of the following are satisfied;
[0015] The parameters of the first etching process include: the first etching process is a dry etching process, the process gas includes CF4, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 200 V to 300 V, and the etching time is 15 s to 20 s;
[0016] The parameters of the second etching process include: the second etching process is a dry etching process, the process gas includes CL2 and O2, the flow rate of CL2 is 10 sccm to 30 sccm, the flow rate of O2 is 10 sccm to 30 sccm, the atmosphere gas includes He, the flow rate of He is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 100 V to 150 V, and the etching time is 15 s to 25 s;
[0017] The first etching selectivity ratio is greater than 50:1;
[0018] The second etching selectivity ratio is greater than 50:1.
[0019] Optionally, before etching the sacrificial layer and the stacked structure in sequence with the anti-reflection coating as a mask and exposing the surface of part of the layer to be processed, the forming method further includes:
[0020] Hardening the photoresist, and using the hardened photoresist as a mask.
[0021] Optionally, the parameters of the hardening treatment include: the hardening process is plasma treatment, the gas includes HBr, the radio frequency power is 800 W to 1200 W, and the treatment time is 30 s to 50 s.
[0022] Optionally, after etching the sacrificial layer and the stacked structure and before forming the target layer, the forming method further includes:
[0023] Trimming the sidewalls of the sacrificial layer and the stacked structure to remove part of the thickness of the sacrificial layer and the stacked structure.
[0024] Optionally, the parameters for trimming the sidewalls of the sacrificial layer and the stacked structure include:
[0025] The trimming gas includes CF4 and CHF3, the flow rate of CF4 is from 50 sccm to 100 sccm, the flow rate of CHF3 is from 10 sccm to 30 sccm, and the RF power is from 400 W to 800 W.
[0026] Optionally, the stacked structure includes: a first hard mask layer and a second hard mask layer located on the first hard mask layer.
[0027] Optionally, in the step of providing the substrate, the substrate further has an isolation structure, the isolation structure divides the substrate into a plurality of active regions, and there is a height difference between the surface of the isolation structure and the surface of the active regions;
[0028] The layer to be processed covers the surface of the isolation structure.
[0029] The present invention also provides a semiconductor structure, including:
[0030] A substrate, on which there is a layer to be processed, and a stacked structure located on the layer to be processed;
[0031] A sacrificial layer, located on the stacked structure;
[0032] An anti-reflection coating, exposing part of the surface of the sacrificial layer;
[0033] A target layer, located on the substrate and exposing part of the surface of the substrate;
[0034] Wherein, the target layer is formed by etching the layer to be processed with the sacrificial layer as a mask, and the exposed surface of the part of the layer to be processed is obtained by etching the sacrificial layer and the stacked structure in sequence with the anti-reflection coating as a mask.
[0035] Optionally, the semiconductor structure satisfies one or more of the following:
[0036] The stacked structure includes: a first hard mask layer and a second hard mask layer located on the first hard mask layer;
[0037] The target layer includes a gate structure;
[0038] An isolation structure, located in the substrate, the isolation structure divides the substrate into a plurality of active regions, and there is a height difference between the surface of the isolation structure and the surface of the active regions.
[0039] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:
[0040] In the method for forming a semiconductor structure provided by an embodiment of the present invention, by pre-forming a sacrificial layer, during the process of forming an anti-reflection coating, damage to the stacked structure can be reduced, and the topography quality of the stacked structure can be improved. When etching the sacrificial layer and the stacked structure in sequence, the sidewalls of the stacked structure have a relatively high flatness, so that when etching the layer to be processed, the topography of the target layer is correspondingly improved. Moreover, during the process of removing the sacrificial layer, the stacked structure can play a role in protecting the target layer and reduce damage to the target layer, thus improving the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] Figures 1 to 8 It is a schematic cross-sectional structure diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION
[0042] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the scope of protection of the present application.
[0043] Currently, the performance of semiconductor structures needs to be improved. In a method for forming a semiconductor structure, a gate structure is formed by patterning polysilicon. However, in the step of patterning polysilicon, due to problems such as polysilicon residue or active region damage defects on the surface of the substrate, the etching window of polysilicon is limited, and a gate structure that meets the process requirements cannot be formed.
[0044] To solve the above technical problems, the present invention provides a method for forming a semiconductor structure, including: providing a substrate, a layer to be processed is formed on the substrate, and a stacked structure is located on the layer to be processed; forming a sacrificial layer on the stacked structure; forming an anti-reflection coating, and a part of the surface of the sacrificial layer is exposed by the anti-reflection coating; using the anti-reflection coating as a mask, etching the sacrificial layer and the stacked structure in sequence to expose a part of the surface of the layer to be processed; using the sacrificial layer as a mask, etching the layer to be processed to form a target layer; removing the sacrificial layer.
[0045] In the present invention, by pre-forming a sacrificial layer, during the process of forming an anti-reflection coating, damage to the stacked structure can be reduced, and the topography quality of the stacked structure can be improved. When etching the sacrificial layer and the stacked structure in sequence, the sidewalls of the stacked structure have a high flatness, so that when etching the layer to be processed, the topography of the target layer is correspondingly improved. Moreover, during the process of removing the sacrificial layer, the stacked structure can play a role in protecting the target layer, reducing damage to the target layer, and thus improving the electrical performance of the semiconductor structure.
[0046] To make the above objects, features, and advantages of the present invention more obvious and understandable, the following specifically describes exemplary embodiments of the present invention with reference to the accompanying drawings.
[0047] Figures 1 to 8 It is a schematic cross-sectional structure diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.
[0048] Refer to Figure 1 , a substrate 100 is provided, on which a layer to be processed 110 and a stacked structure 120 located on the layer to be processed 110 are formed.
[0049] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of the semiconductor structure. Among them, the semiconductor structure can include a fin field-effect transistor (FinFET) or a gate-all-around transistor (GAA).
[0050] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.
[0051] In some embodiments, the substrate may further include a substrate, a plurality of discrete fin portions located above the substrate, and an isolation structure located on the substrate exposed by the fin portions. The isolation structure can cover a part of the sidewalls of the fin portions, and the top of the isolation structure is lower than the top of the fin portions.
[0052] For example, referring to Figure 1 , in the step of providing the substrate 100, the substrate 100 further has isolation structures 102 and 104, and the isolation structures 102 and 104 divide the substrate 100 into a plurality of active regions (not marked in the figure).
[0053] In other words, the isolation structure defines the region of the active region, and the substrate 100 between any adjacent isolation structures is the active region, so that isolation between adjacent devices can be achieved.
[0054] In this embodiment, the method for forming the isolation structures 102 and 104 includes: forming isolation grooves in the substrate 100; and forming the isolation structures 102 and 104 in the isolation grooves by chemical vapor deposition.
[0055] In this embodiment, the materials of the isolation structures 102 and 104 are insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and boron carbonitride nitride.
[0056] In a specific embodiment, the materials of the isolation structures 102 and 104 are silicon oxide.
[0057] In this embodiment, the isolation structure 104 can be a shallow trench isolation (STI) structure.
[0058] In this embodiment, due to process parameters, actual manufacturing requirements, and the influence of the previous process, the heights of the formed isolation structures 102 and 104 are not exactly the same.
[0059] For example, in Figure 1 the structure shown, the height of the isolation structure 102 is higher than that of the isolation structure 104, and there is a height difference between the surface of the isolation structure 102 and the surface of the active region, and there is also a height difference between the surface of the isolation structure 104 and the surface of the active region.
[0060] In a specific embodiment, the surface of the isolation structure 102 is higher than the surface of the active region, while the surface of the isolation structure 104 is lower than the surface of the active region.
[0061] Thus, when there is a height difference between the surface of the isolation structure and the surface of the active region, the subsequently deposited layer to be processed 110 and the stacked structure 120 are affected by this height difference and have different morphologies.
[0062] The layer to be processed 110 provides a process basis for forming the target layer 150 (see Figure 8 ).
[0063] In this embodiment, the material of the layer to be processed 110 can be polysilicon. Correspondingly, the target layer 150 can be a gate structure.
[0064] It should be noted that in different application scenarios, the material of the layer to be processed 110 is different, and the formed target layer 150 is also different. The embodiments of the present invention do not limit the materials, functions, etc. of the layer to be processed and the target layer.
[0065] In this embodiment, the process for forming the layer to be processed 110 includes one or more of chemical vapor deposition, atomic layer deposition, and epitaxial growth processes.
[0066] In a specific embodiment, the layer to be processed 110 is formed by chemical vapor deposition. The film layer formed by chemical vapor deposition is thin and uniform, and has a dense structure, which is beneficial to improving the coverage ability of the layer to be processed 110 and enabling the layer to be processed 110 to have good adhesion to the substrate 100.
[0067] It should be noted that, first, when the isolation structures 102 and 104 are formed in the substrate 100, the layer to be processed 110 covers the surfaces of the isolation structures 102 and 104; second, when there is a height difference between the surface of the isolation structure and the surface of the active region, the top of the layer to be processed 110 has protrusions and depressions.
[0068] In a specific embodiment, referring to Figure 1 , if the height of the surface of the isolation structure 102 is higher than the height of the surface of the active region, the protrusion of the layer to be processed 110 is correspondingly arranged with the isolation structure 102; if the height of the surface of the isolation structure 104 is lower than the height of the surface of the active region, the depression of the layer to be processed 110 is correspondingly arranged with the isolation structure 104.
[0069] The stacked structure 120 serves to protect the layer to be processed 110, improve the surface of the target layer 150, and improve the surface flatness.
[0070] In this embodiment, the stacked structure 120 may include: a first hard mask layer 122 and a second hard mask layer 124 located on the first hard mask layer 122.
[0071] Among them, the second hard mask layer 124 serves as the main body of the stacked structure 120, and the thickness of the second hard mask layer 124 is much greater than the height of the first hard mask layer 122.
[0072] In this embodiment, the material of the first hard mask layer 122 includes silicon oxide. The silicon oxide material has good adhesion to the substrate 100, which is beneficial to improving the stability and process treatment effect of subsequent processes; moreover, silicon oxide is a commonly used silicon oxide in semiconductor processes, which can reduce the difficulty and process cost of forming the first hard mask layer 122 and improve process compatibility.
[0073] In this embodiment, the material of the second hard mask layer 124 includes silicon nitride.
[0074] In this embodiment, the first hard mask layer 122 and the second hard mask layer 124 can be sequentially formed by chemical vapor deposition. The film layer formed by chemical vapor deposition is thin and uniform, and has a dense structure, which is beneficial to improving the coverage ability of the first hard mask layer 122 and the second hard mask layer 124, and enabling the first hard mask layer 122 to have good adhesion to the layer to be processed 110, and enabling the second hard mask layer 124 to have good adhesion to the first hard mask layer 122.
[0075] It should be noted that when there is a height difference between the surface of the isolation structure and the surface of the active region, the tops of the first hard mask layer 122 and the second hard mask layer 124 both have protrusions and depressions.
[0076] In a specific embodiment, referring to Figure 1 , if the height of the surface of the isolation structure 102 is higher than the height of the surface of the active region, the protrusions of the first hard mask layer 122 and the second hard mask layer 124 are correspondingly arranged with the isolation structure 102; if the height of the surface of the isolation structure 104 is lower than the height of the surface of the active region, the depressions of the first hard mask layer 122 and the second hard mask layer 124 are correspondingly arranged with the isolation structure 104.
[0077] Referring to Figure 2 , a sacrificial layer 130 is formed on the stacked structure 120.
[0078] The sacrificial layer 130 is used as a mask when patterning the processing layer 110, and the sacrificial layer 130 can be used as a protective layer to prevent the surface of the second hard mask layer 124 from being directly exposed to the air, thereby improving the surface quality of the second hard mask layer 124.
[0079] Moreover, by pre-forming the sacrificial layer 130, during the formation of the anti-reflection coating 140, the damage to the stacked structure 120 can be reduced, and the topography quality of the stacked structure 120 can be improved, which is beneficial to improving the topography of the target layer 150.
[0080] In this embodiment, the sacrificial layer 130 is formed by chemical vapor deposition. The film layer formed by chemical vapor deposition is thin and uniform, and has a dense structure, which is beneficial to improving the coverage ability of the sacrificial layer 130 and enabling the sacrificial layer 130 to have good adhesion to the stacked structure 120.
[0081] In this embodiment, the materials of the sacrificial layer 130 and the first hard mask layer 122 can be the same. For example, the materials of the sacrificial layer 130 and the first hard mask layer 122 can both include silicon oxide. It should be noted that when there is a height difference between the surface of the isolation structure and the surface of the active region, the top of the sacrificial layer 130 has protrusions and depressions.
[0082] In a specific embodiment, referring to Figure 2 , if the height of the surface of the isolation structure 102 is higher than the height of the surface of the active region, the protrusions of the sacrificial layer 130 are correspondingly arranged with the isolation structure 102; if the height of the surface of the isolation structure 104 is lower than the height of the surface of the active region, the depressions of the sacrificial layer 130 are correspondingly arranged with the isolation structure 104.
[0083] Referring to Figures 3 to 6, an anti-reflective coating 140 is formed, and the anti-reflective coating 140 exposes the surface of a part of the sacrificial layer 130.
[0084] The anti-reflective coating 140 has fluidity. Forming the anti-reflective coating 140 on the sacrificial layer 130 can make the surface of the anti-reflective coating 140 have a high flatness, and the anti-reflective coating 140 can fill the recesses at the top of the sacrificial layer 130 and the spaces on both sides of the protrusions.
[0085] In this embodiment, the material of the anti-reflective coating 140 includes: a dielectric anti-reflective coating (DARC) material or a bottom anti-reflective coating (BARC) material.
[0086] In a specific embodiment, the material of the anti-reflective coating 140 is BARC.
[0087] When there is a height difference between the surface of the isolation structure and the surface of the active region, the inventor found that if an over-etching process is used to form the anti-reflective coating 140, a large amount of photoresist 134 will be consumed. In this way, when the sacrificial layer 130 is etched, the top of the sacrificial layer 130 is likely to be deformed (for example, the top of the sacrificial layer 130 becomes an irregular shape); if the etching is insufficient, the anti-reflective coating 140 will remain at the non-etching window, further resulting in the residue of the layer to be processed 110, which will cause damage to the active region and the target layer 150 that meets the process requirements cannot be obtained.
[0088] In view of this, in this solution, the step of forming the anti-reflective coating 140 may include:
[0089] See Figure 3 , an anti-reflective coating material layer 132 is formed, and the anti-reflective coating material layer 132 is located on the sacrificial layer 130.
[0090] See Figure 4 , a photoresist 134 is formed on the anti-reflective coating material layer 132, and the photoresist 134 exposes the surface of a part of the anti-reflective coating material layer 132.
[0091] Specifically, the photoresist 134 is formed with a graphic opening (not marked in the figure) that exposes a part of the anti-reflective coating material layer 132.
[0092] It should be noted that when the isolation structures 102 and 104 are formed in the substrate 100, the projection of the photoresist 134 on the substrate 100 is located between the adjacent isolation structures 102 and between the adjacent isolation structures 104.
[0093] SeeFigure 5 and Figure 6 Taking the photoresist 134 as a mask, at least two etching processes are adopted to remove the anti-reflection coating material layer 132 exposed by the photoresist 134, and the remaining anti-reflection coating material layer 132 serves as the anti-reflection coating 140.
[0094] Specifically, along the pattern opening, multiple etching processes are adopted to remove the exposed anti-reflection coating material layer 132 to form the anti-reflection coating 140.
[0095] In this embodiment, in each etching process, the etching selectivity ratio can be different.
[0096] By making the etching selectivity ratio different in each etching process, it is possible to achieve precise etching of the anti-reflection coating material layer 132 on the basis of reducing the consumption of the photoresist 134.
[0097] In this way, on the one hand, at the non-etching window, the probability of the anti-reflection coating 140 remaining is significantly reduced, and even the problem of the anti-reflection coating 140 remaining will not occur, and naturally the problem of the remaining processing layer 110 is also reduced or avoided; on the other hand, the retention amount of the photoresist 134 meets the process requirements, so that the top of the sacrificial layer 130 still has a good topography.
[0098] In this embodiment, the at least two etching processes include a first etching process and a second etching process.
[0099] Among them, referring to Figure 5 , in the process of removing the anti-reflection coating material layer 132 by using the first etching process, the anti-reflection coating material layer 132 and the photoresist 134 have a first etching selectivity ratio.
[0100] By making the anti-reflection coating material layer 132 and the photoresist 134 have a first etching selectivity ratio, it is possible to reduce the consumption of the photoresist 134 during the process of removing the anti-reflection coating material layer 132, and improve the topography quality of the bottom of the photoresist 134, and further improve the topography quality of the sacrificial layer 130.
[0101] In a specific embodiment, the first etching selectivity ratio is greater than 50:1.
[0102] In this embodiment, the parameters of the first etching process include: the first etching process is a dry etching process, the process gas includes CF4, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 200 V to 300 V, and the etching time is 15 s to 20 s.
[0103] Among them, by making the gas flow rate 50 sccm to 100 sccm, the flow rate of CF4 is relatively stable, making the etching process smoother, improving the stability of the etching process, which is beneficial to controlling the removal amount of the anti-reflection coating material layer 132.
[0104] By making the etching time 15 s to 20 s, over-etching or under-etching can be avoided, which is beneficial to controlling the removal amount of the anti-reflection coating material layer 132.
[0105] In this embodiment, referring to Figure 5 , by using the first etching process, only the exposed part of the anti-reflection coating material layer 132 with a certain thickness is removed. And during the process of removing a part of the anti-reflection coating material layer 132 with a certain thickness, a part of the photoresist 134 is also consumed.
[0106] For example, the height of the photoresist 134 in the initial state is h1, and after performing the first etching process, the height of the photoresist 134 becomes h2, and h1 is greater than h2.
[0107] Referring to Figure 6 , by using the second etching process, during the process of removing the anti-reflection coating material layer 132, the anti-reflection coating material layer 132 and the sacrificial layer 130 have a second etching selectivity ratio, and the first etching selectivity ratio is different from the second etching selectivity ratio.
[0108] By making the anti-reflection coating material layer 132 and the sacrificial layer 130 have a second etching selectivity ratio, during the process of removing the anti-reflection coating material layer 132, the loss of the sacrificial layer 130 can be reduced, and the morphology quality of the photoresist 134 can be improved, and then the morphology quality of the stacked structure 120 can be improved.
[0109] In a specific embodiment, the second etching selectivity ratio is greater than 50:1.
[0110] In this embodiment, the second etching process is a dry etching process, the process gas includes CL2 and O2, the flow rate of CL2 is 10 sccm to 30 sccm, the flow rate of O2 is 10 sccm to 30 sccm, the atmosphere gas includes He, the flow rate of He is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 100 V to 150 V, and the etching time is 15 s to 25 s.
[0111] Among them, by making the flow rate of CL2 10 sccm to 30 sccm and the flow rate of O2 10 sccm to 30 sccm, the flow rates of CL2 and O2 are relatively stable, making the etching process smoother, improving the stability of the etching process, which is beneficial to controlling the removal amount of the anti-reflection coating material layer 132 and reducing the loss of the sacrificial layer 130.
[0112] By setting the etching time to 15 s to 20 s, over-etching or under-etching can be avoided, which is beneficial to controlling the amount of the anti-reflection coating material layer 132 removed.
[0113] It should be noted that an isolation structure is formed in the substrate 100, and in a region where the surface of the isolation structure is lower than the surface of the active region, a part of the sacrificial layer 130 in this region is also removed when the second etching process is performed.
[0114] For example, referring to Figure 6 , the sacrificial layer 130 located on the isolation structure 104 and on both sides of the anti-reflection coating 140 is removed.
[0115] Referring to Figure 7 , using the anti-reflection coating 140 as a mask, the sacrificial layer 130 and the stacked structure 120 are etched in sequence to expose a part of the surface of the layer 110 to be processed.
[0116] Among them, for the process step of performing etching treatment using the anti-reflection coating 140 as a mask, the description of existing examples can be referred to.
[0117] In some embodiments, before performing the process steps Figure 7 illustrated, in other words, before using the anti-reflection coating 140 as a mask to etch the sacrificial layer 130 and the stacked structure 120 in sequence to expose a part of the surface of the layer 110 to be processed, the forming method further includes:
[0118] Hardening the photoresist 134, and the hardened photoresist 134 is used as a mask.
[0119] That is to say, in the step of exposing a part of the layer 110 to be processed, the photoresist 134 and the anti-reflection coating 140 are used as masks together.
[0120] In some embodiments, by performing the step of hardening the photoresist 134, the structure of the photoresist 134 becomes more stable, so that in subsequent processing, it has better process stability and effect, and the resistance during the etching process is improved.
[0121] In some embodiments, the parameters of the hardening treatment include: the hardening process is plasma treatment, the gas includes HBr, the radio frequency power is 800 W to 1200 W, and the treatment time is 30 s to 50 s.
[0122] By making the hardening treatment time greater than or equal to 30 s, the photoresist 134 can be sufficiently hardened, which increases the etching resistance performance of the photoresist 134; by making the hardening treatment time less than or equal to 50 s, the over-hardening problem of the photoresist 134 will not occur, correspondingly reducing the difficulty of removing the photoresist 134 subsequently and shortening the process duration.
[0123] In some embodiments, after etching the sacrificial layer 130 and the stacked structure 120 and before forming the target layer 150, the forming method further includes:
[0124] Trimming the sidewalls of the sacrificial layer 130 and the sidewalls of the stacked structure 120 to remove a part of the thickness of the sacrificial layer 130 and the stacked structure 120.
[0125] By performing the trimming process, the feature sizes of the sacrificial layer 130 and the stacked structure 120 become smaller, which can reduce the residual problem of the processing layer 110 caused by removing the layer to be processed 110 in the subsequent process, and is beneficial to realizing a target layer with a smaller size under the condition of limited lithography capabilities, which is of great significance for improving process compatibility and integration.
[0126] In some embodiments, the parameters for trimming the sidewalls of the sacrificial layer 130 and the sidewalls of the stacked structure 120 include:
[0127] The trimming gas includes CF4 and CHF3, the flow rate of CF4 is 50 sccm to 100 sccm, the flow rate of CHF3 is 10 sccm to 30 sccm, and the radio frequency power is 400 W to 800 W.
[0128] It should be noted that when performing the trimming process, the feature sizes of the obtained sacrificial layer 130 and the stacked structure 120 should be consistent with the process requirements.
[0129] In some embodiments, after exposing a part of the layer to be processed 110 and before forming the target layer 150, the photoresist 134 is also removed.
[0130] In some embodiments, an ashing process can be used to remove the photoresist 134.
[0131] It should be noted that in the above-mentioned multiple processing schemes, the order can be adjusted according to the process requirements. In a specific embodiment, the photoresist 134 can be hardened first, then the sacrificial layer 130 and the stacked structure 120 are etched in sequence, then the sidewalls of the sacrificial layer 130 and the sidewalls of the stacked structure 120 are trimmed, and finally the photoresist 134 is removed.
[0132] It should be noted that during the process of removing the photoresist 134, the anti-reflection coating 140 is also removed accordingly, so as to expose the top of the sacrificial layer 130. Due to the above solution, the top topography of the sacrificial layer 130 changes less and still has a very high flatness.
[0133] Refer to Figure 8 , using the sacrificial layer 130 as a mask, etch the layer to be processed 110 to form a target layer 150.
[0134] The target layer 150 can be used as a gate structure.
[0135] During the operation of the device, the target layer 150 is used to control the opening and closing of the conductive channel. In this embodiment, the target layer 150 is a polysilicon gate structure, and the polysilicon gate structure may include a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) located on the gate dielectric layer.
[0136] The gate electrode layer is used as an external electrode for electrically connecting the gate structure to an external circuit.
[0137] The material of the gate electrode layer includes one or more of titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), titanium aluminide (TiAl), tungsten (W), aluminum (Al), titanium silicon nitride (TiSiN), and titanium aluminum carbide (TiAlC).
[0138] In this embodiment, the gate electrode layer may include one or both of a work function layer and an electrode layer.
[0139] In this embodiment, the work function layer is used to adjust the threshold voltage of the transistor. For example, when forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the N-type work function layer includes one or more of titanium aluminide and titanium aluminum carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the P-type work function layer includes one or more of titanium nitride, tantalum nitride, and titanium silicon nitride.
[0140] The electrode layer is used to electrically connect to an external circuit. The material of the electrode layer is a conductive material, including one or more of tungsten and aluminum. In this embodiment, the material of the electrode layer is tungsten.
[0141] The gate dielectric layer is used to achieve electrical isolation between the gate electrode layer and the conductive channel.
[0142] In this embodiment, the material of the gate dielectric layer includes one or more of hafnium oxide (HfO2), zirconium oxide (ZrO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), aluminum oxide (Al2O3), silicon dioxide (SiO2), and lanthanum oxide (La2O3).
[0143] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from zirconium oxide (ZrO2), hafnium silicate (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), or aluminum oxide (Al2O3). In other embodiments, the gate dielectric layer may further include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer, or the gate dielectric layer may only include a gate oxide layer.
[0144] In this embodiment, the target layer 150 is taken as an example of a polysilicon gate structure for illustration. In other embodiments, based on actual process requirements, the target layer may also be other types of gate structures, such as: an amorphous silicon gate structure or a metal gate structure.
[0145] In some embodiments, the isolation structure is located on both sides of the target layer 150.
[0146] Next, refer to Figure 8 , after forming the target layer 150, the step of removing the sacrificial layer 130 is further performed.
[0147] In some embodiments, a dry etching process (e.g., a reactive ion etching process) can be used to remove the sacrificial layer 130.
[0148] To solve the above technical problems, the present invention also provides a semiconductor structure.
[0149] Figure 8 is a schematic diagram of a semiconductor structure corresponding to an embodiment of the semiconductor structure of the present invention, wherein the semiconductor structure can be obtained by using the formation method of the semiconductor structure described in any of the above embodiments.
[0150] Combined with Figures 1 to 7 Refer to Figure 8 , the semiconductor structure includes: a substrate 100, a layer to be processed 110 on the substrate 100 (refer to Figure 1 ), and a stacked structure 120 located on the layer to be processed 110; a sacrificial layer 130 (refer to Figure 2 ), located on the stacked structure 120; an anti-reflection coating 140 (refer to Figure 5) exposing the surface of part of the sacrificial layer 130; a target layer 150, located on the substrate 100 and exposing the surface of part of the substrate 100.
[0151] Wherein, the target layer 150 is formed by etching the layer to be processed 110 using the sacrificial layer 130 as a mask, and the exposed surface of part of the layer to be processed 110 is obtained by sequentially etching the sacrificial layer 130 and the stacked structure 120 using the anti-reflection coating 140 as a mask.
[0152] It should be noted that both the sacrificial layer 130 and the anti-reflection coating 140 are intermediate structures, and in an actual product, the sacrificial layer 130 and the anti-reflection coating 140 are not shown.
[0153] Descriptions of the sacrificial layer 130 and the anti-reflection coating 140 can be referred to the foregoing examples.
[0154] In this embodiment, the substrate 100 can provide a process operation basis for the formation process of a semiconductor structure. Among them, the semiconductor structure can include a fin field-effect transistor (FinFET) or a gate-all-around transistor (GAA).
[0155] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium, and the substrate can also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate can be a material suitable for process requirements or easy to integrate.
[0156] In some embodiments, the substrate can also include a substrate, a plurality of discrete fin portions located above the substrate, and an isolation structure located on the substrate exposed by the fin portions. The isolation structure can cover part of the side walls of the fin portions, and the top of the isolation structure is lower than the top of the fin portions.
[0157] For example, referring to Figure 8 , in the step of providing the substrate 100, the substrate 100 further has isolation structures 102 and 104, and the isolation structures 102 and 104 divide the substrate 100 into a plurality of active regions (not marked in the figure).
[0158] In other words, the isolation structure defines the region of the active region, and the substrate 100 between any adjacent isolation structures is the active region, so as to achieve isolation between adjacent devices.
[0159] In some embodiments, the isolation structure is located on both sides of the target layer 150.
[0160] In this embodiment, the materials of the isolation structures 102 and 104 are insulating materials. For example, one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and boron carbonitride nitride.
[0161] In a specific embodiment, the materials of the isolation structures 102 and 104 are silicon oxide.
[0162] In this embodiment, the isolation structure 104 can be a shallow trench isolation structure STI.
[0163] In this embodiment, due to process parameters, actual manufacturing requirements, and the influence of the previous process, the heights of the isolation structures 102 and 104 are not exactly the same.
[0164] For example, in Figure 8 In the structure shown, the height of the isolation structure 102 is higher than that of the isolation structure 104, and there is a height difference between the surface of the isolation structure 102 and the surface of the active region, and there is also a height difference between the surface of the isolation structure 104 and the surface of the active region.
[0165] In a specific embodiment, the surface of the isolation structure 102 is higher than the surface of the active region, while the surface of the isolation structure 104 is lower than the surface of the active region.
[0166] In this way, in the case where there is a height difference between the surface of the isolation structure and the surface of the active region, adopting this solution can reduce the influence brought by the height difference, so that the stacked structure 120 and the target layer 150 have a relatively high topography.
[0167] The stacked structure 120 plays a role in protecting the surface of the target layer 150 and improving the surface flatness.
[0168] In this embodiment, the stacked structure 120 may include: a first hard mask layer 122 and a second hard mask layer 124 located on the first hard mask layer 122.
[0169] Among them, the second hard mask layer 124 serves as the main body of the stacked structure 120, and the thickness of the second hard mask layer 124 is much greater than the height of the first hard mask layer 122.
[0170] In this embodiment, the material of the first hard mask layer 122 includes silicon oxide. The silicon oxide material has good adhesion to the substrate 100, which is beneficial to improving the stability and process treatment effect of subsequent processes; moreover, silicon oxide is a commonly used silicon oxide in semiconductor processes and can improve process compatibility.
[0171] In this embodiment, the material of the second hard mask layer 124 includes silicon nitride.
[0172] The target layer 150 can be used as a gate structure.
[0173] When the device is operating, the target layer 150 is used to control the opening and closing of the conductive channel. In this embodiment, the target layer 150 is a polysilicon gate structure, and the polysilicon gate structure may include a gate dielectric layer (not shown in the figure) and a gate electrode layer (not shown in the figure) located on the gate dielectric layer.
[0174] Among them, for more descriptions of the target layer 150, reference can be made to the foregoing examples.
[0175] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate, on which a layer to be processed is formed, and a stacked structure located on the layer to be processed; Forming a sacrificial layer on the stacked structure; Forming an anti-reflection coating, with the anti-reflection coating exposing a part of the surface of the sacrificial layer; Using the anti-reflection coating as a mask, etching the sacrificial layer and the stacked structure in sequence to expose a part of the surface of the layer to be processed; Using the sacrificial layer as a mask, etching the layer to be processed to form a target layer; Removing the sacrificial layer.
2. The method for forming a semiconductor structure according to claim 1, wherein The step of forming the anti-reflection coating includes: Forming an anti-reflection coating material layer, with the anti-reflection coating material layer located on the sacrificial layer; Forming a photoresist on the anti-reflection coating material layer, with the photoresist exposing a part of the surface of the anti-reflection coating material layer; Using the photoresist as a mask, adopting at least two etching processes to remove the anti-reflection coating material layer exposed by the photoresist, and the remaining anti-reflection coating material layer serves as the anti-reflection coating; Wherein, in each etching process, the etching selectivity is different, and after exposing a part of the layer to be processed and before forming the target layer, the photoresist is also removed.
3. The method for forming a semiconductor structure according to claim 2, wherein The at least two etching processes include a first etching process and a second etching process; When using the first etching process to remove the anti-reflection coating material layer, the anti-reflection coating and the photoresist have a first etching selectivity; When using the second etching process to remove the anti-reflection coating material layer, the anti-reflection coating and the sacrificial layer have a second etching selectivity.
4. The method for forming a semiconductor structure according to claim 3, wherein Satisfying one or more of the following; The parameters of the first etching process include: the first etching process is a dry etching process, the process gas includes CF4, the gas flow rate is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 200 V to 300 V, and the etching time is 15 s to 20 s; The parameters of the second etching process include: the second etching process is a dry etching process, the process gas includes CL2 and O2, the flow rate of CL2 is 10 sccm to 30 sccm, the flow rate of O2 is 10 sccm to 30 sccm, the atmosphere gas includes He, the flow rate of He is 50 sccm to 100 sccm, the radio frequency power is 200 W to 300 W, the bias voltage is 100 V to 150 V, and the etching time is 15 s to 25 s; The first etching selectivity is greater than 50:1; The second etching selectivity is greater than 50:
1.
5. The method for forming a semiconductor structure according to claim 2, characterized in that, Before using the anti-reflection coating as a mask to etch the sacrificial layer and the stacked structure in sequence to expose a part of the surface of the layer to be processed, the forming method further includes: Hardening the photoresist, and the hardened photoresist serves as a mask.
6. The method for forming a semiconductor structure according to claim 5, wherein, The parameters of the hardening treatment include: the hardening process is plasma treatment, the gas includes HBr, the radio frequency power is 800 W to 1200 W, and the treatment time is 30 s to 50 s.
7. The method for forming a semiconductor structure according to claim 1, wherein, After etching the sacrificial layer and the stacked structure and before forming the target layer, the forming method further includes: Trim the sidewalls of the sacrificial layer and the sidewalls of the stacked structure to remove a partial thickness of the sacrificial layer and the stacked structure.
8. The method for forming a semiconductor structure according to claim 7, wherein The parameters for trimming the sidewalls of the sacrificial layer and the sidewalls of the stacked structure include: The trimming gas includes CF4 and CHF3, the flow rate of CF4 is 50 sccm to 100 sccm, the flow rate of CHF3 is 10 sccm to 30 sccm, and the RF power is 400 W to 800 W.
9. The method for forming a semiconductor structure according to claim 1, wherein The stacked structure includes: a first hard mask layer and a second hard mask layer located on the first hard mask layer.
10. The method for forming a semiconductor structure according to claim 1, wherein, In the step of providing a substrate, the substrate further has an isolation structure therein, the isolation structure divides the substrate into a plurality of active regions, and there is a height difference between the surface of the isolation structure and the surface of the active regions; The layer to be processed covers the surface of the isolation structure.
11. A semiconductor structure, characterized in that, Comprising: A substrate having a layer to be processed thereon and a stacked structure located on the layer to be processed; A sacrificial layer located on the stacked structure; An anti-reflection coating exposing a part of the surface of the sacrificial layer; A target layer located on the substrate and exposing a part of the surface of the substrate; Wherein, the target layer is formed by etching the layer to be processed with the sacrificial layer as a mask, and the exposed surface of the part of the layer to be processed is obtained by etching the sacrificial layer and the stacked structure in sequence with the anti-reflection coating as a mask.
12. The semiconductor structure according to claim 11, wherein Meet one or more of the following: The stacked structure includes: a first hard mask layer and a second hard mask layer located on the first hard mask layer; The target layer includes a gate structure; An isolation structure located within the substrate, the isolation structure divides the substrate into a plurality of active regions, and there is a height difference between the surface of the isolation structure and the surface of the active regions.