High performance processor chip package structure and method of packaging

Abstract

The application discloses a high-performance processor chip packaging structure and a packaging method, and belongs to the chip packaging field.The high-performance processor chip packaging structure comprises a high-performance processor chip layer, the high-performance processor chip layer is electrically connected with an intermediate layer, the intermediate layer is electrically connected with a packaging substrate, a heat dissipation cover is arranged above the intermediate layer, an inner heat conduction layer is arranged between the top of the high-performance processor chip layer and the heat dissipation cover, an outer heat conduction layer is arranged outside the heat dissipation cover, the outer heat conduction layer is connected with a heat dissipation fin, and the side of the packaging substrate is provided with an insulating layer and a solder mask layer.The application solves the problem that the chip in the prior art is displaced under the action of external force, thereby affecting the performance of the finally formed packaging structure, realizes the overall sealing and structural reinforcement between the high-performance processor chip layer and the packaging substrate, prevents the high-performance processor chip layer from being displaced on the upper surface of the packaging substrate after installation, and thus ensures the performance of the high-performance processor chip layer packaging structure.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of chip packaging, in particular to a high-performance processor chip packaging structure and a packaging method. BACKGROUND

[0002] At present, the bandwidth and computing power of chips are continuously improved, so that the packaging size of the chips is getting larger and larger.

[0003] A chip packaging method and a chip packaging structure are disclosed in Chinese Patent No. CN119601473A. After the first plastic encapsulation layer is made, the first plastic encapsulation structure is cut to reduce the thermal stress of the first plastic encapsulation layer due to the inconsistent thermal expansion coefficients and to reduce the risk of cracking of the subsequent process carrier board. Then, the cut plastic encapsulation unit is transferred to a second carrier board for second plastic encapsulation processing to form a second plastic encapsulation layer. Since the material of the first plastic encapsulation layer is the same as that of the second plastic encapsulation layer, the thermal stress difference between the first plastic encapsulation layer and the second plastic encapsulation layer is small, further reducing the risk of cracking of the carrier board due to the thermal stress difference, improving the subsequent process production efficiency, and recycling the carrier board to reduce production costs.

[0004] The above-mentioned patent directly bonds the chip to the surface of the substrate before forming the plastic encapsulation layer. During the formation of the plastic encapsulation layer and the subsequent process, the chip will be displaced under the action of external force, thereby affecting the performance of the finally formed packaging structure. Therefore, it does not meet the existing demand, and for this purpose, we propose a high-performance processor chip packaging structure and a packaging method. SUMMARY

[0005] The purpose of the present application is to provide a high-performance processor chip packaging structure and a packaging method, which realizes the overall sealing and structural reinforcement between the high-performance processor chip layer and the packaging substrate. The positioning groove and the positioning protrusion can make the high-performance processor chip layer more firmly installed on the upper surface of the packaging substrate, prevent the high-performance processor chip layer from being displaced on the upper surface of the packaging substrate after installation, thereby ensuring the performance of the high-performance processor chip layer packaging structure, avoiding the influence of excessive temperature on the stability and service life of the high-performance processor chip layer, improving the overall heat dissipation effect while ensuring the stable operation of the high-performance processor chip layer, and solving the problems raised in the above background technology.

[0006] To achieve the above-mentioned purpose, the present application provides the following technical scheme: a high-performance processor chip layer, characterized in that the high-performance processor chip layer is connected with an intermediate layer, the bottom of the intermediate layer is installed with a packaging substrate, the upper part of the intermediate layer is provided with a heat dissipation cover, the top of the high-performance processor chip layer and the heat dissipation cover are provided with an inner heat conduction layer, the outer part of the heat dissipation cover is provided with an outer heat conduction layer, the outer heat conduction layer is provided with a heat dissipation fin, the side edge of the packaging substrate is provided with an insulating layer and a solder mask layer, and the insulating layer and the solder mask layer are inwardly recessed along the side edge of the packaging substrate.

[0007] Preferably, the back surface of the high-performance processor chip layer is provided with a positioning groove, a seed layer is formed on the upper surface of the packaging substrate, a first plastic sealing layer is formed on the upper surface of the seed layer, the first plastic sealing layer and the seed layer are patterned to obtain a positioning bump, the positioning groove on the high-performance processor chip layer is installed on the positioning bump on the packaging substrate, the bottom of the re-wiring layer is provided with a second plastic sealing layer, and the second plastic sealing layer is electrically connected with the high-performance processor chip layer, and the upper surface of the re-wiring layer is provided with a solder ball bump, and the solder ball bump is electrically connected with the re-wiring layer.

[0008] The high-performance processor chip packaging method is applied to the high-performance processor chip packaging structure, and includes the following steps:

[0009] A hole is etched on the packaging substrate by using a DRIE method to manufacture a high-aspect-ratio blind hole structure;

[0010] An insulating layer, a solder mask layer and a seed layer are manufactured on the packaging substrate;

[0011] The packaging substrate is placed in a copper sulfate solution, and the seed layer is used as a cathode for electroplating, and after the electroplating is completed, a first plastic sealing layer is formed on the surface of the seed layer, the first plastic sealing layer and the seed layer are patterned to obtain a positioning bump;

[0012] A high-performance processor chip layer is manufactured, and a positioning groove is formed on the high-performance processor chip layer, and the positioning groove on the high-performance processor chip layer is installed on the positioning bump on the packaging substrate;

[0013] The packaging substrate on the back surface of the high-performance processor chip layer is removed to expose the copper filling, and a vertical interconnection channel is formed on the upper and lower surfaces of the high-performance processor chip layer;

[0014] An epoxy resin layer is formed on the high-performance processor chip layer, and the high-performance processor chip layer is polished according to a preset size and a preset flatness;

[0015] The high-performance processor chip layer is electroplated, and after the electroplating is completed, the high-performance processor chip layer is etched, and after the etching is completed, the second plastic sealing layer is used for product plastic sealing;

[0016] After the plastic sealing is completed, a re-wiring layer is manufactured on the high-performance processor chip layer, and the re-wiring layer is connected with the high-performance processor chip layer.

[0017] Preferably, the high-performance processor chip layer is manufactured, and specifically includes:

[0018] The high-performance processor chip is fixed on the packaging substrate, and the front surface of the high-performance processor chip is used for patching to obtain an upper chip;

[0019] The high-performance processor chip is flip-chip mounted on the back of the high-performance processor chip to obtain a lower chip, and the upper chip and the lower chip are connected in series to obtain a high-performance processor chip layer.

[0020] Preferably, the manufacturing of the re-wiring layer specifically comprises:

[0021] A patterned photoresist layer is formed on the upper surface of the seed layer to define a metal line pattern of the re-wiring layer (12), a metal line layer is formed on the upper surface of the seed layer covered by the photoresist layer according to the metal line pattern, and a copper plating area is exposed;

[0022] The copper is plated on the exposed copper plating area to form a conductive layer, and the conductive layer is connected to the pads of the high-performance processor chip layer and external pins;

[0023] The photoresist is stripped, and after the photoresist is stripped, the excess metal in the metal line layer is removed by wet etching, and the metal under the metal line pattern is retained to form a metal wiring layer;

[0024] The metal wiring layer is subjected to plasma etching, and after the etching is completed, a dielectric layer is coated on the redistribution layer;

[0025] The above steps are repeated, and the photoresist, plating, etching, and passivation of each redistribution layer are sequentially completed, and finally the metal line layer is encapsulated by a protective layer, the bonding wire is bonded to the protective layer, and the bonding wire is electrically led out to obtain a re-wiring layer.

[0026] Preferably, the manufacturing of the seed layer specifically comprises: forming a seed layer on the upper surface of the packaging substrate, and etching the seed layer, and after the etching is completed, a patterned seed layer is formed, and the patterned seed layer is connected to the electrodes of the high-performance processor chip layer.

[0027] Preferably, the manufacturing of the sidewall insulation layer specifically comprises: forming a uniform thin film of silicon dioxide on the sidewalls and the surface of the packaging substrate by chemical vapor deposition, and designing the thin film into a structure that is inwardly recessed to form a sidewall insulation layer.

[0028] Preferably, the solder resist layer is composed of resin, hardener, filler, dye, and ultraviolet reactive substance, and is formed on the upper surface of the insulation layer by photoresist coating, ultraviolet exposure, and chemical development technology, and the solder resist layer is inwardly recessed along the side edges of the packaging substrate.

[0029] Preferably, after the epoxy resin is coated, the high-performance processor chip is subjected to heat dissipation optimization, the thickness and size of the epoxy resin coating at each position after the heat dissipation optimization are determined, and during the polishing of the high-performance processor chip layer, adaptive polishing control is performed on different positions according to the thickness and size of the epoxy resin coating; wherein the heat dissipation optimization specifically comprises:

[0030] Collecting temperature data of each position on the surface of the high-performance processor chip layer by using an infrared thermal imager at a frequency of no less than 10 frames per second;

[0031] Drawing a temperature curve of each position according to the temperature data of each position, and performing temperature change analysis through the temperature curve to obtain the temperature change of each position;

[0032] According to the temperature change, combining the thermal physical properties of the material, the epoxy resin covering thickness of each position after optimization is obtained by implementing the epoxy resin covering thickness optimization.

[0033] Preferably, during the packaging process, the high-performance processor chip layer is subjected to thermal stress optimization, specifically including:

[0034] A thermal stress optimization model for chip packaging is constructed based on neural network technology for a pre-set chip packaging thermal stress model;

[0035] Thermal stress test data of past chip packaging is obtained for learning and training of the thermal stress optimization model, and after the training reaches a predetermined target, a trained thermal stress optimization model is obtained;

[0036] An embedded FBG optical fiber sensor is used to monitor the thermal stress change of chip packaging in real time, and the trained thermal stress optimization model is used to control and adjust the packaging process parameters;

[0037] A Bayesian optimization algorithm is used to determine the thermal stress uniformity index of chip packaging, and the thermal stress uniformity index is compared with a pre-set uniformity threshold value, if the thermal stress uniformity index is greater than the uniformity threshold value, the temperature control strategy of chip packaging is adjusted accordingly to realize the thermal stress uniformity control of chip packaging.

[0038] Compared with the prior art, the beneficial effects of the present application are:

[0039] The present application forms a first plastic sealing layer on the seed layer, realizes the overall sealing and structural reinforcement between the high-performance processor chip layer and the packaging substrate, makes the high-performance processor chip layer more firmly installed on the upper surface of the packaging substrate, prevents the high-performance processor chip layer from shifting on the upper surface of the packaging substrate after installation, thereby ensuring the performance of the high-performance processor chip layer packaging structure, the heat dissipation efficiency can be significantly improved by setting the heat dissipation cover, the inner heat conduction layer and the outer heat conduction layer, the stability and service life of the high-performance processor chip layer are avoided due to the high temperature, the inner heat conduction layer is tightly attached to the inner surface of the high-performance processor chip layer and the heat dissipation cover, prevents loosening or falling due to thermal expansion or mechanical vibration, improves the overall heat dissipation effect while ensuring the stable work of the high-performance processor chip layer. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1A high-performance processor chip packaging structure of the present application;

[0041] Figure 2 A packaging substrate cross-sectional view of the high-performance processor chip packaging structure of the present application;

[0042] Figure 3 A high-performance processor chip layer connection diagram of the high-performance processor chip packaging structure of the present application;

[0043] Figure 4 A high-performance processor chip packaging completion diagram of the present application;

[0044] Figure 5 A high-performance processor chip packaging method of the present application.

[0045] In the figure: 1, high-performance processor chip layer; 2, intermediate layer; 3, packaging substrate; 4, heat dissipation cover; 5, inner heat conduction layer; 6, outer heat conduction layer; 7, cavity; 8, heat dissipation fin; 9, insulating layer; 10, solder resist layer; 11, seed layer; 12, re-wiring layer; 13, first plastic packaging layer; 14, positioning groove; 15, second plastic packaging layer. DETAILED DESCRIPTION

[0046] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0047] In order to solve the problem that the prior art directly bonds the chip to the surface of the packaging substrate 3 before forming the plastic packaging layer, and the chip will be displaced under the action of external force when forming the plastic packaging layer and subsequent processes, thereby affecting the performance of the finally formed packaging structure, please refer to Figures 1-3 The present embodiment provides the following technical solutions:

[0048] The high-performance processor chip packaging structure comprises a high-performance processor chip layer 1, an interposer 2 connected to the high-performance processor chip layer 1, a packaging substrate 3 mounted at the bottom of the interposer 2, and the high-performance processor chip layer 1 and the interposer 2 are electrically connected, and the interposer 2 and the packaging substrate 3 are electrically connected. By arranging the interposer 2 on the surface of the packaging substrate 3, the interposer 2 is made of glass, and is connected to the high-performance processor chip layer 1 and the packaging substrate 3 through micro-bumps and C4 bumps. By using the high-precision wiring capability, the interconnection density bottleneck caused by process limitations in the traditional packaging substrate 3 is solved. The high-performance processor chip layer 1 is connected to the packaging substrate 3 through the interposer 2, which not only provides stable mechanical support and ensures the stability of the high-performance processor chip layer 1 during the packaging process, but also prevents damage caused by external forces. The interposer 2 also shortens the wiring length between the high-performance processor chip layer 1 and the packaging substrate 3, significantly improves the signal transmission efficiency, reduces the signal delay, thereby reducing the noise and power consumption. A heat dissipation cover 4 is arranged above the interposer 2, and a cavity 7 is arranged between the heat dissipation cover 4 and the interposer 2. The high-performance processor chip layer 1 is arranged in the cavity 7. An inner heat conduction layer 5 is arranged between the top of the high-performance processor chip layer 1 and the heat dissipation cover 4. An outer heat conduction layer 6 is arranged outside the heat dissipation cover 4. A heat dissipation fin 8 is arranged on the outer heat conduction layer 6. An insulating layer 9 and a solder resist layer 10 are arranged on the side of the packaging substrate 3, and the insulating layer 9 and the solder resist layer 10 are inwardly recessed along the side of the packaging substrate 3. The solder resist layer 10 extends to the outside of the insulating layer 9, covers the insulating layer 9 and is combined with the packaging substrate 3, which can completely seal and protect the insulating layer 9, slow down the erosion of water vapor and the like to the insulating layer 9. By arranging the insulating layer 9 and the solder resist layer 10 which are inwardly recessed along the side of the packaging substrate 3, the cutting of the insulating layer 9 and the solder resist layer 10 during the cutting and separation of the chips is avoided, thereby avoiding the formation of micro-cracks. By arranging the heat dissipation cover 4, the inner heat conduction layer 5 and the outer heat conduction layer 6, the heat dissipation efficiency can be significantly improved, and the inner heat conduction layer 5 can fill the small gaps and uneven surfaces between the high-performance processor chip layer 1 and the heat dissipation cover 4, forming a good heat conduction channel, thereby greatly reducing the contact thermal resistance, so that the heat can be more effectively transferred to the heat sink and dissipated to the air, avoiding the influence of high temperature on the stability and service life of the high-performance processor chip layer 1.

[0049] The inner heat conduction layer 5 is tightly attached to the inner surface of the high-performance processor chip layer 1 and the heat dissipation cover 4, preventing loosening or falling off caused by thermal expansion or mechanical vibration, thereby ensuring stable operation of the high-performance processor chip layer 1, reducing performance fluctuations caused by temperature changes, and reducing the working temperature of the high-performance processor chip layer 1 by improving heat dissipation efficiency, thereby reducing material aging and other physical damage caused by high temperature and prolonging the overall service life of the device. The heat dissipation fins 8 can effectively conduct the heat generated by the high-performance processor chip layer 1 away, and can also reduce the thermal resistance during heat transfer, making the heat transfer to the external environment more smooth, improving the overall heat dissipation effect.

[0050] The back surface of the high-performance processor chip layer 1 is provided with a positioning groove 14, a seed layer 11 is formed on the upper surface of the packaging substrate 3, and a first plastic sealing layer 13 is formed on the upper surface of the seed layer 11. By forming the first plastic sealing layer 13 on the seed layer 11, the overall sealing and structural reinforcement between the high-performance processor chip layer 1 and the packaging substrate 3 are achieved. The positioning groove 14 and the positioning bump can make the high-performance processor chip layer 1 more firmly installed on the upper surface of the packaging substrate 3, preventing the high-performance processor chip layer 1 from shifting on the upper surface of the packaging substrate 3 after installation, thereby ensuring the performance of the high-performance processor chip layer 1 packaging structure. The first plastic sealing layer 13 and the seed layer 11 are patterned to obtain the positioning bump. The positioning groove 14 on the high-performance processor chip layer 1 is installed on the positioning bump on the packaging substrate 3. The bottom of the re-wiring layer 12 is provided with a second plastic sealing layer 15, and the second plastic sealing layer 15 is electrically connected with the high-performance processor chip layer 1. The upper surface of the re-wiring layer 12 is provided with a solder ball bump, and the solder ball bump is electrically connected with the re-wiring layer 12.

[0051] Please refer to Figures 4-5 , the high-performance processor chip packaging method is applied to the high-performance processor chip packaging structure, which comprises the following steps:

[0052] A DRIE method is used to etch holes on the packaging substrate 3 to produce a high-aspect-ratio blind hole structure;

[0053] An insulating layer 9, a solder mask layer 10 and a seed layer 11 are made on the packaging substrate 3;

[0054] The packaging substrate 3 is placed in a copper sulfate solution, and the seed layer 11 is used as the cathode for electroplating. After electroplating is completed, a first plastic sealing layer 13 is formed on the surface of the seed layer 11. The first plastic sealing layer 13 and the seed layer 11 are patterned to obtain the positioning bump.

[0055] A high-performance processor chip layer 1 is made, and a positioning groove 14 is formed on the high-performance processor chip layer 1. The positioning groove 14 on the high-performance processor chip layer 1 is installed on the positioning bump of the packaging substrate 3;

[0056] Remove the excess packaging substrate 3 from the back of the high-performance processor chip layer 1, expose the copper filling, and form vertical interconnection channels on the upper and lower surfaces of the high-performance processor chip layer 1;

[0057] Cover the high-performance processor chip layer 1 with a layer of epoxy resin, and polish the high-performance processor chip layer 1 to the desired size and flatness;

[0058] Electroplate the high-performance processor chip layer 1, and after electroplating, etch the high-performance processor chip layer 1, and after etching, use the second plastic encapsulation layer 15 to encapsulate the finished product;

[0059] After plastic encapsulation, make a rewiring layer 12 on the high-performance processor chip layer 1 and connect the rewiring layer 12 to the high-performance processor chip layer 1. The rewiring layer 12 is used for electrical lead-out of the high-performance processor chip layer 1.

[0060] The high-performance processor chip layer 1 is made, specifically including:

[0061] Fix the high-performance processor chip on the packaging substrate 3, with the front of the high-performance processor chip for surface mounting, to obtain an upper chip;

[0062] Flip-chip with the back of the high-performance processor chip to obtain a lower chip, and connect the upper chip and the lower chip in series to obtain the high-performance processor chip layer 1.

[0063] The rewiring layer 12 is made, specifically including:

[0064] Form a patterned photoresist layer on the upper surface of the seed layer 11, define the metal wire pattern of the rewiring layer (12), and form a metal wire layer on the upper surface of the seed layer 11 covered by the photoresist layer according to the metal wire pattern, exposing the area to be electroplated;

[0065] Electroplate copper in the exposed area to be electroplated to form a conductive layer, connecting the pads of the high-performance processor chip layer 1 and the external pins;

[0066] Strip the photoresist, and after stripping the photoresist, remove the excess metal in the metal wire layer using wet etching, leaving the metal under the metal wire pattern to form a metal wiring layer;

[0067] Plasma etch the metal wiring layer to eliminate sharp corners and optimize line spacing and integration, and after etching, coat a dielectric layer on the redistribution layer;

[0068] Repeat the above steps, and each redistribution layer is sequentially completed with photoetching, electroplating, etching, and passivation treatment. Finally, encapsulate the metal wire layer with a protective layer, bond the bonding wire with the protective layer, and perform electrical lead-out to obtain the rewiring layer 12.

[0069] The preparation of the seed layer 11 specifically includes: forming the seed layer 11 on the upper surface of the packaging substrate 3, and etching the seed layer 11 to form a patterned seed layer 11 after the etching is completed, and the patterned seed layer 11 is connected to the electrode of the high-performance processor chip layer 1.

[0070] The production of the sidewall insulating layer 9 specifically includes: forming a uniform thin film of silicon dioxide on the sidewall and surface of the packaging substrate 3 through chemical vapor deposition, and designing the thin film to have an inwardly indented structure to form the sidewall insulating layer 9.

[0071] The solder resist layer 10 is composed of resin, hardener, filler, dye and ultraviolet reactive substance. Photoresist coating, ultraviolet exposure and chemical development technology are used to form the solder resist layer 10 on the upper surface of the insulating layer 9, and the solder resist layer 10 is indented inward along the side of the packaging substrate 3.

[0072] In summary, the high-performance processor chip packaging structure of the present invention forms a first plastic sealing layer 13 on the seed layer 11 to achieve overall sealing and structural reinforcement between the high-performance processor chip layer 1 and the packaging substrate 3. The positioning groove 14 and the positioning bump can make the high-performance processor chip layer 1 more firmly installed on the upper surface of the packaging substrate 3, and prevent the high-performance processor chip layer 1 from shifting on the upper surface of the packaging substrate 3 after installation, thereby ensuring the performance of the packaging structure of the high-performance processor chip layer 1. By setting the heat dissipation cover 4, the inner heat conductive layer 5 and the outer heat conductive layer 6, the heat dissipation efficiency can be significantly improved. At the same time, the inner heat conductive layer 5 can fill the tiny gaps and uneven surfaces between the high-performance processor chip layer 1 and the heat dissipation cover 4 to form a good heat conduction channel, thereby greatly reducing the contact thermal resistance, so that heat can be more effectively transferred to the radiator and dissipated. to the air to avoid excessive temperature affecting the stability and life of the high-performance processor chip layer 1. The inner heat-conducting layer 5 is tightly fitted to the inner surface of the high-performance processor chip layer 1 and the heat dissipation cover 4 to prevent loosening or falling off due to thermal expansion or mechanical vibration, thereby ensuring the stable operation of the high-performance processor chip layer 1 and reducing performance fluctuations caused by temperature changes. By improving the heat dissipation efficiency, the operating temperature of the high-performance processor chip layer 1 can be reduced, thereby reducing material aging and other physical damage caused by high temperature, and extending the overall service life of the device. The heat sink 8 can effectively and quickly conduct the heat generated by the high-performance processor chip layer 1, and can also reduce the thermal resistance in the heat transfer process, so that the heat can be more smoothly transferred to the external environment, thereby improving the overall heat dissipation effect and ensuring the stable operation of the high-performance processor chip layer 1.

[0073] On the basis of the foregoing embodiment, after the epoxy resin is covered, heat dissipation optimization is performed on the high-performance processor chip, the thickness size of the epoxy resin covering at each position after heat dissipation optimization is determined, and adaptive polishing control is performed on different positions according to the thickness size of the epoxy resin covering when polishing the high-performance processor chip layer; wherein the heat dissipation optimization specifically includes:

[0074] The infrared thermal imager is used to collect temperature data of each position on the surface of the high-performance processor chip at a frequency of not less than 10 frames per second;

[0075] According to the temperature data of each position, a temperature curve of each position is drawn, and temperature change analysis is performed on the temperature curve to obtain the temperature change of each position.

[0076] According to the temperature change, combined with the thermal physical properties of the material, the thickness optimization of the epoxy resin covering is performed to obtain the thickness size of the epoxy resin covering at each position after optimization.

[0077] Specifically, the thermal physical properties of the material include heat transfer coefficient, specific heat capacity and other parameters. According to the thermal physical properties of the chip packaging material, the thickness size of the epoxy resin covering at each position of the chip after optimization is determined by performing heat dissipation optimization, and adaptive polishing control is performed on different positions according to the thickness size of the epoxy resin covering. It is beneficial to optimize the epoxy resin at each position of the chip packaging considering heat dissipation, so that the packaging is more reasonable, the heat dissipation effect of the packaged chip is better, which is beneficial to improve the performance of the chip, reduce the failure rate of the chip and prolong the service life of the chip.

[0078] On the basis of the foregoing embodiment, during the packaging process, the high-performance processor chip layer 1 is subjected to thermal stress optimization, specifically including:

[0079] For the pre-set chip packaging thermal stress model, a thermal stress optimization model of chip packaging is constructed based on neural network technology; the pre-set chip packaging thermal stress model is as follows:

[0080]

[0081] Wherein, is the thermal stress of the chip packaging, is the Young's modulus, is the coefficient of thermal expansion (CTE) of the chip packaging material, is the temperature change in the chip packaging, is the Poisson's ratio;

[0082] Obtain the thermal stress test data of the past chip packaging, and use the thermal stress test data for learning and training of the thermal stress optimization model, and obtain the trained thermal stress optimization model after the training reaches the predetermined target;

[0083] The FBG optical fiber sensor is embedded to monitor the thermal stress change of the chip packaging in real time, and the trained thermal stress optimization model is applied to control and adjust the packaging process parameters;

[0084] The Bayesian optimization algorithm is used to determine the thermal stress uniformity index of the chip packaging:

[0085]

[0086] Wherein, is the number of times of collecting the thermal stress data of the chip packaging in real time, is the thermal stress data collected for the time, is the mean value of the collected thermal stress data, is the thermal stress uniformity index of the chip packaging;

[0087] The thermal stress uniformity index is compared with the preset uniformity threshold value, and if the thermal stress uniformity index is greater than the uniformity threshold value, the temperature control strategy of the chip packaging is adjusted to realize the thermal stress uniformity control of the chip packaging.

[0088] Specifically, for the pre-set chip packaging thermal stress model, a thermal stress optimization model is established, and after training, the packaging process parameters are controlled and adjusted, so that the thermal stress uniformity of the chip packaging is better, which is conducive to ensuring the consistency of the quality of the packaged chip, improving the yield, reducing the chip failure rate, and prolonging the service life of the chip. The algorithm used in the scheme has strong practicability, small calculation amount, and less resource occupation during operation, which can ensure the real-time performance of the chip packaging process control.

[0089] It should be noted that in this paper, relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment.

[0090] Although the embodiments of the present application have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the present application.

Claims

1. High-performance processor chip package structure, comprising a high-performance processor chip layer (1), characterized in that The high-performance processor chip layer (1) is connected with an interposer (2), the bottom of the interposer (2) is provided with a packaging substrate (3), the top of the interposer (2) is provided with a heat dissipation cover (4), the top of the high-performance processor chip layer (1) is provided with an inner heat conduction layer (5) between the high-performance processor chip layer (1) and the heat dissipation cover (4), the outer part of the heat dissipation cover (4) is provided with an outer heat conduction layer (6), the outer heat conduction layer (6) is provided with a heat dissipation fin (8), the side of the packaging substrate (3) is provided with an insulating layer (9) and a solder resist layer (10), and the insulating layer (9) and the solder resist layer (10) are inwardly recessed along the side of the packaging substrate (3). The back of the high-performance processor chip layer (1) is provided with a positioning groove (14), the upper surface of the packaging substrate (3) is formed with a seed layer (11), the upper surface of the seed layer (11) is formed with a first plastic sealing layer (13), the first plastic sealing layer (13) and the seed layer (11) are patterned to obtain a positioning bump, the positioning groove (14) on the high-performance processor chip layer (1) is mounted on the positioning bump on the packaging substrate (3), the bottom of the re-wiring layer (12) is provided with a second plastic sealing layer (15), and the second plastic sealing layer (15) is electrically connected with the high-performance processor chip layer (1), the upper surface of the re-wiring layer (12) is provided with a solder ball bump, and the solder ball bump is electrically connected with the re-wiring layer (12).

2. A method for packaging a high performance processor chip, applied in the high performance processor chip packaging structure as claimed in claim 1, characterized in that: The method comprises the following steps: A hole is etched on the packaging substrate (3) by using a DRIE method to form a high-aspect-ratio blind hole structure; An insulating layer (9), a solder resist layer (10) and a seed layer (11) are formed on the packaging substrate (3); The packaging substrate (3) is placed in a copper sulfate solution, and the seed layer (11) is used as a cathode for electroplating. After electroplating, a first plastic sealing layer (13) is formed on the surface of the seed layer (11). The first plastic sealing layer (13) and the seed layer (11) are patterned to obtain a positioning bump. A high-performance processor chip layer (1) is manufactured, and a positioning groove (14) is formed on the high-performance processor chip layer (1). The positioning groove (14) on the high-performance processor chip layer (1) is mounted on the positioning bump on the packaging substrate (3). The packaging substrate (3) on the back of the high-performance processor chip layer (1) is removed to expose the copper filling and form a vertical interconnection channel on the upper and lower surfaces of the high-performance processor chip layer (1). An epoxy resin layer is formed on the high-performance processor chip layer (1), and the high-performance processor chip layer (1) is polished according to the preset size and flatness. The high-performance processor chip layer (1) is electroplated, and after electroplating, the high-performance processor chip layer (1) is etched. After etching, the second plastic sealing layer (15) is used for product plastic sealing. After plastic sealing, a re-wiring layer (12) is formed on the high-performance processor chip layer (1), and the re-wiring layer (12) is connected with the high-performance processor chip layer (1). The re-wiring layer (12) is used for electrical lead-out of the high-performance processor chip layer (1).

3. The high performance processor chip packaging method of claim 2, wherein: The high-performance processor chip layer (1) is manufactured, and specifically comprises: Fixing the high-performance processor chip on the packaging substrate (3), and mounting the high-performance processor chip by the front surface of the high-performance processor chip to obtain an upper chip; Mounting the high-performance processor chip by the back surface of the high-performance processor chip to obtain a lower chip, connecting the upper chip and the lower chip in series to obtain a high-performance processor chip layer (1).

4. The high performance processor chip packaging method of claim 2, wherein: The manufacturing of the re-wiring layer (12) specifically includes: forming a patterned photoresist layer on the upper surface of the seed layer (11) to define a metal wire pattern of the re-wiring layer (12), forming a metal wire layer on the upper surface of the seed layer (11) covered by the photoresist layer according to the metal wire pattern to expose a region to be electroplated; electroplating copper on the exposed electroplated region to form a conductive layer, connecting the pads of the high-performance processor chip layer (1) and external pins; peeling off the photoresist, and after peeling off the photoresist, removing the excess metal in the metal wire layer by wet etching to retain the metal under the metal wire pattern to form a metal wiring layer; performing plasma etching on the metal wiring layer to form a redistribution layer, and after etching, coating a dielectric layer on the redistribution layer; repeating the above steps, and sequentially completing photoetching, electroplating, etching and passivation treatment for each redistribution layer to finally encapsulate the metal wire layer by the protective layer, bond the bonding wire with the protective layer, and electrically lead out to obtain the re-wiring layer (12).

5. The high performance processor chip packaging method of claim 2, wherein: The manufacturing of the seed layer (11) specifically includes: forming a seed layer (11) on the upper surface of the packaging substrate (3), and etching the seed layer (11), and after etching, forming a patterned seed layer (11), and the patterned seed layer (11) is connected with the electrodes of the high-performance processor chip layer (1).

6. The high performance processor chip packaging method of claim 2, wherein: The manufacturing of the insulating layer (9) specifically includes: forming a uniform thin film of silicon dioxide on the sidewall and surface of the packaging substrate (3) by chemical vapor deposition, and designing the thin film into a structure that is inwardly recessed to form the insulating layer (9).

7. The high performance processor chip package method of claim 2, wherein: The solder resist layer (10) is composed of resin, hardener, filler, dye and ultraviolet reactive substance, and is formed on the upper surface of the insulating layer (9) by using photoresist coating, ultraviolet exposure and chemical development technology, and the solder resist layer (10) is inwardly recessed along the side edge of the packaging substrate (3).

8. The high performance processor chip package method of claim 2, wherein: After covering the epoxy resin, heat dissipation optimization is performed on the high-performance processor chip, the thickness size of the epoxy resin covering at each position after heat dissipation optimization is determined, and during polishing of the high-performance processor chip layer (1), adaptive polishing control is performed on different positions according to the thickness size of the epoxy resin covering; wherein the heat dissipation optimization specifically includes: using an infrared thermal imager to collect temperature data of each position on the surface of the high-performance processor chip at a frequency of not less than 10 frames per second; drawing a temperature curve of each position according to the temperature data of each position, and analyzing the temperature change of each position through the temperature curve to obtain the temperature change of each position; combining the thermal physical properties of the material according to the temperature change, and performing epoxy resin covering thickness optimization to obtain the thickness size of the epoxy resin covering at each position after optimization.

9. The high performance processor chip package method of claim 2, wherein: During the packaging process, heat stress optimization is performed on the high-performance processor chip layer (1), specifically including: A chip packaging thermal stress optimization model is constructed based on a neural network technology for a preset chip packaging thermal stress model; Thermal stress test data of previous chip packaging is acquired for learning and training of the thermal stress optimization model, and after the training reaches a predetermined target, a trained thermal stress optimization model is obtained; An embedded FBG optical fiber sensor is adopted to monitor the thermal stress change of the chip packaging in real time, and the trained thermal stress optimization model is applied to control and adjust the packaging process parameters; A Bayesian optimization algorithm is adopted to determine a thermal stress uniformity index of the chip packaging, and the thermal stress uniformity index is compared with a preset uniformity threshold value, and if the thermal stress uniformity index is greater than the uniformity threshold value, the temperature control strategy of the chip packaging is adjusted to realize the thermal stress uniformity control of the chip packaging.

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