Configuration method, device, equipment and medium for direct current filter of symmetric monopole LCC-HVDC system

Abstract

The invention relates to the field of high-voltage direct-current power transmission, in particular to a direct-current filter configuration method, device, equipment and medium of a symmetric single-pole LCC-HVDC system, and the method comprises the steps: obtaining a topological structure of the symmetric single-pole LCC-HVDC system, considering the distributed capacitance of a direct-current power transmission line to the ground, and determining a harmonic current circulation path of the direct-current side of a converter of an inverter station; determining the frequency and the effective value of a harmonic component on the direct-current power transmission line through the harmonic current circulation path; and according to the times of the harmonic components and the effective values thereof, respectively arranging direct-current filters with corresponding times at the sending end and the receiving end. Through the above direct-current filter configuration scheme, the problem that the direct-current side harmonic distribution characteristics of the HVDC system in a symmetrical single-pole wiring mode are greatly different from those of a traditional symmetrical double-pole HVDC system is solved. Under steady-state operation, the ratio of the effective value of the harmonic current to the rated current is well controlled, and harmonic waves at a direct-current outlet of the rectification side can be filtered out.

Description

Technical Field

[0001] The present invention relates to the field of high - voltage direct - current (HVDC) power transmission, and particularly to a method, device, equipment, and medium for configuring a DC filter in a symmetric monopolar LCC - HVDC system. Background Art

[0002] With the rapid growth of power supply capacity, electricity demand, and the increasing tension of resources and energy, as well as the urgent need for environmental protection, it is necessary to build a large number of new transmission lines or transform existing transmission lines to significantly improve the transmission capacity of key sections of the power grid. However, due to terrain and natural obstacles, it is extremely difficult to develop key channel resources. Making full use of the transformation of key transmission channels within the existing regional power grid to build an "embedded" high - voltage direct - current (LCC - HVDC, Line - Commutated Conveter - High - Voltage DC) power transmission system is an economic and feasible solution.

[0003] Compared with the conventional extra - high - voltage direct - current (UHVDC) power transmission system using a symmetric bipolar topology, the "embedded" HVDC project is more suitable for adopting a symmetric monopolar topology structure with only the inverter - side station grounded. However, directly applying the DC filter configuration of the symmetric UHVDC system to the symmetric monopolar system may have adaptability problems.

[0004] The information disclosed in this background - art section is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or any form of implication that this information constitutes prior art known to those skilled in the art. Summary of the Invention

[0005] The present invention provides a method, device, equipment, and medium for configuring a DC filter in a symmetric monopolar LCC - HVDC system, thus effectively solving the problems in the background art.

[0006] To achieve the above - mentioned purpose, the technical solution adopted by the present invention is as follows: A method for configuring a DC filter in a symmetric monopolar LCC - HVDC system, where the symmetric monopolar LCC - HVDC system is a bipolar 12 - pulse converter, and the method includes the following steps:

[0007] Obtain the topological structure of the symmetric monopolar LCC - HVDC system, consider the distributed capacitance of the DC transmission line to the ground, and determine the harmonic current circulation path on the DC side of the inverter - station converter;

[0008] Determine the order and effective value of the harmonic components on the DC transmission line through the harmonic current circulation path;

[0009] Set DC filters of corresponding orders at the sending end and the receiving end respectively according to the order of the harmonic components and the effective value of the corresponding order.

[0010] Further, when DC filters of corresponding numbers are respectively arranged at the sending end and the receiving end, it further includes: connecting the DC filter at the sending end between the positive and negative buses, and connecting the DC filter at the sending end between the bus and the ground.

[0011] Further, two groups of DC filters are arranged at the sending end.

[0012] Further, it further includes:

[0013] When the inter-station communication is abnormal, if two groups of DC filters are lost simultaneously at the sending end, the DC power transmission system is blocked; if one group of DC filter is lost at the sending end and one group of DC filter is lost at the receiving end, the DC power transmission system is not blocked.

[0014] Further, it further includes:

[0015] Collecting data including harmonic current, voltage signals and current parameter values of the filter;

[0016] Denosing and preprocessing the collected original signals, and extracting the amplitude, frequency and phase information of each order harmonic component;

[0017] Constructing a discrete-time state space model of the filter and its compensation system with the amplitude, frequency and phase information of each order harmonic component;

[0018] Setting a prediction time domain and a control time domain, and predicting the states within a set future step length by using the discrete-time state space model;

[0019] Designing a cost function considering state deviation and control input variation as the objective of the model predictive control MPC optimization problem;

[0020] Setting the upper and lower limits of the control input and the state according to the filter hardware and system safety requirements;

[0021] Obtaining the current state and real-time harmonic data at each sampling moment; calculating the state trajectory within a set future step length by using the discrete-time state space model;

[0022] Online solving the above-mentioned constrained MPC optimization problem to obtain an optimal control sequence; updating the filter parameters according to the control output;

[0023] After the new filter parameters are adjusted, continue to collect system data, and update the state according to the state trajectory to form a closed-loop feedback.

[0024] Further, the constructing a discrete-time state space model of the filter and its compensation system with the amplitude, frequency and phase information of each order harmonic component includes:

[0025] Construct a state vector with the amplitude, frequency, and phase information of each harmonic component;

[0026] Construct a state equation and an output equation with the state vector;

[0027] Construct the discrete-time state space model with the state equation and the output equation.

[0028] Further, the state equation is:

[0029] x(k + 1) = Ax(k) + Bu(k);

[0030] The output equation is:

[0031] y(k) = C x(k) + Du(k);

[0032] Where:

[0033]

[0034] In the formula, x(k) is the state vector, describing the state of the system at time k, x(k + 1) is the state vector at time k + 1, u(k) is the control input vector, y(k) is the output value at time k, ΔC(k) is the capacitance adjustment amount, ΔL(k) is the inductance adjustment amount, ΔA comp (k) is the compensation amplitude adjustment amount, and A, B, C, D are the system model matrices respectively, determined by the physical characteristics of the system.

[0035] Further, in the setting of the prediction time domain and the control time domain, and using the discrete-time state space model to predict the state within the future set number of steps, the discrete-time state space model is:

[0036]

[0037] In the formula, N p is the prediction time domain, x(k + i|k) is the predicted future i-th step system state at time k, u(k + i|k) is the predicted future i-th step control input at time k, and j is a parameter and ranges from 0 to i - 1.

[0038] Further, the cost function is:

[0039]

[0040] In the formula, J is the cost, x ref is the target state vector, representing the state under the ideal state; u refis the reference control input, corresponding to the initial parameters or nominal parameters of the filter; Q is the state error weighting matrix, reflecting the importance attached by the system to harmonic suppression; R is the control input change weighting matrix, restricting the amplitude of filter parameter adjustment; x(k) is the state vector, describing the state of the system at time k, x(k + 1) is the state vector at time k + 1, u(k) is the control input vector, N p is the prediction time domain; T is the total number of prediction steps.

[0041] Furthermore, the setting of the upper and lower limits of the control input and the state includes:

[0042] u min ≤u(k + i|k)≤u max , i = 0, 1,..., N c -1;

[0043] x min ≤x(k + i|k)≤x max , i = 1, 2,..., N p ;

[0044] In the formula, u min , u max are respectively the minimum and maximum values of the filter parameter adjustment; x min , x max are respectively the minimum and maximum values of the safe operating range, N c is the control time domain.

[0045] Furthermore, the updating of the filter parameters according to the control output includes:

[0046] C(k + 1) = C(k) + ΔC(k);

[0047] L(k + 1) = L(k) + ΔL(k);

[0048] A comp (k + 1) = A comp (k) + ΔA comp (k);

[0049] In the formula, C(k) is the capacitance parameter at time k, C(k + 1) is the capacitance parameter at time k + 1; L(k) is the inductance parameter at time k, L(k + 1) is the inductance parameter at time k + 1; Acomp(k) is the compensation amplitude parameter at time k, Acomp(k + 1) is the compensation amplitude parameter at time k + 1.

[0050] The present invention further includes a DC filter configuration device for a symmetrical monopolar LCC-HVDC system, including:

[0051] An acquisition unit for acquiring the topological structure of a symmetrical monopole LCC-HVDC system, considering the distributed capacitance of the DC transmission line to the ground, and determining the harmonic current circulation path on the DC side of the inverter converter;

[0052] A harmonic calculation unit for determining the order of the harmonic components on the DC transmission line and the effective value of the corresponding order through the harmonic current circulation path;

[0053] A DC filter unit for respectively setting DC filters of corresponding orders at the sending end and the receiving end according to the order of the harmonic components and their effective values.

[0054] The present invention further includes a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the method as described above is implemented.

[0055] The present invention further includes a storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method as described above is implemented.

[0056] The beneficial effects of the present invention are as follows: Through the DC filter configuration scheme, the present invention solves the problem that the harmonic distribution characteristics on the DC side of the HVDC system under the symmetrical monopole connection mode are quite different from those of the traditional symmetrical bipolar HVDC system. Through the harmonic current circulation path, the order of the harmonic components on the DC transmission line and their effective values are determined; according to the order of the harmonic components and their effective values, DC filters of corresponding orders are respectively set at the sending end and the receiving end. Under steady-state operation, the ratio of the effective value of the harmonic current to the rated current is well controlled, and the harmonics at the DC outlet of the rectifier side can be filtered out. Description of the Drawings

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0058] Figure 1 It is a flowchart of the method in Embodiment 1;

[0059] Figure 2 It is a structural schematic diagram of the device in Embodiment 1;

[0060] Figure 3 It is a schematic diagram of the circulation loop of the sixth harmonic in the symmetrical monopole topology high-voltage DC system in Embodiment 2;

[0061] Figure 4It is the equivalent circuit of the sixth harmonic in the symmetric monopole topology high-voltage DC system in Embodiment 2;

[0062] Figure 5 It is a schematic diagram of different DC filter wiring methods adopted at the sending end and the receiving end in Embodiment 2;

[0063] Figure 6 It is the steady-state voltage of the negative pole fault in the symmetric monopole system under different grounding conditions of the transition resistance in Embodiment 2;

[0064] Figure 7 It is a schematic diagram when two groups of DC filters at the inverter station are withdrawn during the communication fault in Embodiment 2;

[0065] Figure 8 It is a schematic diagram of the structure of the computer device of the present invention. Detailed implementation manners

[0066] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0067] Embodiment 1:

[0068] As Figure 1 shown: A method for configuring a DC filter for a symmetric monopole LCC-HVDC system. The symmetric monopole LCC-HVDC system is a bipolar 12-pulse converter, and includes the following steps:

[0069] Obtain the topological structure of the symmetric monopole LCC-HVDC system, consider the distributed capacitance of the DC transmission line to the ground, and determine the harmonic current circulation path on the DC side of the converter at the inverter station;

[0070] Through the harmonic current circulation path, determine the order and effective value of the harmonic components on the DC transmission line;

[0071] According to the order of the harmonic components and the effective value of the corresponding order, set DC filters of the corresponding order at the sending end and the receiving end respectively.

[0072] Through the above DC filter configuration scheme, the problem that the harmonic distribution characteristics on the DC side of the HVDC system under the symmetric monopole wiring method are quite different from those of the traditional symmetric bipolar HVDC system is solved. Through the harmonic current circulation path, determine the order and effective value of the harmonic components on the DC transmission line; according to the order and effective value of the harmonic components, set DC filters of the corresponding order at the sending end and the receiving end respectively. Under steady-state operation, the ratio of the effective value of the harmonic current to the rated current is well controlled, and the harmonics at the DC outlet of the rectifier side can be filtered out.

[0073] In this embodiment, when DC filters with corresponding numbers of times are respectively arranged at the sending end and the receiving end, it further includes: connecting the DC filter at the sending end between the positive and negative buses, and connecting the DC filter at the sending end between the bus and the ground.

[0074] Among them, two sets of DC filters are arranged at the sending end.

[0075] As an optimization of the above embodiment, it further includes:

[0076] When the inter-station communication is abnormal, if two sets of DC filters are lost simultaneously at the sending end, the DC transmission system is blocked; if one set of DC filter is lost at the sending end and one set of DC filter is lost at the receiving end, the DC transmission system is not blocked. Thus, during the communication fault, the DC system blocking scheme can be realized.

[0077] As an optimization of the above embodiment, it further includes:

[0078] Collect data including harmonic current, voltage signals, and current parameter values of the filter;

[0079] Denoise and preprocess the collected original signals, and extract the amplitude, frequency, and phase information of each harmonic component;

[0080] Construct a discrete-time state space model of the filter and its compensation system with the amplitude, frequency, and phase information of each harmonic component;

[0081] Set the prediction time domain and the control time domain, and use the discrete-time state space model to predict the state within the future set number of steps;

[0082] Design a cost function considering the state deviation and the change amount of the control input as the objective of the model predictive control MPC optimization problem;

[0083] Set the upper and lower limits of the control input and the state according to the filter hardware and system safety requirements;

[0084] Obtain the current state and real-time harmonic data at each sampling moment; calculate the state trajectory within the future set number of steps using the discrete-time state space model;

[0085] Online solve the above constrained MPC optimization problem to obtain the optimal control sequence; update the filter parameters according to the control output;

[0086] After the new filter parameters are adjusted, continue to collect system data, and update the state according to the state trajectory to form a closed-loop feedback.

[0087] Using model predictive control, the filter parameters can be dynamically adjusted according to the future prediction of the system, achieving precise compensation for different harmonic components, thereby improving the harmonic suppression effect and overall operation stability of the system, while ensuring that the parameter adjustment is carried out within a safe and smooth range. This method helps to reduce system energy consumption, extend equipment life and achieve efficient operation in practical engineering.

[0088] In this embodiment, a discrete-time state space model of the filter and its compensation system is constructed based on the amplitude, frequency and phase information of each harmonic component, including:

[0089] Construct a state vector based on the amplitude, frequency and phase information of each harmonic component;

[0090] Construct a state equation and an output equation based on the state vector;

[0091] Construct a discrete-time state space model based on the state equation and the output equation.

[0092] Construct a discrete-time state space model of the filter and its compensation system, describe the influence of filter parameters on the harmonic suppression effect, establish a mathematical model to facilitate the prediction of the system state at future moments, and provide a prediction basis for the MPC algorithm.

[0093] Among them, the state equation is:

[0094] x(k + 1) = Ax(k) + Bu(k);

[0095] The output equation is:

[0096] y(k) = C x(k) + Du(k);

[0097] Where:

[0098]

[0099] In the formula, x(k) is the state vector, describing the state of the system at time k, x(k + 1) is the state vector at time k + 1, u(k) is the control input vector, y(k) is the output value at time k, ΔC(k) is the capacitor adjustment amount, ΔL(k) is the inductor adjustment amount, ΔA comp (k) is the compensation amplitude adjustment amount, and A, B, C, D are the system model matrices respectively, which are determined by the physical characteristics of the system.

[0100] Set the prediction horizon and the control horizon, and use the discrete-time state space model to predict the state within the future set number of steps. The discrete-time state space model is:

[0101]

[0102] In the formula, N pLet \(P\) be the prediction horizon, \(x(k + i|k)\) be the predicted future system state at the \(i\)-th step at time \(k\), \(u(k + i|k)\) be the predicted future control input at the \(i\)-th step at time \(k\), and \(j\) be a parameter ranging from \(0\) to \(i - 1\).

[0103] By setting the prediction horizon and control horizon, using the discrete-time state-space model to predict the state within the set future step length, predicting the future state change, providing a basis for solving the optimal control input subsequently, and ensuring that the filter parameter adjustment can respond to harmonic fluctuations in advance.

[0104] As an optimization of the above embodiment, the cost function is:

[0105]

[0106] In the formula, \(J\) is the cost, \(x\) ref is the target state vector, representing the state under the ideal state; \(u\) ref is the reference control input, corresponding to the initial parameters or nominal parameters of the filter; \(Q\) is the state error weighting matrix, reflecting the importance degree of the system for harmonic suppression; \(R\) is the control input change weighting matrix, restricting the amplitude of the filter parameter adjustment; \(x(k)\) is the state vector, describing the state of the system at time \(k\), \(x(k + 1)\) is the state vector at time \(k + 1\), \(u(k)\) is the control input vector, \(N\) p is the prediction horizon; \(T\) is the total number of prediction steps.

[0107] By setting the cost function, in the optimization process, it not only ensures that the system state approaches the target state as soon as possible but also avoids overly aggressive parameter adjustment, ensuring the stable and reliable operation of the system.

[0108] In this embodiment, setting the upper and lower limits of the control input and state includes:

[0109] \(u\) min \(\leq u(k + i|k)\leq u\) max , \(i = 0, 1,\cdots, N\) c - 1;

[0110] \(x\) min \(\leq x(k + i|k)\leq x\) max , \(i = 1, 2,\cdots, N\) p ;

[0111] In the formula, \(u\) min , \(u\) max are respectively the minimum and maximum values of the filter parameter adjustment; \(x\) min , \(x\) max are respectively the minimum and maximum values of the safe operating range, and \(N\) c is the control horizon.

[0112] By setting the upper and lower limits of the control input and state, it is ensured that the control input solved by MPC is within the range allowed by the hardware, preventing system instability or equipment damage caused by parameter overrun.

[0113] As an optimization of the above embodiment, updating the filter parameters according to the control output includes:

[0114] C(k + 1) = C(k) + ΔC(k);

[0115] L(k + 1) = L(k) + ΔL(k);

[0116] A comp (k + 1) = A comp (k) + ΔA comp (k);

[0117] In the formula, C(k) is the capacitance parameter at time k, C(k + 1) is the capacitance parameter at time k + 1; L(k) is the inductance parameter at time k, L(k + 1) is the inductance parameter at time k + 1; Acomp(k) is the compensation amplitude parameter at time k, Acomp(k + 1) is the compensation amplitude parameter at time k + 1.

[0118] Real-time solution and closed-loop control ensure that the system can quickly respond to harmonic fluctuations. By predicting in advance and optimizing and adjusting the filter parameters online, harmonic suppression is made more accurate, and the dynamic performance and adaptability of the system are greatly improved.

[0119] Through the above steps, model predictive control can be used to dynamically adjust the filter parameters according to the future prediction of the system, realizing precise compensation for different harmonic components, thereby improving the harmonic suppression effect and the overall operation stability of the system, while ensuring that the parameter adjustment is carried out within a safe and smooth range. This method helps to reduce system energy consumption, extend equipment life and achieve efficient operation in practical engineering.

[0120] As Figure 2 shown, this embodiment also includes a DC filter configuration device for a symmetric monopolar LCC-HVDC system, including:

[0121] An acquisition unit for acquiring the topological structure of the symmetric monopolar LCC-HVDC system, considering the distributed capacitance of the DC transmission line to the ground, and determining the harmonic current circulation path on the DC side of the inverter station converter;

[0122] A harmonic calculation unit for determining the order and effective value of the harmonic components on the DC transmission line through the harmonic current circulation path;

[0123] A DC filter unit for respectively setting DC filters of corresponding orders at the sending end and the receiving end according to the effective value of the harmonic components of the corresponding orders.

[0124] With the above DC filter configuration device, the problem that the harmonic distribution characteristics on the DC side of the HVDC system in the symmetric monopole connection mode are quite different from those of the traditional symmetric bipolar HVDC system is solved. Through the harmonic current circulation path, the order and effective value of the harmonic components on the DC transmission line are determined; according to the order and effective value of the harmonic components, DC filters corresponding to the order are set at the sending end and the receiving end respectively. Under steady-state operation, the ratio of the effective value of the harmonic current to the rated current is well controlled, and the harmonics at the DC outlet of the rectifier side can be filtered out.

[0125] Embodiment 2:

[0126] As Figure 3 shown, in this embodiment, the Yangzhen symmetric monopole LCC-HVDC system is taken as an example. The Yangzhen symmetric monopole LCC-HVDC system adopts a symmetric monopole topology structure, and the midpoint of the DC side of the 12-pulse converter at the inverter station is grounded. In addition, considering the distributed capacitance of the DC transmission line to the ground, this provides a circulation path for the 6th harmonic current on the DC side of the 6-pulse converter at the inverter station.

[0127] From Figure 3 the abstracted 6th harmonic circulation loop is as Figure 4 shown, where L and C respectively represent the equivalent inductance and capacitance of the DC line. It can be seen that the loops composed of the positive and negative 6th harmonic voltage sources are decoupled from each other. Therefore, even if the amplitudes of the positive and negative 6th harmonic voltage sources are equal and the phases are opposite, the 6th harmonic components of the voltage and current on the DC transmission line cannot be eliminated.

[0128] According to Figure 4 the circuit in, the effective value of the 6th harmonic current I6th on the DC side of the inverter can be calculated by the following formula:

[0129]

[0130] It can be found from the formula that under the condition that other conditions remain unchanged, the longer the transmission distance L is, the larger the amplitude of the 6th harmonic current I6th is.

[0131] In this scheme, different DC filter wiring methods are adopted at the sending end and the receiving end. Among them, the DC filter at the sending end is connected between the positive and negative buses; the DC filter at the receiving end is connected between the bus and the ground, as Figure 5 shown.

[0132] Figure 6 shows the DC voltage and current waveforms when Scheme 3 is adopted. Under steady-state operation, the ratio of the effective value of the 6th harmonic current to the rated DC current is also very small, only 2%. Since the HP12 / 24 DC filter is equipped at the rectifier side, the 24th harmonic at the DC outlet of the rectifier side can be filtered out.

[0133] This embodiment proposes a DC filter configuration scheme applicable to the "embedded" symmetric monopole LCC-HVDC system of the symmetric monopole topology, which solves the problem that the harmonic distribution characteristics on the DC side of the HVDC system under the symmetric monopole connection mode are quite different from those of the traditional symmetric bipolar HVDC system. In the symmetric monopole system, the DC side where the grounding point is located mainly has 6 / 12th harmonics to the ground, while the DC side where the grounding point is not located mainly has 12 / 24th harmonics between the poles. For this specific topology, the present invention proposes a scheme of configuring 6 / 12th DC filters on the side where the grounding point is not located and 12 / 24th DC filters on the grounding point side.

[0134] During a communication fault, when two sets of DC filters at the inverter station are withdrawn, the DC system does not lock out, as Figure 7 shown. This does not conform to the logic strategy of locking out the DC system when two sets of DC filters are withdrawn during normal communication conditions.

[0135] Therefore, the strategy is changed to: in the absence of inter-station communication, if two sets of DC filters are lost simultaneously at the sending end, lock out the DC system; if one set of DC filters is lost at the receiving end and one set of DC filters is lost at the sending end, do not lock out the DC system.

[0136] Please refer to Figure 8 the structural schematic diagram of the computer device provided by the embodiment of the present application shown. A computer device 400 provided by the embodiment of the present application includes: a processor 410 and a memory 420. The memory 420 stores a computer program executable by the processor 410. When the computer program is executed by the processor 410, it executes the method as described above.

[0137] The embodiment of the present application also provides a storage medium 430. A computer program is stored on the storage medium 430. When the computer program is run by the processor 410, it executes the method as described above.

[0138] Among them, the storage medium 430 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0139] In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. The meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0140] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "coupled", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0141] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0142] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or process. The scope of the preferred embodiments of the present invention includes additional implementations, where functions may be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present invention pertain.

[0143] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or in conjunction with such instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which the program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or otherwise processing as appropriate, and then stored in a computer memory.

[0144] It should be understood that various parts of the present invention can be implemented by hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0145] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the method of the above embodiments can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0146] The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present invention.

Claims

1. A DC filter configuration method for a symmetrical monopolar LCC-HVDC system, where the symmetrical monopolar LCC-HVDC system is a bipolar 12-pulse converter, characterized in that, It includes the following steps: Obtain the topological structure of the symmetric monopolar LCC-HVDC system, consider the distributed capacitance of the DC transmission line to the ground, and determine the harmonic current circulation path on the DC side of the inverter converter station; Through the harmonic current circulation path, determine the order and effective value of the harmonic components on the DC transmission line; According to the order of the harmonic components and the effective value of the corresponding order, set DC filters of the corresponding order at the sending end and the receiving end respectively.

2. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 1, characterized in that When setting the DC filters of the corresponding order at the sending end and the receiving end respectively, it further includes: connecting the DC filter at the sending end between the positive and negative buses, and connecting the DC filter at the sending end between the bus and the ground.

3. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 1, wherein Two sets of DC filters are set at the sending end.

4. The method for configuring a DC filter of the symmetric monopole LCC-HVDC system according to claim 3, characterized in that, It further includes: When the inter-station communication is abnormal, if two sets of DC filters are lost simultaneously at the sending end, lock the DC transmission system; If one set of DC filter is lost at the sending end and one set of DC filter is lost at the receiving end, do not lock the DC transmission system.

5. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 1, characterized in that, It further includes the following steps: Collect data including harmonic current, voltage signals, and current parameter values of the filter; Denoise and preprocess the collected original signals, and extract the amplitude, frequency, and phase information of each harmonic component; Construct a discrete-time state space model of the filter and its compensation system with the amplitude, frequency, and phase information of each harmonic component; Set the prediction time domain and the control time domain, and use the discrete-time state space model to predict the state within the future set step length; Design a cost function considering the state deviation and the change amount of the control input as the objective of the model predictive control MPC optimization problem; According to the filter hardware and system safety requirements, set the upper and lower limits of the control input and the state; Obtain the current state and real-time harmonic data at each sampling moment; use the discrete-time state space model to calculate the state trajectory within the future set step length; Solve the above-mentioned constrained MPC optimization problem online to obtain the optimal control sequence; update the filter parameters according to the control output; After the new filter parameters are adjusted, continue to collect system data, and update the state according to the state trajectory to form a closed-loop feedback.

6. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 5, wherein, The constructing the discrete-time state space model of the filter and its compensation system with the amplitude, frequency, and phase information of each harmonic component includes: Construct a state vector with the amplitude, frequency, and phase information of each harmonic component; Construct a state equation and an output equation with the state vector; Construct the discrete-time state space model with the state equation and the output equation.

7. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 6, characterized in that, The state equation is: x(k + 1) = Ax(k) + Bu(k); The output equation is: y(k) = Cx(k) + Du(k); Where: Where, x(k) is the state vector, describing the state of the system at time k, x(k + 1) is the state vector at time k + 1, u(k) is the control input vector, y(k) is the output value at time k, ΔC(k) is the capacitance adjustment amount, ΔL(k) is the inductance adjustment amount, and ΔA comp (k) is the compensation amplitude adjustment amount, and A, B, C, and D are the system model matrices respectively, which are determined by the physical characteristics of the system.

8. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 7, characterized in that In the setting the prediction time domain and the control time domain, and using the discrete-time state space model to predict the state within the future set step length, the discrete-time state space model is: where N p is the prediction horizon, x(k+i|k) is the predicted future system state at the i-th step at time k, u(k+i|k) is the predicted future control input at the i-th step at time k, and j is a parameter and ranges from 0 to i-1.

9. The DC filter configuration method for the symmetric monopole LCC-HVDC system according to claim 5, characterized in that, The cost function is: where J is the cost and x ref is the target state vector, representing the state under the ideal state; u ref is the reference control input, corresponding to the initial parameters or nominal parameters of the filter; Q is the state error weighting matrix, reflecting the degree of emphasis of the system on harmonic suppression; R is the control input change weighting matrix, restricting the amplitude of filter parameter adjustment; x(k) is the state vector, describing the state of the system at time k, x(k + 1) is the state vector at time k + 1, u(k) is the control input vector, N p is the prediction horizon; T is the total number of prediction steps.

10. The method for configuring a DC filter of a symmetric monopole LCC-HVDC system according to claim 9, characterized in that, The setting the upper and lower limits of the control input and the state includes: u min u(k + i|k) ≤ u max where i = 0, 1, ..., N c - 1; x min ≤x(k + i|k)≤x max ,where i = 1, 2,..., N p ; where, u min , u max are the minimum and maximum values for adjusting the filter parameters respectively; x min , x max are the minimum and maximum values of the safe operating range respectively, and N c is the control time domain.

11. The DC filter configuration method for a symmetric monopole LCC-HVDC system as claimed in claim 7, wherein, The updating the filter parameters according to the control output includes: C(k + 1) = C(k) + ΔC(k); L(k + 1) = L(k) + ΔL(k); A comp (k + 1)=A comp (k)+ΔA comp (k); Wherein, C(k) is the capacitance parameter at time k, and C(k + 1) is the capacitance parameter at time k + 1; L(k) is the inductance parameter at time k, and L(k + 1) is the inductance parameter at time k + 1; Acomp(k) is the compensation amplitude parameter at time k, and Acomp(k + 1) is the compensation amplitude parameter at time k + 1.

12. A DC filter configuration device for a symmetrical monopole LCC-HVDC system, characterized in that, Using the method according to any one of claims 1 to 11, the apparatus comprises: An acquisition unit, configured to acquire the topological structure of the symmetrical monopolar LCC-HVDC system, consider the distributed capacitance of the DC transmission line to the ground, and determine the harmonic current circulation path on the DC side of the inverter station converter; A harmonic calculation unit, configured to determine the order and the effective value of the harmonic components on the DC transmission line through the harmonic current circulation path; A DC filter unit, configured to respectively set DC filters of corresponding orders at the sending end and the receiving end according to the order of the harmonic components and the effective value of the corresponding order.

13. A computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, the method according to any one of claims 1-11 is implemented.

14. A storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the method according to any one of claims 1-11 is implemented.

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