Signal sampling rate adaptive adjustment method and system

Abstract

The disclosed embodiment discloses a method and system for adaptively adjusting a signal sampling rate. The method includes: obtaining the original sampling rate and target sampling rate of the original signal; receiving the original signal, sampling the original signal according to the original sampling rate, and obtaining the signal value of the sampling point in real time; discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate, respectively, to obtain a discrete first time value and a second time value; storing the real-time obtained signal value and the first time value in parallel in multiple filter groups; based on the second time value and the first time value stored by the filter group, triggering the filter group to perform an interpolation operation on the stored signal value to obtain a signal interpolation; sorting the signal interpolation according to the working sequence of the multiple filter groups, and outputting the sorted signal interpolation according to the target sampling rate to form a target signal. This method can flexibly adjust the sampling rate of the input signal, and at the same time, reduce processing time and resource consumption based on multiple filter groups.

Description

Technical Field

[0001] The present disclosure relates to the field of signal processing technology, and in particular to a method and system for adaptively adjusting a signal sampling rate. Background Art

[0002] With the continuous development of modern technologies in fields such as communications, radar, electronic countermeasures, and high-speed data transmission, the application of broadband signals is becoming increasingly widespread. Compared with narrowband signals, broadband signals have a wider frequency range, higher dynamic range, and more complex modulation characteristics. These characteristics give broadband signals significant advantages in information transmission and processing.

[0003] However, when processing broadband signals, existing FPGA signal output methods mostly use fixed sampling rates or preset rate modes, which are difficult to adapt to the dynamic rate requirements of broadband signals. This fixed mode cannot be flexibly adjusted according to the actual changes in the signal, resulting in limited flexibility in signal processing. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a method and system for adaptively adjusting a signal sampling rate, which can flexibly adjust the sampling rate of an input signal while reducing processing time and resource consumption based on multiple filter groups.

[0005] In a first aspect, an embodiment of the present disclosure provides a method for adaptively adjusting a signal sampling rate, which adopts the following technical solutions:

[0006] Get the original sampling rate and target sampling rate of the original signal;

[0007] Receive the original signal, sample the original signal according to the original sampling rate, and obtain the signal value of the sampling point in real time;

[0008] Discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate respectively to obtain a discrete first time value and a discrete second time value;

[0009] storing the real-time acquired signal value and the first time value in parallel into a plurality of filter banks;

[0010] triggering the filter bank to perform an interpolation operation on the stored signal value based on the second time value and the first time value stored in the filter bank to obtain a signal interpolation value;

[0011] The signal interpolations are sorted according to the working timing of the plurality of filter groups, and the sorted signal interpolations are output according to the target sampling rate to form a target signal.

[0012] Optionally, discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate to obtain a discrete first time value and a discrete second time value includes:

[0013] When the original signal is received, the first counter and the second counter are started simultaneously, wherein the counting frequency of the second counter is higher than the counting frequency of the first counter;

[0014] using the count value of the first counter to represent a discrete first time value;

[0015] Obtaining a conversion factor based on the original sampling rate and the target sampling rate;

[0016] A discrete second time value is acquired based on the count value of the second counter and the conversion factor.

[0017] Optionally, the storing the real-time acquired signal value and the first time value in parallel into a plurality of filter banks includes:

[0018] storing the real-time acquired signal values ​​in parallel in the first FIFO data buffers of the plurality of filter banks;

[0019] The first time value acquired in real time is stored in parallel in the second FIFO data buffers of the plurality of filter banks.

[0020] Optionally, triggering the filter bank to perform an interpolation operation on the stored signal value based on the second time value and the first time value stored in the filter bank to obtain a signal interpolation value includes:

[0021] extracting a start value and an operation value from the second time value;

[0022] Determine a target number according to the numbering order of the filter groups, and send the target number, the start value, and the operation value to each filter group;

[0023] When the number of the filter group is the same as the target number, triggering the filter group to compare the received start value with the earliest first time value stored in the second FIFO data buffer; wherein the second FIFO data buffer is the data buffer of the filter group;

[0024] If the comparison is consistent, a signal interpolation value is obtained based on the signal value stored in the filter bank and the received operation value.

[0025] Optionally, extracting the start value and the operation value from the second time value includes:

[0026] extracting an integer part of the second time value as a start value;

[0027] A decimal portion of the second time value is extracted as a calculation value.

[0028] Optionally, obtaining a signal interpolation value based on the signal value stored in the filter bank and the received operation value includes:

[0029] constructing a signal column vector based on the signal values ​​stored by the filter bank;

[0030] Obtaining a matrix mapping signal vector based on the signal column vector and a preset interpolation matrix;

[0031] Obtaining a decreasing exponential column vector of the operation value based on the order N of the interpolation matrix;

[0032] A signal interpolation value is obtained based on the matrix-mapped signal vector and the decreasing index column vector.

[0033] Optionally, the signal sampling rate adaptive adjustment method further includes:

[0034] Storing the startup value and the operation value in a startup value cache queue and an operation value cache queue respectively;

[0035] The start and stop of the second counter are controlled based on the remaining storage space sizes of the startup value cache queue and the operation value cache queue.

[0036] In a second aspect, the embodiments of the present disclosure further provide a signal sampling rate adaptive adjustment system, which adopts the following technical solutions:

[0037] The signal sampling rate adaptive adjustment system includes a signal front-end processing module, multiple filter banks, a variable sampling rate control module, a sequential value module and a FIFO buffer;

[0038] The input end of the signal front-end processing module is connected to the output end of the signal source;

[0039] The input end of the variable sampling rate control module is connected to the output end of the sampling rate configuration module;

[0040] The output end of the signal front-end processing module and the output end of the variable sampling rate control module are both connected to the input ends of the multiple filter groups, and the variable sampling rate control module is connected to the signal front-end processing module;

[0041] The output ends of the plurality of filter groups are connected to the input end of the sequential value taking module;

[0042] The output end of the sequential value taking module is connected to the input end of the FIFO buffer.

[0043] Optionally, the signal front-end processing module includes a signal receiver and a first counter, and the multiple filter banks each include a first FIFO data buffer and a second FIFO data buffer;

[0044] The input end of the signal receiver is connected to the output end of the signal source;

[0045] The output end of the signal receiver is connected to the input end of the first counter and the input end of the first FIFO data buffer respectively;

[0046] The output end of the first counter is connected to the input end of the second FIFO data buffer.

[0047] Optionally, the variable sampling rate control module includes a second counter, an operator, a start value cache queue, an operation value cache queue and a controller, and the multiple filter groups further include a comparator and a digital signal processor;

[0048] An input terminal of the second counter is connected to an output terminal of the signal receiver;

[0049] The input end of the operator is connected to the output end of the second counter and the output end of the sampling rate configuration module;

[0050] The output end of the operator is connected to the input end of the startup value cache queue and the input end of the operation value cache queue;

[0051] The input end of the controller is connected to the output end of the startup value cache queue and the output end of the operation value cache queue;

[0052] The input end of the comparator is connected to the output end of the controller and the output end of the second FIFO data buffer, and the controller is also connected to the second counter and the digital signal processor;

[0053] An input terminal of the digital signal processor is connected to an output terminal of the comparator and an output terminal of the first FIFO data buffer;

[0054] The output end of the digital signal processor is connected to the input end of the sequential value taking module.

[0055] The signal sampling rate adaptive adjustment method provided by the embodiment of the present disclosure can flexibly adjust the sampling rate according to actual needs by obtaining the original sampling rate and target sampling rate of the original signal, and adapt to the complex and changeable rate requirements of broadband signals. The sampling time at the original sampling rate and the target sampling rate is discretized respectively, and the continuous time signal is converted into discrete time points. This discretization process reduces the data complexity, enables the subsequent signal processing algorithm to run efficiently, and greatly improves the flexibility of signal processing. The method adopts a parallel storage and interpolation operation mechanism to store the real-time acquired signal value and the first time value in parallel in multiple filter groups, thereby improving the data storage speed and reducing the storage delay. When the filter group is triggered to work, the interpolation operation can be performed in parallel according to the stored data, making full use of the system's parallel computing resources, such as multi-core processors and parallel computing units, etc., greatly improving the overall data processing efficiency, and ensuring that the real-time requirements can be met when processing broadband signals. In addition, the filter bank can not only perform preliminary processing and screening on the stored data to provide appropriate data for interpolation operations, but also effectively avoid the generation and interference of mirror frequencies during the interpolation operation. By processing the second time value and the first time value, it can determine the position in the original sampled signal that needs to be interpolated and perform accurate interpolation operations, thereby ensuring high-quality signal output. Signal interpolation is sorted according to the working timing of multiple filter banks to ensure that the output signal values ​​are arranged in the correct time sequence, avoiding signal distortion and confusion. The signal interpolation is output according to the target sampling rate, which can accurately reconstruct a signal that meets the target sampling rate requirements, ensuring signal accuracy and integrity, and providing a reliable solution for broadband signal processing.

[0056] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following specifically cites preferred embodiments and describes them in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0058] Figure 1 A schematic diagram of a flow chart of a signal sampling rate adaptive adjustment method provided in an embodiment of the present disclosure;

[0059] Figure 2 A schematic diagram of a signal resampling circuit according to an embodiment of the present disclosure;

[0060] Figure 3 A schematic diagram of a process for discretizing sampling time provided in an embodiment of the present disclosure;

[0061] Figure 4 A schematic diagram of a flow chart of a parallel storage method provided in an embodiment of the present disclosure;

[0062] Figure 5 A flowchart of a filter bank control method provided by an embodiment of the present disclosure;

[0063] Figure 6 A flow chart of a signal interpolation calculation method provided in an embodiment of the present disclosure;

[0064] Figure 7 The time-frequency diagram obtained by performing sampling rate conversion using a traditional 4th-order Farrow interpolation filter according to the embodiment of the present disclosure;

[0065] Figure 8 This is a time-frequency diagram obtained after sampling rate conversion using the signal sampling rate adaptive adjustment method provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] It should be clear that the following embodiments of the present disclosure are described through specific concrete examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other in the absence of conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0068] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0069] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present disclosure. The illustrations only show components related to the present disclosure and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0070] Additionally, in the following description, specific details are provided to provide a thorough understanding of the examples. However, one skilled in the art will appreciate that the aspects described can be practiced without these specific details.

[0071] Reference Figure 1 The present disclosure provides a method for adaptively adjusting a signal sampling rate, comprising the following steps:

[0072] S1: Get the original sampling rate and target sampling rate of the original signal;

[0073] S2: Receive the original signal, sample the original signal according to the original sampling rate, and obtain the signal value of the sampling point in real time;

[0074] S3: discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate respectively to obtain a discrete first time value and a discrete second time value;

[0075] S4: storing the real-time acquired signal value and the first time value in parallel into a plurality of filter banks;

[0076] S5: Based on the second time value and the first time value stored in the filter bank, trigger the filter bank to perform an interpolation operation on the stored signal value to obtain a signal interpolation value;

[0077] S6: Sort the signal interpolation according to the working timing of the plurality of filter groups, and output the sorted signal interpolation according to the target sampling rate to form a target signal.

[0078] Existing FPGA signal output methods are primarily based on fixed sampling rates or preset rate modes, which present significant drawbacks when processing wideband signals. First, fixed-rate output modes lack flexibility and cannot adapt to the dynamic rate requirements of wideband signals, limiting signal processing flexibility. Second, while existing variable-rate output methods address the shortcomings of fixed rates to some extent, they are mostly applicable only to narrowband signals. These methods rely on the narrow bandwidth of narrowband signals and achieve variable-rate output through simple filtering, modulation, and demodulation. However, when applied to wideband signals, these methods generate a large number of image frequencies, which interfere with each other and degrade signal quality. Furthermore, the massive data volume of wideband signals places extremely high demands on the computational speed of signal processing systems. However, existing FPGA signal output methods often fail to meet real-time requirements when processing wideband signals, resulting in a lack of real-time signal processing capabilities. As narrowband signals gradually decrease and the application scenarios of wideband signals continue to expand, the shortcomings of existing FPGA signal output methods are becoming increasingly apparent.

[0079] The signal sampling rate adaptive adjustment method provided by the present disclosure can flexibly adjust the sampling rate according to actual needs by obtaining the original sampling rate and target sampling rate of the original signal, and adapt to the complex and changeable rate requirements of broadband signals. The sampling time at the original sampling rate and the target sampling rate are discretized respectively, and the continuous time signal is converted into discrete time points. This discretization process reduces the data complexity, enables the subsequent signal processing algorithm to run efficiently, and greatly improves the flexibility of signal processing. The method adopts a parallel storage and interpolation operation mechanism to store the real-time acquired signal value and the first time value in parallel in multiple filter groups, thereby improving the data storage speed and reducing the storage delay. When the filter group is triggered to work, the interpolation operation can be performed in parallel according to the stored data, making full use of the system's parallel computing resources, such as multi-core processors and parallel computing units, greatly improving the overall data processing efficiency, and ensuring that the real-time requirements can be met when processing broadband signals. In addition, the filter bank can not only perform preliminary processing and screening on the stored data to provide appropriate data for interpolation operations, but also effectively avoid the generation and interference of mirror frequencies during the interpolation operation. By processing the second time value and the first time value, it can determine the position in the original sampled signal that needs to be interpolated and perform accurate interpolation operations, thereby ensuring high-quality signal output. Signal interpolation is sorted according to the working timing of multiple filter banks to ensure that the output signal values ​​are arranged in the correct time sequence, avoiding signal distortion and confusion. The signal interpolation is output according to the target sampling rate, which can accurately reconstruct a signal that meets the target sampling rate requirements, ensuring signal accuracy and integrity, and providing a reliable solution for broadband signal processing.

[0080] In summary, this method can flexibly adjust the sampling rate of the input signal, and can more effectively utilize hardware resources and reduce processing time and resource consumption when processing large-scale signals, especially when facing the demand for increased broadband signal rates.

[0081] In S1, users can manually enter the original sampling rate of the original signal through the interface of the sampling rate configuration module, while the target sampling rate can be automatically determined according to system requirements or preset rules, or it can be manually entered through the interface of the sampling rate configuration module.

[0082] In S2, a signal receiver is set up to receive the original signal output by the signal source. The original sampling rate of the original signal is the input sampling rate, but this sampling rate currently does not meet user requirements, so the sampling rate needs to be adjusted. Before adjustment, the signal receiver samples the original signal at the original sampling rate, obtains sampling points in real time, and records the signal values ​​at these sampling points in bits. These recorded signal values ​​will serve as the basis for subsequent interpolation operations.

[0083] Reference Figure 2 The signal resampling circuit schematic is shown. By optimizing the signal processing architecture inside the field programmable gate array (FPGA), the rate control mechanism is optimized. Sig_in represents the original signal emitted by the signal source, and SR represents the signal receiver. SR is responsible for receiving Sig_in and sampling it according to the original sampling rate, and then outputting the signal values ​​at these sampling points, which are recorded as 、 、…、 、…。

[0084] In S3, resampling refers to the process of converting the original signal from its original sampling rate to the target sampling rate to form the target signal. This process requires that the time points of the original signal at the two sampling rates be clearly defined. Discretization is the process of converting a continuous-time signal into a discrete-time signal. Through discretization, the time points of the original signal at the original sampling rate and the target sampling rate can be clearly defined, thus providing the necessary basis for resampling. Figure 3 The flowchart of sampling time discretization is shown. "Discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate to obtain discrete first and second time values" includes the following steps:

[0085] S31: When the original signal is received, the first counter and the second counter are started simultaneously, and the counting frequency of the second counter is higher than the counting frequency of the first counter;

[0086] S32: using the count value of the first counter to represent a discrete first time value;

[0087] S33: Obtain a conversion factor based on the original sampling rate and the target sampling rate;

[0088] S34: Acquire a discrete second time value based on the count value of the second counter and the conversion factor.

[0089] In the above steps, receiving the original signal is a trigger point, at which point the first counter and the second counter are simultaneously activated. The count value of the first counter represents the sampling time points of the original signal after being discretized at the original sampling rate, recorded as first time values. These first time values ​​constitute the normalized time axis of the original signal. The count value of the second counter is used to subsequently calculate the sampling time points of the original signal after being discretized at the target sampling rate, recorded as second time values. These second time values ​​constitute the normalized time axis of the target signal.

[0090] Because the target sampling rate is usually higher than the original sampling rate, the time interval for discretizing the sampling time at the target sampling rate will be shorter than that at the original sampling rate. This requires that the counting frequency of the second counter be higher than that of the first counter, so that the second counter generates the time axis at a faster rate than the first counter. For example, if the counting frequency of the first counter is 100MHz, the counting frequency of the second counter can be set to 400MHz.

[0091] The second time value is equal to the product of the count value of the second counter and the conversion factor, and the conversion factor is the ratio of the original sampling rate to the target sampling rate. The calculation formula of the second time value is as follows:

[0092] ;(Formula 1)

[0093] In formula 1, is a time series index of the target signal, used to mark the order of each count of the second counter and the order of generating the second time value; For the A second time value; The first count values; is the original sampling rate; is the target sampling rate; is the conversion factor.

[0094] Reference Figure 2 , CNT1 represents the first counter, CNT1 is connected to the signal receiver SR, and is used to bind the output of Sig_in, and CNT2 represents the second counter. When SR receives the original signal, it sends a start instruction to CNT1 and CNT2. After receiving the start instruction, the first counter and the second counter start counting according to their respective frequencies. The first counter generates a first time value in real time, which is recorded as 、 、…、 ,…. CNT1 and SR together constitute the signal front-end processing module, which is Figure 2 It is represented as FE, which is used to receive and process the original signal and output the signal value of the sampling point and the corresponding first time value The count value generated by the second counter is recorded as 、 、…、 , ..., AU represents an arithmetic unit, which is used to generate a count value according to the second counter And the original sampling rate output by the sampling rate configuration module and target sampling rate , calculate the second time value.

[0095] To convert the original signal from its original sampling rate to its target sampling rate, the signal's time points must be aligned at the two sampling rates. By utilizing the auto-increment function of the first and second counters, time is discretized to obtain the discretized first and second time values. These discretized first and second time values ​​provide the basis for this alignment of signal time points, allowing comparison and processing of the original signal's time points at the two sampling rates. Furthermore, the discretized signal and time values ​​make signal processing more flexible. In digital signal processing systems, these discrete values ​​can be efficiently stored and processed, supporting a variety of complex signal processing algorithms.

[0096] In S4, refer to Figure 4 The flowchart of the parallel storage method shown in the figure, "Parallel storage of real-time acquired signal values ​​and first time values ​​into multiple filter banks" includes the following steps:

[0097] S41: storing the real-time acquired signal values ​​in parallel into the first FIFO data buffers of the plurality of filter banks;

[0098] S42: The first time value acquired in real time is stored in parallel in the second FIFO data buffers of the plurality of filter banks.

[0099] In the above steps, refer to Figure 2 , multiple filter groups are pre-set, and these filter groups complete the interpolation operation of the signal value in parallel, thereby improving the resampling speed of the original signal. The number of filter groups can be freely adjusted according to the FPGA resources, and each filter group has its own number, such as FB1, FB2, ..., FB h 、…、FB H , where h is the number and H is the total number of filter banks.

[0100] In order to facilitate each filter to process the signal value in time according to the time point, the signal value and the corresponding first time value need to be stored in parallel in the corresponding FIFO data buffer (First-In-First-Out Data Buffer). Each filter group includes two FIFO data buffers with first-in-first-out characteristics. When the data is full, if there is new data, the earliest stored data (at the head of the data queue) will be moved out, and then the new data will be stored at the tail of the data queue. One of the FIFO data buffers is used to store the signal value, recorded as the first FIFO data buffer; the other is used to store the first time value, recorded as the second FIFO data buffer. Figure 2 In FIG, Buffer1 represents the first FIFO data buffer, and Buffer2 represents the second FIFO data buffer.

[0101] The method of storing the real-time acquired signal value and the first time value in parallel in each filter bank facilitates subsequent interpolation operations. The storage establishes a correspondence between the signal value and the first time value, facilitating accurate interpolation based on the time point at the original sampling rate. The filter bank characteristics can also be used to interpolate the stored signal in a targeted manner, improving accuracy and efficiency. Furthermore, it facilitates parallel processing and improves efficiency. Multiple filter banks operating in parallel can fully leverage the advantages of parallel processing, shorten sampling rate adjustment time, and meet real-time signal processing requirements. Furthermore, it facilitates the sorting and output of signal interpolation, providing a unified data source for sorting, adapting to differences in filter bank operating timing, and ensuring that the target signal is output at the target sampling rate.

[0102] In S5, refer to Figure 5 The flowchart of the filter bank control method shown in the figure, "triggering the filter bank to perform an interpolation operation on the stored signal value based on the second time value and the first time value stored in the filter bank to obtain a signal interpolation value" includes the following steps:

[0103] S51: extracting a start value and an operation value from the second time value;

[0104] S52: Determine the target number according to the order of the filter groups, and send the target number, the start value, and the operation value to each filter group;

[0105] S53: When the filter group number is the same as the target number, the filter group is triggered to compare the received start value with the first time value stored earliest in the second FIFO data buffer; if the comparison is consistent, S54 is executed; if the comparison is inconsistent, S55 is executed;

[0106] S54: Obtaining a signal interpolation value based on the signal value stored in the filter bank and the received operation value;

[0107] S55: The task of not triggering interpolation operation.

[0108] In the above steps, the start value is used to trigger the filter bank to begin interpolation operations, while the run value is used in conjunction with the corresponding signal value to participate in the specific interpolation operation. First, the second time value is processed and split into an integer portion and a decimal portion, with the integer portion serving as the start value and the decimal portion serving as the run value. Next, the target numbers are determined sequentially, starting with the smallest filter bank number and setting it as the first target number. Subsequently, the extracted start value, run value, and target number are transmitted to each filter bank via a data transmission channel. Upon receiving the target number, each filter bank checks whether its own number matches the received target number. If the filter bank number matches the target number, the filter bank reads the oldest stored first time value from its second FIFO data buffer. Due to the first-in, first-out nature of the second FIFO data buffer, the oldest stored first time value is located at the beginning of the buffer. The start value received by the filter bank is then compared with the read first time value. If the comparison is consistent, it means that the current time point has met the triggering conditions for the filter bank to perform interpolation operations. At this time, the filter bank can be triggered to perform interpolation operations on the signal values ​​stored in the first FIFO data buffer. In other words, the filter bank will calculate the signal interpolation value according to the preset interpolation algorithm based on the received operation value and the stored signal value. If the comparison is inconsistent, it means that the current time point has not yet met the requirements for the filter bank to perform interpolation operations. At this time, the filter bank interpolation operation task is not triggered.

[0109] Reference Figure 2 The operator AU and counter CNT2 are part of the variable sampling rate control module, which is used to control the interpolation operation of each filter bank. The module also includes a controller, which is represented by CTRL, and a variable sampling rate control module, which is represented by SRC. After calculating the second time value, the operator AU extracts the start value and the operation value from it. Int represents the start value, and frac represents the operation value. For example, when the second time values ​​are [0, 0.5, 1, 1.5, 2, 2.5, 3, 3.5], the extracted start values ​​are Int = [0, 0, 1, 1, 2, 2, 3, 3], and the operation values ​​are frac = [0, 0.5, 0, 0.5, 0, 0.5, 0, 0.5]. CTRL determines the target number according to the numbering sequence of the filter banks. In Figure 2, the target number is represented by Target. For example, the initial value of Target is number 1, and then it will change to number 2, number 3, and so on until number H. After all numbers are traversed, polling will continue and start again from number 1.

[0110] Each filter bank includes a comparator and a digital signal processor. Figure 2 In the figure, the comparator is represented by CMP, and the digital signal processor is represented by DSP. CTRL sends Int and Target to the CMP of each filter bank, and frac to the DSP of each filter bank. After receiving this data, the CMP compares the filter bank number with the result of Target. This triggers a comparison between Int and the earliest first time value stored in the second FIFO data buffer Buffer2 of the filter bank. When both comparisons meet the conditions, the interpolation operation for the filter bank is started. At this time, the CMP sends a calculation instruction to the DSP, which, upon receiving the calculation instruction, begins the interpolation operation using frac.

[0111] Furthermore, the counting frequency of the second counter is relatively high, which makes the real-time generation speed of the second time value relatively fast. In order to process the generated second time value in a timely manner, a startup value cache queue and an operation value cache queue are configured in the variable sampling rate control module, wherein the startup value cache queue is used to store the generated startup value, and the operation value cache queue is used to store the generated operation value. The remaining storage space size of the startup value cache queue and the operation value cache queue is monitored in real time. When the remaining storage space size of any cache queue is lower than the first threshold, it means that the cache queue is about to be full, and the counting operation of the second counter is suspended. The remaining storage space size of the cache queue continues to be monitored. When the remaining storage space size is higher than the second threshold, it indicates that the cache queue has released enough space and the second counter is restarted. When the remaining storage space size of any cache queue is higher than the third threshold, it means that the buffered data in the cache queue is about to run out, and the counting frequency of the second counter needs to be accelerated.

[0112] exist Figure 2 In the figure, BQ1 represents the startup value cache queue, and BQ2 represents the calculation value cache queue. CTRL not only extracts Int and frac from BQ1 and BQ2 respectively, but also monitors the remaining storage space of BQ1 and BQ2 in real time, and controls the start and stop of the second counter based on the remaining storage space of the two.

[0113] By configuring the startup value cache queue and the calculation value cache queue to promptly process the frequently generated startup values ​​and calculation values, and monitoring the remaining storage space of the cache queue in real time, the counting is paused to prevent overflow when the value is below the first threshold, and the counting is restarted to ensure continuity when the value is above the second threshold. When the value is above the third threshold, the counting frequency is accelerated to dynamically respond to the situation where the buffered data is about to run out, which can improve data processing efficiency, stability and flexibility.

[0114] When the filter group is triggered to perform interpolation operation, the filter group starts to calculate the signal interpolation. Figure 6The flowchart of the signal interpolation calculation method shown in the figure "Obtaining a signal interpolation value based on the signal value stored in the filter bank and the received operation value" includes the following steps:

[0115] S541: Constructing a signal column vector based on the signal values ​​stored in the filter bank;

[0116] S542: Obtain a matrix mapping signal vector based on the signal column vector and a preset interpolation matrix;

[0117] S543: Obtaining a decreasing exponential column vector of the operation value based on the order N of the interpolation matrix;

[0118] S544: Obtain signal interpolation based on the matrix mapping signal vector and the decreasing index column vector.

[0119] In the above steps, the interpolation matrix is ​​a matrix with N rows and N columns. The number of storage units of Buffer1 and Buffer2 is set to be equal to the order N, so that the number of signal values ​​stored by the filter bank and the number of first time values ​​are always N. This not only facilitates the alignment of the signal value with the first time value, but also helps in the subsequent calculation of the signal value stored by the filter bank and the interpolation matrix. First, the signal value stored by the filter bank is constructed as a signal column vector. The expression of the signal column vector is as follows:

[0120] ;(Formula 2)

[0121] In formula 2, is the time series index of the original signal, used to mark the generation order of the signal value. The order of the marked signal value is consistent with the order of each count of the first counter. At the same time, the order of each count of the first counter is also the generation order of the first time value. is the signal column vector; For the signal values; is the transpose of the matrix.

[0122] The interpolation matrix can be generated by various methods such as the sinc method (Single function method) and the Lagrange method. The general expression of the interpolation matrix is ​​as follows:

[0123] ;(Formula 3)

[0124] In formula 3, is the interpolation matrix, … is the element value of the interpolation matrix.

[0125] Taking the Lagrange method as an example, construct an interpolation matrix of N=4, and for each interpolation point and , calculate the polynomial coefficients through the Lagrange interpolation polynomial, where, , , the expression of the Lagrange interpolation polynomial is as follows:

[0126] ;(Formula 4)

[0127] In formula 4, is the independent variable; is the Lagrangian basis function.

[0128] Substitute into formula 4 value, calculated 、 、 、 The polynomial coefficients of , these polynomial coefficients form a coefficient matrix, the expression of the coefficient matrix is ​​as follows:

[0129] ;(Formula 5)

[0130] In formula 5, is the coefficient matrix.

[0131] The calculation results of the interpolation matrix are as follows:

[0132] ;(Formula 6)

[0133] Multiply the signal column vector by the interpolation matrix to obtain an N+1-order matrix-mapped signal vector. Calculate the decreasing exponent column vectors of the operation values ​​according to the matrix order N. The elements in the decreasing exponent column vectors are the powers of the operation values, and the powers decrease from N−1 to 0. The expression of the decreasing exponent column vector is as follows:

[0134] ;(Formula 7)

[0135] In formula 7, is a column vector of decreasing exponents.

[0136] The decreasing exponential column vector is transposed and multiplied with the matrix mapping signal vector, and then the sum is obtained to obtain the signal interpolation. The calculation formula of the signal interpolation is as follows:

[0137] ;(Formula 8)

[0138] In formula 8, For the Signal interpolation calculated by filter banks; Maps the signal vector to the matrix.

[0139] Reference Figure 2The digital signal processor DSP reads the signal value from the first FIFO data buffer Buffer1, forms a signal column vector with the read signal value, and then calculates the signal interpolation value in combination with the operation value frac sent by the controller CTRL. The row vector composed of the extracted operation values ​​can be compared to the time axis, and the calculated signal interpolation values ​​are equivalent to the signal sampling values ​​corresponding to each time point on this time axis. For example, assuming that the starting value calculated by the variable sampling rate control module is 24, the input signal flows through the filter group FB1 sequentially. When the first time value of 24 is stored, the condition is triggered and the difference operation begins. The calculation result is output as: 0.4677 + 0.8839i, which is sent to the FIFO buffer and output according to the target sampling rate of 150Mhz.

[0140] In S6, the filter banks execute their operations sequentially according to their numbering order. Therefore, the operating timing of the filter banks is determined by the numbering order. The filter bank numbers corresponding to the signal interpolation are sorted in ascending order. The signal interpolation is stored in the FIFO buffer according to this sorting order. The field programmable gate array outputs the sorted signal interpolation in the FIFO buffer at the target sampling rate, thereby generating the target signal.

[0141] Reference Figure 2 , SVM represents the sequential value module, FIFOCache represents the FIFO buffer, SVM is responsible for arranging the filter group numbers corresponding to the signal interpolation in ascending order, and storing the signal interpolation in FIFOCache according to the sorting order. Through this method, it can ensure that the field programmable gate array can correctly output the order of signal interpolation, so that the output signal interpolation forms the target signal.

[0142] In summary, the variable sampling rate control module controls the filter bank calculation process based on the original sampling rate of the original signal and the target sampling rate. Assuming four filter banks are configured, when data from each sampling point arrives, the filter bank combinations involved may be [1], [1,2], [1,2,3], or [1,2,3,4]. That is, the number of activated filter banks changes in real time with the amount of data. Each filter bank operates according to the instructions issued by the variable sampling rate control module and calculates signal interpolation. The output results of filter banks 1-4 may appear as [O1], [O1,O2], [O1, O2,O3], or [O1, O2,O3,O4]. These calculated signal interpolations are sent to the sequential value acquisition module for sorting. In this way, the FPGA can simultaneously utilize multiple filter banks to adjust the sampling rate, speeding up signal processing. Moreover, when the original sampling rate of the original signal changes, this method can still effectively convert the original signal from the changed original sampling rate to the target sampling rate, and significantly improves the flexibility of sampling rate adjustment.

[0143] Taking the original sampling rate of 100MHz as an example, a 50MHz broadband swept frequency complex signal is constructed with a duration of 1e-4 seconds. The goal is to increase the sampling rate of the broadband swept frequency complex signal from 100MHz to 150MHz. Figure 7 , we can see that after using the traditional 4th order Farrow interpolation filter to convert the sampling rate, a large number of mirror frequencies appear in the time-frequency diagram. These frequency components interfere with each other, resulting in a decrease in signal quality. In order to improve this situation, this application adopts a signal sampling rate adaptive adjustment method to perform sampling rate conversion, and refers to Figure 8 The time-frequency diagram after conversion is shown. It can be seen from the figure that the time-frequency domain characteristics after conversion are basically consistent with the time-frequency domain characteristics of the original input signal, which shows that the signal quality is well maintained during the adjustment of the sampling rate.

[0144] Reference Figure 2 , the present disclosure provides a signal sampling rate adaptive adjustment system, including a signal front-end processing module, multiple filter banks, a variable sampling rate control module, a sequential value module and a FIFO buffer;

[0145] The input end of the signal front-end processing module is connected to the output end of the signal source;

[0146] The input end of the variable sampling rate control module is connected to the output end of the sampling rate configuration module;

[0147] The output end of the signal front-end processing module and the output end of the variable sampling rate control module are both connected to the input ends of the plurality of filter groups, and the variable sampling rate control module is connected to the signal front-end processing module;

[0148] The output ends of the plurality of filter banks are connected to the input ends of the sequential value taking modules;

[0149] The output end of the sequential value module is connected to the input end of the FIFO buffer.

[0150] Among them, the variable sampling rate control module receives the original sampling rate and target sampling rate of the original signal sent by the sampling rate configuration module; the signal front-end processing module receives the original signal emitted by the signal source, samples the original signal according to the original sampling rate, obtains the signal value of the sampling point in real time, and discretizes the sampling time of the original signal at the original sampling rate to obtain a discrete first time value, and stores the real-time obtained signal value and the first time value in parallel in multiple filter groups.

[0151] The variable sampling rate control module discretizes the sampling time of the original signal at the target sampling rate to obtain a discrete second time value. Based on the second time value and the first time value stored in the filter group, the filter group is triggered to perform an interpolation operation on the stored signal value to obtain a signal interpolation value.

[0152] The sequential value acquisition module sorts the signal interpolation according to the working sequence of multiple filter groups, and stores the signal interpolation into the FIFO buffer in the sorted order. The field programmable gate array outputs the sorted signal interpolation in the FIFO buffer according to the target sampling rate to form the target signal.

[0153] Furthermore, the signal front-end processing module includes a signal receiver and a first counter, and the plurality of filter banks each include a first FIFO data buffer and a second FIFO data buffer;

[0154] The input end of the signal receiver is connected to the output end of the signal source;

[0155] The output end of the signal receiver is connected to the input end of the first counter and the input end of the first FIFO data buffer respectively;

[0156] The output end of the first counter is connected to the input end of the second FIFO data buffer.

[0157] In which, when the signal receiver receives the original signal, the first counter is controlled to start counting, and the count value of the first counter is used to represent the discrete first time value. At the same time, the signal receiver obtains the signal value of the sampling point in real time through the original sampling rate; the real-time obtained signal value is stored in parallel in the first FIFO data buffer of multiple filter groups; the real-time obtained first time value is stored in parallel in the second FIFO data buffer of multiple filter groups.

[0158] Furthermore, the variable sampling rate control module includes a second counter, an operator, a start value cache queue, an operation value cache queue and a controller, and the plurality of filter banks also include a comparator and a digital signal processor;

[0159] An input terminal of the second counter is connected to an output terminal of the signal receiver;

[0160] The input end of the arithmetic unit is connected to the output end of the second counter and the output end of the sampling rate configuration module;

[0161] The output end of the operator is connected to the input end of the startup value cache queue and the input end of the operation value cache queue;

[0162] The input end of the controller is connected to the output end of the startup value cache queue and the output end of the operation value cache queue;

[0163] The input end of the comparator is connected to the output end of the controller and the output end of the second FIFO data buffer, and the controller is also connected to the second counter and the digital signal processor;

[0164] The input end of the digital signal processor is connected to the output end of the comparator and the output end of the first FIFO data buffer;

[0165] The output end of the digital signal processor is connected to the input end of the sequential value module.

[0166] Among them, when the signal receiver receives the original signal, the second counter is controlled to start counting; the operator obtains the conversion factor according to the original sampling rate and target sampling rate output by the sampling rate configuration module, and obtains the discrete second time value based on the count value and conversion factor of the second counter.

[0167] The operator extracts the start value and the operation value from the second time value and stores them in the start value cache queue and the operation value cache queue respectively; the controller controls the start and stop of the second counter based on the remaining storage space size of the start value cache queue and the operation value cache queue.

[0168] The controller also determines the target number according to the numbering order of the filter groups, and sends the target number, start value and operation value to each filter group; when the number of the filter group is the same as the target number, the filter group is triggered to compare the received start value with the first time value stored earliest in the second FIFO data buffer; if the comparison is consistent, the signal interpolation is obtained based on the signal value stored in the filter group and the received operation value.

[0169] The various variations and specific examples of the signal sampling rate adaptive adjustment method provided above are also applicable to the signal sampling rate adaptive adjustment system provided in the present disclosure. Through the above detailed description of the signal sampling rate adaptive adjustment method, those skilled in the art can clearly understand the implementation method of the signal sampling rate adaptive adjustment system. For the sake of brevity of the specification, it will not be described in detail here.

[0170] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and not restrictive, and should not be construed as necessarily possessed by each embodiment of the present disclosure. Furthermore, the specific details disclosed above are provided for illustrative purposes and to facilitate understanding, rather than as limitations. These details do not limit the present disclosure to necessarily being implemented using these specific details.

[0171] In the present disclosure, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. The block diagrams of the devices, devices, equipment, and systems involved in the present disclosure are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, devices, equipment, and systems can be connected, arranged, or configured in any manner. Words such as "including," "comprising," "having," and the like are open-ended words, meaning "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or" and can be used interchangeably therewith, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0172] Additionally, as used herein, "or" used in a list of items beginning with "at least one" indicates a separate list, so that, for example, a list of "at least one of A, B, or C" means A or B or C, or AB or AC or BC, or ABC (i.e., A and B and C). Furthermore, the word "exemplary" does not mean that the example described is preferred or better than other examples.

[0173] It should also be noted that in the system and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0174] Various changes, substitutions, and modifications may be made to the technology described herein without departing from the teachings defined by the appended claims. Moreover, the scope of the claims of this disclosure is not limited to the specific aspects of the processes, machines, manufactures, compositions of things, means, methods, and actions described above. Currently existing or later developed processes, machines, manufactures, compositions of things, means, methods, or actions that perform substantially the same function or achieve substantially the same results as the corresponding aspects described herein may be utilized. Accordingly, the appended claims include within their scope such processes, machines, manufactures, compositions of things, means, methods, or actions.

[0175] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0176] The above description has been provided for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although a number of example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for adaptively adjusting a signal sampling rate, characterized in that: include: Get the original sampling rate and target sampling rate of the original signal; Receive the original signal, sample the original signal according to the original sampling rate, and obtain the signal value of the sampling point in real time; Discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate respectively to obtain a discrete first time value and a discrete second time value; The step of discretizing the sampling time of the original signal at the original sampling rate and the target sampling rate to obtain a discrete first time value and a discrete second time value comprises: When the original signal is received, the first counter and the second counter are started simultaneously, wherein the counting frequency of the second counter is higher than the counting frequency of the first counter; using the count value of the first counter to represent a discrete first time value; Obtaining a conversion factor based on the original sampling rate and the target sampling rate; acquiring a discrete second time value based on the count value of the second counter and the conversion factor; storing the real-time acquired signal value and the first time value in parallel into a plurality of filter banks; triggering the filter bank to perform an interpolation operation on the stored signal value based on the second time value and the first time value stored in the filter bank to obtain a signal interpolation value; The step of triggering the filter bank to perform an interpolation operation on the stored signal value based on the second time value and the first time value stored in the filter bank to obtain a signal interpolation value includes: extracting a start value and an operation value from the second time value; Determine a target number according to the numbering order of the filter groups, and send the target number, the start value, and the operation value to each filter group; When the number of the filter group is the same as the target number, triggering the filter group to compare the received start value with the earliest first time value stored in a second FIFO data buffer; wherein the second FIFO data buffer is the data buffer of the filter group; If the comparison is consistent, obtaining a signal interpolation value based on the signal value stored in the filter bank and the received operation value; The step of extracting the start value and the operation value from the second time value includes: extracting an integer part of the second time value as a start value; extracting a decimal part of the second time value as a calculation value; The step of obtaining a signal interpolation value based on the signal value stored in the filter bank and the received operation value comprises: constructing a signal column vector based on the signal values ​​stored by the filter bank; Obtaining a matrix mapping signal vector based on the signal column vector and a preset interpolation matrix; Obtaining a decreasing exponential column vector of the operation value based on the order N of the interpolation matrix; Obtaining a signal interpolation value based on the matrix mapping signal vector and the decreasing index column vector; The signal interpolations are sorted according to the working timing of the plurality of filter groups, and the sorted signal interpolations are output according to the target sampling rate to form a target signal.

2. The signal sampling rate adaptive adjustment method according to claim 1, characterized in that: The step of storing the real-time acquired signal value and the first time value in parallel into a plurality of filter banks comprises: storing the real-time acquired signal values ​​in parallel in the first FIFO data buffers of the plurality of filter banks; The first time value acquired in real time is stored in parallel in the second FIFO data buffers of the plurality of filter banks.

3. The signal sampling rate adaptive adjustment method according to claim 1, characterized in that: Also includes: Storing the startup value and the operation value in a startup value cache queue and an operation value cache queue respectively; The start and stop of the second counter are controlled based on the remaining storage space sizes of the startup value cache queue and the operation value cache queue.

4. A signal sampling rate adaptive adjustment system, configured to execute the signal sampling rate adaptive adjustment method according to any one of claims 1 to 3, characterized in that: It includes a signal front-end processing module, multiple filter groups, a variable sampling rate control module, a sequential value module and a FIFO buffer; The input end of the signal front-end processing module is connected to the output end of the signal source; The input end of the variable sampling rate control module is connected to the output end of the sampling rate configuration module; The output end of the signal front-end processing module and the output end of the variable sampling rate control module are both connected to the input ends of the multiple filter groups, and the variable sampling rate control module is connected to the signal front-end processing module; The output ends of the plurality of filter groups are connected to the input end of the sequential value taking module; The output end of the sequential value taking module is connected to the input end of the FIFO buffer.

5. The signal sampling rate adaptive adjustment system according to claim 4, characterized in that: The signal front-end processing module includes a signal receiver and a first counter, and the plurality of filter banks each include a first FIFO data buffer and a second FIFO data buffer; The input end of the signal receiver is connected to the output end of the signal source; The output end of the signal receiver is connected to the input end of the first counter and the input end of the first FIFO data buffer respectively; The output end of the first counter is connected to the input end of the second FIFO data buffer.

6. The signal sampling rate adaptive adjustment system according to claim 5, characterized in that: The variable sampling rate control module includes a second counter, an operator, a start value cache queue, an operation value cache queue and a controller, and the multiple filter banks also include a comparator and a digital signal processor; An input terminal of the second counter is connected to an output terminal of the signal receiver; The input end of the operator is connected to the output end of the second counter and the output end of the sampling rate configuration module; The output end of the operator is connected to the input end of the startup value cache queue and the input end of the operation value cache queue; The input end of the controller is connected to the output end of the startup value cache queue and the output end of the operation value cache queue; The input end of the comparator is connected to the output end of the controller and the output end of the second FIFO data buffer, and the controller is also connected to the second counter and the digital signal processor; An input terminal of the digital signal processor is connected to an output terminal of the comparator and an output terminal of the first FIFO data buffer; The output end of the digital signal processor is connected to the input end of the sequential value taking module.

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