Successive approximation type analog-to-digital converter based on comparator relative gain
By splitting the DAC into high and low DACs and leveraging the relative gain of the four-input comparator, the DAC power and area problems in SAR ADC are solved, achieving lower power and area.
Patent Information
- Application Number
- CN202510341706.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-21
- Publication Date
- 2025-07-11
AI Technical Summary
The power consumption and area problems of DACs in existing SAR ADCs grow exponentially with the increase of digits, becoming a bottleneck that limits its further reduction of power consumption and area.
Using a design based on the comparator relative gain, the DAC is split into a high- and low-dAC, and the relative gain of the four-input comparator provides the reference voltage required for the high- and low-date digital codes, respectively, reducing the total number of capacitors.
It greatly reduces the size and power consumption of the DAC, and achieves lower power consumption and area, and reduces the total unit capacitance to 2M+1+2N-M compared to traditional SAR ADCs.
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Figure CN120301425A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of integrated circuit design, and in particular relates to a successive approximation analog-to-digital converter based on relative gain of a comparator. Background Art
[0002] SAR ADC (Successive Approximation Register Analog to Digital Converter) is widely used in communications, biomedicine, industrial control, consumer electronics, Internet of Things, audio and video processing, automotive electronics and other fields. With the rapid development of integrated circuit technology and the continuous improvement of the integration of electronic information systems, these application fields have put forward higher requirements on the performance of SAR ADC, especially the power consumption and area, which have put forward more stringent requirements on low power consumption and small area.
[0003] In the design of SAR ADC, DAC (Digital to Analog Converter) is one of its core components, and its power consumption and area overhead account for a considerable proportion. The power consumption and area of DAC are proportional to the capacitance of DAC, and increase exponentially with the increase of SAR ADC bit number. When the bit number of SAR ADC exceeds 12 bits, the power consumption and area problem of DAC becomes particularly prominent, becoming the biggest bottleneck restricting SAR ADC from further reducing power consumption and area.
[0004] Therefore, how to reduce the power consumption and area overhead of DAC in SAR ADC has become a technical problem that needs to be solved urgently. Summary of the invention
[0005] In order to solve the above problems existing in the prior art, the present invention provides a successive approximation analog-to-digital converter based on the relative gain of a comparator. The technical problem to be solved by the present invention is achieved by the following technical solutions:
[0006] The present invention provides a successive approximation analog-to-digital converter based on comparator relative gain, comprising: a high-bit DAC, a low-bit DAC, a four-input comparator and SAR logic, wherein:
[0007] The upper plate of the capacitor of the high-bit DAC collects the input differential signal and is connected to the high-gain differential input pair of the four-input comparator. The high-bit DAC is used to provide a reference voltage required for quantizing the M-bit high-bit digital code;
[0008] The upper plates of the capacitors of the low-order DAC receive a common-mode voltage and are connected to the low-gain differential input pair of the four-input comparator. The low-order DAC is used to provide a reference voltage required for quantifying an (N - M)-bit low-order digital code; both M and N are integers greater than 2, and N > M.
[0009] The four-input comparator is used to compare the output voltage of the high-order DAC and the output voltage of the low-order DAC to obtain each bit of the digital code; the relative gain between the high-gain differential input pair and the low-gain differential input pair of the four-input comparator is 2 M times;
[0010] The input end of the SAR logic is connected to the output end of the four-input comparator. The SAR logic is used to latch each bit of the digital code and adjust the reference voltages of the high-order DAC and the low-order DAC according to each bit of the digital code, and output the latched digital code to obtain an N-bit digital code.
[0011] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0012] The successive approximation analog-to-digital converter based on the relative gain of the comparator of the present invention splits a traditional large-overhead DAC into two small-overhead DACs, namely a high-order DAC and a low-order DAC, by means of the relative gain of the four-input comparator. The high-order DAC is used to provide a reference voltage required for quantifying an M-bit high-order digital code, and the low-order DAC is used to provide a reference voltage required for quantifying an (N - M)-bit low-order digital code, so as to implement an N-bit digital code. Compared with the traditional SAR ADC, the total number of unit capacitors of the present invention is reduced to 2 M+1 +2 N -M pieces, greatly reducing the size of the DAC and having lower power consumption and area than the traditional SAR ADC.
[0013] The above description is only an overview of the technical solution of the present invention. In order to be able to understand the technical means of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the drawings, is described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 is a structural diagram of a successive approximation analog-to-digital converter based on the relative gain of the comparator provided by an embodiment of the present invention;
[0015] Figure 2 is a circuit diagram of a four-input comparator provided by an embodiment of the present invention;
[0016] Figure 3 is a control clock diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present invention. Detailed implementation manners
[0017] In order to further elaborate on the technical means and effects adopted by the present invention to achieve the intended invention purpose, the following, in combination with the accompanying drawings and specific implementation manners, will provide a detailed description of a successive approximation analog-to-digital converter based on the relative gain of a comparator according to the present invention.
[0018] The foregoing and other technical contents, features, and effects of the present invention can be clearly presented in the following detailed description in conjunction with the accompanying drawings. Through the description of the specific implementation manners, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and illustration purposes, and are not used to limit the technical solutions of the present invention.
[0019] An embodiment of the present invention provides a successive approximation analog-to-digital converter based on the relative gain of a comparator. Please refer to Figure 1 , Figure 1 which is a structural diagram of a successive approximation analog-to-digital converter based on the relative gain of a comparator provided by an embodiment of the present invention. As shown in Figure 1 , the successive approximation analog-to-digital converter based on the relative gain of a comparator in this embodiment includes: a high-order DAC, a low-order DAC, a four-input comparator, and SAR logic.
[0020] Among them, the upper plates of the capacitors of the high-order DAC collect the input differential signal and are connected to the high-gain differential input pair of the four-input comparator. The high-order DAC is used to provide the reference voltage required for quantifying the M-bit high-order digital code; the upper plates of the capacitors of the low-order DAC input the common-mode voltage and are connected to the low-gain differential input pair of the four-input comparator. The low-order DAC is used to provide the reference voltage required for quantifying the (N - M)-bit low-order digital code; both M and N are integers greater than 2, and N > M.
[0021] The four-input comparator is used to compare the output voltage of the high-order DAC and the output voltage of the low-order DAC to obtain each bit of the digital code. In this embodiment, the relative gain between the high-gain differential input pair and the low-gain differential input pair of the four-input comparator is 2 M times, which is used to align the output voltage ranges of the high-order DAC and the low-order DAC.
[0022] The input end of the SAR logic is connected to the output end of the four-input comparator. The SAR logic is used to latch each bit of the digital code and adjust the reference voltages of the high-order DAC and the low-order DAC according to each bit of the digital code, and output the latched digital code to obtain an N-bit digital code.
[0023] In an alternative embodiment, the high - order DAC includes a positive - terminal sampling switch, a negative - terminal sampling switch, a first positive - terminal capacitor array, a first negative - terminal capacitor array, a first positive - terminal load capacitor, and a first negative - terminal load capacitor.
[0024] Among them, the first terminals of the positive - terminal sampling switch and the negative - terminal sampling switch (switch S in the figure a ) input differential signals V IN,P and V IN,N . The second terminal of the positive - terminal sampling switch is connected to the upper plates of the capacitors in the first positive - terminal capacitor array; the lower plates of the capacitors in the first positive - terminal capacitor array receive the positive reference voltage V refp , the negative reference voltage V refn or the common - mode voltage V cm through the first positive - terminal selection switch. The second terminal of the negative - terminal sampling switch is connected to the upper plates of the capacitors in the first negative - terminal capacitor array; the lower plates of the capacitors in the first negative - terminal capacitor array receive the positive reference voltage V refp , the negative reference voltage V refn or the common - mode voltage V cm through the first negative - terminal selection switch. The upper plate of the first positive - terminal load capacitor is connected to the second terminal of the positive - terminal sampling switch, and the lower plate inputs the common - mode voltage V cm ; the upper plate of the first negative - terminal load capacitor is connected to the second terminal of the negative - terminal sampling switch, and the lower plate inputs the common - mode voltage V cm .
[0025] In this embodiment, the sizes of the capacitors connected in parallel in the first positive - terminal capacitor array and the first negative - terminal capacitor array increase in binary. The size of the highest - order capacitor in the first positive - terminal capacitor array and the first negative - terminal capacitor array is 2 M-1 C u , and the sizes of the first positive - terminal load capacitor and the first negative - terminal load capacitor are C u , where C u is the unit capacitor.
[0026] In an alternative embodiment, the low - order DAC includes a positive - terminal reset switch, a negative - terminal reset switch, a second positive - terminal capacitor array, a second negative - terminal capacitor array, a second positive - terminal load capacitor, and a second negative - terminal load capacitor.
[0027] Among them, the positive - terminal reset switch and the negative - terminal reset switch (switch S in the figure b ) input the common - mode voltage V cm . The second terminal of the positive - terminal reset switch is connected to the upper plates of the capacitors in the second positive - terminal capacitor array; the lower plates of the capacitors in the second positive - terminal capacitor array receive the positive reference voltage V refp , the negative reference voltage V refn or the common - mode voltage V cm。The second terminal of the negative terminal reset switch is connected to the upper plate of the capacitor in the second negative terminal capacitor array; the lower plate of the capacitor in the second negative terminal capacitor array receives the positive reference voltage V refp , the negative reference voltage V refn or the common mode voltage V cm through the second negative terminal selection switch. The upper plate of the second positive terminal load capacitor is connected to the second terminal of the positive terminal reset switch, and the lower plate inputs the common mode voltage V cm ; the upper plate of the second negative terminal load capacitor is connected to the second terminal of the negative terminal reset switch, and the lower plate inputs the common mode voltage V cm .
[0028] In this embodiment, the capacitance values of the capacitors connected in parallel in the second positive terminal capacitor array and the second negative terminal capacitor array increase in binary. The capacitance value of the highest bit capacitor in the second positive terminal capacitor array and the second negative terminal capacitor array is 2 N-M-2 C u , and the capacitance values of the second positive terminal load capacitor and the second negative terminal load capacitor are C u , C u being the unit capacitance.
[0029] Furthermore, the four-input comparator of this embodiment will be described in detail. Please continue to refer to Figure 1 . In this embodiment, the positive input terminal of the high-gain differential input pair of the four-input comparator is connected to the upper plate of the capacitor in the first positive terminal capacitor array and the upper plate of the first positive terminal load capacitor, and the negative input terminal is connected to the upper plate of the capacitor in the first negative terminal capacitor array and the upper plate of the first negative terminal load capacitor. The positive input terminal of the low-gain differential input pair of the four-input comparator is connected to the upper plate of the capacitor in the second positive terminal capacitor array and the upper plate of the second positive terminal load capacitor, and the negative input terminal is connected to the upper plate of the capacitor in the second negative terminal capacitor array and the upper plate of the second negative terminal load capacitor.
[0030] Please refer to Figure 2 . Figure 2 is a circuit diagram of a four-input comparator provided by an embodiment of the present invention. As shown in Figure 2 , the four-input comparator includes transistors M1 to M 13 . The gate of transistor M1 serves as the positive input terminal of the high-gain differential input pair, the gate of transistor M2 serves as the negative input terminal of the high-gain differential input pair, the gate of transistor M3 serves as the positive input terminal of the low-gain differential input pair, the gate of transistor M4 serves as the negative input terminal of the low-gain differential input pair. The sources of transistors M1, M2, M3, and M4 are all connected to the drain of transistor M5. The source of transistor M5 is grounded, and the gate inputs the control clock Φ C . The drain of transistor M1 is connected to the source of transistor M8, the drain of transistor M2 is connected to the source of transistor M 13 , the drain of transistor M3 is connected to the source of transistor M 12The source of transistor M4 is connected to the source of transistor M9. The drain of transistor M 12 and M 13 have their gates input with the control clock Φ C , and their drains are both connected to the voltage terminal. The drain of transistor M8 is respectively connected to the sources of transistors M 10 and M6, and its gate is connected to the gate of transistor M6. The drain of transistor M9 is respectively connected to the sources of transistors M7 and M 11 , and its gate is connected to the gate of transistor M7. The drains of transistors M 10 , M6, M7 and M 11 are all connected to the voltage terminal. The gates of transistors M 10 and M 11 are both input with the control clock Φ C . The gates of transistors M6 and M7 are used as the output terminals of a four-input comparator to output differential signals V OUTP , V OUTN , and the gates of transistors M6 and M7 are respectively grounded through capacitors.
[0031] In this embodiment, transistors M1 and M2 form a high-gain differential input pair, and transistors M3 and M4 form a low-gain differential input pair. Transistors M1 and M2 have the same size, and transistors M3 and M4 have the same size. Transistors M1, M2, M3 and M4 have the same gate length, but the width-to-length ratio of transistors M1 and M2 is 2 M times that of transistors M3 and M4. Therefore, the relative gain of the high-gain differential input pair with respect to the low-gain differential input pair is 2 M times. When the control clock Φ C becomes low, transistors M 10 , M 11 , M 12 and M 13 conduct, and transistor M5 turns off, causing the output signals V OUTP and V OUTN of the four-input comparator to be reset to VDD (i.e., high level). When the control clock Φ C becomes high, transistors M 10 , M 11 , M 12 and M 13 turn off, and transistor M5 conducts, and according to the magnitude of the input signal, the comparator outputs a high level or a low level.
[0032] Specifically, when [V 高位,P -V 高位,N +(V 低位,P -V 低位,N ) / 2 M is greater than 0, the four-input comparator outputs V OUTP to remain high, VOUTN goes low; when [V 高位,P - V 高位,N +(V 低位,P - V 低位,N ) / 2 M is less than 0, the four - input comparator outputs V OUTP goes low and V OUTN remains high.
[0033] In this embodiment, the first control terminal of the SAR logic is connected to the first positive - terminal selection switch and the first negative - terminal selection switch; the second control terminal of the SAR logic is connected to the second positive - terminal selection switch and the second negative - terminal selection switch. When quantifying the high - order M - bit digital code, the SAR logic controls the switching of the first positive - terminal selection switch and the first negative - terminal selection switch according to the input digital code by using a V cm - based switching strategy to adjust the reference voltage of the high - order DAC and keep the reference voltage of the low - order DAC unchanged. When quantifying the low - order (N - M) - bit digital code, the SAR logic controls the switching of the second positive - terminal selection switch and the second negative - terminal selection switch according to the input digital code by using a V cm - based switching strategy to adjust the reference voltage of the low - order DAC and keep the reference voltage of the high - order DAC unchanged.
[0034] In a traditional SAR ADC, there is only 1 DAC, and the comparator is two - input and connected to the upper - plate of the single DAC. The DAC is composed of 2 N unit capacitors C u . In the SAR ADC of this embodiment, the high - order DAC is composed of 2 M+1 unit capacitors Cu, and the low - order DAC is composed of 2 N-M unit capacitors Cu. Therefore, the total capacitance of the high - order DAC and the low - order DAC is 2 M+1 +2 N-M . Since N > M, so 2 M+1 +2 N-M <2 N . Exemplarily, assume N = 16, M = 8. Then the total capacitance of the DAC in the SAR ADC of this embodiment is 2 9 +2 8 = 768 unit capacitors, while the total capacitance of the DAC in the traditional SAR ADC is 2 16 = 65536 unit capacitors.
[0035] The successive approximation analog-to-digital converter based on the relative gain of a comparator according to an embodiment of the present invention splits a traditional large-overhead DAC into two small-overhead DACs, namely a high-order DAC and a low-order DAC, by means of the relative gain of a four-input comparator. The high-order DAC provides the reference voltage required for quantifying the M-bit high-order digital code, and the low-order DAC provides the reference voltage required for quantifying the (N - M)-bit low-order digital code, thereby realizing an N-bit digital code. Compared with a traditional SAR ADC, the total number of unit capacitors of the successive approximation analog-to-digital converter according to the embodiment of the present invention is reduced to 2 M+1 +2 N-M pieces, significantly reducing the size of the DAC and having lower power consumption and area than a traditional SAR ADC.
[0036] Further, the working process of the successive approximation analog-to-digital converter based on the relative gain of a comparator according to this embodiment is described.
[0037] Please refer to Figure 3 , Figure 3 which is a control clock diagram of a successive approximation analog-to-digital converter provided by an embodiment of the present invention. As shown in Figure 3 , Φ S is the control clock of the sampling switch S a and the reset switch S b , and Φ C is the control clock of the four-input comparator.
[0038] When Φ S is at a high level, the switches S a and S b conduct, the upper plates of the capacitors of the high-order DAC sample the input signal, and the lower plates are connected to the common-mode voltage V cm ; the upper and lower plates of the capacitors of the low-order DAC are both reset and connected to the common-mode voltage V cm . When Φ S becomes low, the switches S a and S b disconnect, the input signal is collected on the upper plates of the capacitors of the high-order DAC, and the upper plates of the capacitors of the low-order DAC first maintain the common-mode voltage V cm . The four-input comparator is reset. Then, the four-input comparator starts to work under the control of Φ C . When Φ C becomes high, the four-input comparator starts to work, compares the voltages at the input ends of the comparator, and obtains the highest-order digital code. The SAR logic latches the highest-order digital code and controls the highest-order capacitor 2 cm of the high-order DAC using a V M-1 C uThe lower plate of is switched. If the highest - order digit code is 1, the highest - order capacitor 2 at the P - terminal of the high - order DAC M-1 C u The lower plate of is switched from the common - mode voltage V cm to the negative reference voltage V refn , and the highest - order capacitor 2 at the N - terminal of the high - order DAC M-1 C u The lower plate of is switched from the common - mode voltage V cm to the positive reference voltage V refp . If the highest - order digit code is 0, the highest - order capacitor 2 at the P - terminal of the high - order DAC M-1 C u The lower plate of is switched from the common - mode voltage V cm to the positive reference voltage V refp , and the highest - order capacitor 2 at the N - terminal of the high - order DAC M-1 C u The lower plate of is switched from the common - mode voltage V cm to the negative reference voltage V refn . While the lower - plate switch of the capacitor of the high - order DAC is being switched, Φ C becomes low level, and the four - input comparator is reset. Then, Φ C becomes high level. At this time, the lower - plate switch of the capacitor of the high - order DAC has completed the switching, and the four - input comparator compares the input - terminal voltage again to obtain the second - highest - order digit code. The SAR logic latches the second - highest - order digit code and controls the lower plate of the second - highest - order capacitor 2 of the high - order DAC M-2 C u to be switched. And so on, until the M - bit high - order digit code is obtained. It should be noted that when quantifying the M - bit high - order digit code, only the voltage of the lower plate of the capacitor of the high - order DAC is switched, while the voltage of the capacitor of the low - order DAC remains unchanged all the time.
[0039] Then, starting from the (N - M) - th digit code, instead of switching the voltage of the lower plate of the capacitor of the high - order DAC, the voltage of the lower plate of the capacitor of the low - order DAC is switched. Similar to the high - order DAC, when the (N - M) - th digit code is 1, the highest - order capacitor 2 at the P - terminal of the low - order DAC N-M-2 C u The lower plate of is switched from the common - mode voltage V cm to the negative reference voltage V refn , and the highest - order capacitor 2 at the N - terminal of the low - order DAC N-M-2 C u The lower plate of is switched from the common - mode voltage V cm to the positive reference voltage V refp . If the (N - M) - th digit code is 0, the highest - order capacitor 2 at the P - terminal of the low - order DAC N-M-2 C u The lower plate of is switched from the common - mode voltage Vcm Switch to the positive reference voltage V refp , and for the highest-order capacitor 2 at the N terminal of the lower-order DAC N-M-2 C u , the lower plate of which switches from the common-mode voltage V cm to the negative reference voltage V refn . And so on until the N-M-bit lower-order digital code is obtained.
[0040] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements includes not only those elements but also other elements not expressly listed. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.
[0041] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not have to be directed to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine the different embodiments or examples described in this specification.
[0042] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present invention.
Claims
1. A successive approximation analog-to-digital converter based on the relative gain of a comparator, characterized in that Comprising: A high - order DAC, a low - order DAC, a four - input comparator, and SAR logic, wherein The upper plates of the capacitors of the high - order DAC collect the input differential signal and are connected to the high - gain differential input pair of the four - input comparator. The high - order DAC is used to provide the reference voltage required for quantifying the M - bit high - order digital code; The upper plates of the capacitors of the low - order DAC input the common - mode voltage and are connected to the low - gain differential input pair of the four - input comparator. The low - order DAC is used to provide the reference voltage required for quantifying the (N - M) - bit low - order digital code; Both M and N are integers greater than 2, and N > M; The four-input comparator is used to compare the output voltage of the high-order DAC and the output voltage of the low-order DAC to obtain each digital code; the relative gain between the high-gain differential input pair and the low-gain differential input pair of the four-input comparator is 2 M times; The input end of the SAR logic is connected to the output end of the four - input comparator. The SAR logic is used to latch each bit of the digital code and adjust the reference voltage of the high - order DAC and the reference voltage of the low - order DAC according to each bit of the digital code, and output the latched digital code to obtain an N - bit digital code.
2. The successive approximation analog-to-digital converter based on the relative gain of the comparator according to claim 1, wherein The high - order DAC includes a positive - end sampling switch, a negative - end sampling switch, a first positive - end capacitor array, a first negative - end capacitor array, a first positive - end load capacitor, and a first negative - end load capacitor, wherein The first ends of the positive - end sampling switch and the negative - end sampling switch input the differential signal; The second end of the positive - end sampling switch is connected to the upper plates of the capacitors in the first positive - end capacitor array; The lower plates of the capacitors in the first positive - end capacitor array receive the positive reference voltage, the negative reference voltage, or the common - mode voltage through the first positive - end selection switch; The second end of the negative - end sampling switch is connected to the upper plates of the capacitors in the first negative - end capacitor array; The lower plates of the capacitors in the first negative - end capacitor array receive the positive reference voltage, the negative reference voltage, or the common - mode voltage through the first negative - end selection switch; The upper plate of the first positive - end load capacitor is connected to the second end of the positive - end sampling switch, and the lower plate inputs the common - mode voltage; The upper plate of the first negative - end load capacitor is connected to the second end of the negative - end sampling switch, and the lower plate inputs the common - mode voltage.
3. The successive approximation analog-to-digital converter based on the relative gain of the comparator according to claim 2, wherein The sizes of the capacitors connected in parallel in the first positive - end capacitor array and the first negative - end capacitor array increase in binary.
4. The successive approximation analog-to-digital converter based on the relative gain of a comparator according to claim 2, wherein The low - order DAC includes a positive - end reset switch, a negative - end reset switch, a second positive - end capacitor array, a second negative - end capacitor array, a second positive - end load capacitor, and a second negative - end load capacitor, wherein The first ends of the positive - end reset switch and the negative - end reset switch input the common - mode voltage; The second end of the positive - end reset switch is connected to the upper plates of the capacitors in the second positive - end capacitor array; The lower plates of the capacitors in the second positive - end capacitor array receive the positive reference voltage, the negative reference voltage, or the common - mode voltage through the second positive - end selection switch; The second end of the negative - end reset switch is connected to the upper plates of the capacitors in the second negative - end capacitor array; The lower plates of the capacitors in the second negative - end capacitor array receive the positive reference voltage, the negative reference voltage, or the common - mode voltage through the second negative - end selection switch; The upper plate of the second positive terminal load capacitor is connected to the second terminal of the positive terminal reset switch, and the common-mode voltage is input to the lower plate; the upper plate of the second negative terminal load capacitor is connected to the second terminal of the negative terminal reset switch, and the common-mode voltage is input to the lower plate.
5. The successive approximation analog-to-digital converter based on the relative gain of the comparator according to claim 4, wherein The capacitances of the capacitors connected in parallel in the second positive terminal capacitor array and the second negative terminal capacitor array increase in binary.
6. The successive approximation analog-to-digital converter based on the relative gain of the comparator according to claim 4, wherein The positive input terminal of the high-gain differential input pair is connected to the upper plates of the capacitors in the first positive terminal capacitor array and the upper plate of the first positive terminal load capacitor, and the negative input terminal is connected to the upper plates of the capacitors in the first negative terminal capacitor array and the upper plate of the first negative terminal load capacitor; The positive input terminal of the low-gain differential input pair is connected to the upper plates of the capacitors in the second positive terminal capacitor array and the upper plate of the second positive terminal load capacitor, and the negative input terminal is connected to the upper plates of the capacitors in the second negative terminal capacitor array and the upper plate of the second negative terminal load capacitor.
7. The successive approximation analog-to-digital converter based on the relative gain of a comparator according to claim 4, wherein The first control terminal of the SAR logic is connected to the first positive terminal selection switch and the first negative terminal selection switch; the second control terminal of the SAR logic is connected to the second positive terminal selection switch and the second negative terminal selection switch.
8. The successive approximation analog-to-digital converter based on the relative gain of the comparator according to claim 7, wherein When quantizing the M-bit high-order digital code, the SAR logic adopts a V cm -based switch switching strategy to control the switching of the first positive terminal selection switch and the first negative terminal selection switch to adjust the reference voltage of the high-order DAC, and keep the reference voltage of the low-order DAC unchanged; When quantifying the N-M bit low-order digital code, the SAR logic adopts a V cm -based switch switching strategy to control the switching of the second positive terminal selection switch and the second negative terminal selection switch to adjust the reference voltage of the low-order DAC, and keep the reference voltage of the high-order DAC unchanged.