Polarization code parallel processing method and device

Abstract

The invention relates to a polar code parallel processing method and device, and the method comprises the steps: carrying out the parallel triangular interleaving operation of a polar code through employing a triangular interleaving address table; the method comprises the following steps: setting a parity check bit register with the same length as a mother code, and initializing the first K bits of the parity check bit register into the first K bits of an input bit stream; performing XOR operation on the K bits of the nth group of the parity check bit register and the K bits of the (n + 1) th group of the input bit stream, and storing an obtained result into the K bits of the (n + 1) th group of the parity check bit register; and performing AND operation on the data stored in the parity check bit register and the data stored in the mask register to obtain three parity check bit values. According to the invention, time delay can be obviously reduced.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and in particular, to a method and apparatus for parallel processing of polar codes. Background Art

[0002] During the rate matching process of the polar code of the uplink control channel, there is a triangular interleaving operation. Among them, the triangular interleaver is composed of an isosceles triangle with a length of T. As Figure 1 shown, the side length T of the isosceles triangle is 8. The bits e0 to e7 of the polar code are written into the first row of the isosceles triangle, and the bits e8 to e 14 bits are written into the second row of the isosceles triangle, and the bits e 15 ~e 20 bits are written into the third row of the isosceles triangle, and the bits e 21 ~e 25 bits are written into the fourth row of the isosceles triangle, and the bits e 26 ~e 29 bits are written into the fifth row of the isosceles triangle, and the bits e 30 ~e 32 bits are written into the sixth row of the isosceles triangle, and the bits e 33 ~e 34 bits are written into the seventh row of the isosceles triangle, and the bits e 35 bits are written into the eighth row of the isosceles triangle. At this time, the isosceles triangle is written row by row. Because the actual data only reaches the e 31 bits, so e 32 ~e 35 are filled with NULL, and then read out column by column from the isosceles triangle, skipping the NULL values. Due to the requirements of throughput and latency for polar codes, the method of writing row by row and then reading column by column in triangular interleaving obviously cannot meet the requirements of high throughput and low latency. In addition, currently, the parity check (PC) bits of the PC-polar of the polar code of the uplink control channel are generated in a serial manner in the protocol, and this method of generating bit by bit serially cannot meet the requirements of low latency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a method and apparatus for parallel processing of polar codes, which can significantly reduce latency.

[0004] The technical solution adopted by the present invention to solve its technical problem is: to provide a method for parallel processing of polar codes, including the following steps:

[0005] Perform triangular interleaving operation on the polar code in parallel using a triangular interleaving address table;

[0006] Set a parity check bit register with the same length as the mother code, and initialize the first 5 bits of the parity check bit register to the first 5 bits of the input bit stream;

[0007] Perform an exclusive OR operation on the 5 bits of the nth group of the parity check bit register and the 5 bits of the (n + 1)th group of the input bit stream, and store the obtained result in the 5 bits of the (n + 1)th group of the parity check bit register;

[0008] Perform an AND operation on the data stored in the parity check bit register and the data stored in the mask register to obtain three parity check bit values. Among them, the positions of the three parity check bits in the data stored in the mask register are 1, and the remaining positions are 0;

[0009] Where n is a positive integer.

[0010] After obtaining the three parity check bit values, it further includes:

[0011] Store the obtained three parity check bit values in a value register with the same length as the mother code;

[0012] Perform an exclusive OR operation on the data stored in the value register and the input bit stream to obtain information bits.

[0013] The triangular interleaving operation of the polar code is completed in parallel using a triangular interleaving address table, specifically including:

[0014] Calculate the length of the triangular interleaver used in the triangular interleaving operation according to the rate matching length;

[0015] Determine the triangular interleaving address table according to the length of the triangular interleaver;

[0016] Perform a triangular interleaving operation on the polar code, and execute it in parallel according to the triangular interleaving address table during the triangular interleaving operation.

[0017] The length of the triangular interleaver is obtained through Calculated, where T is the length of the triangular interleaver and E is the rate matching length, Indicates rounding up.

[0018] The determination of the triangular interleaving address table according to the length of the triangular interleaver specifically includes:

[0019] Calculate the triangular interleaving address according to the length of the triangular interleaver. The triangular interleaving address is expressed as: address(i,j) = iT + j - i*(i - 1) / 2;

[0020] When \(i + j \lt T\) and \(address(i,j) \lt E\), store the triangular interleaving address column - by - column into the triangular interleaving address table;

[0021] Where \(address(i,j)\) is the triangular interleaving address, \(i\) is the row index, \(j\) is the column index, both \(i\) and \(j\) are natural numbers, \(T\) is the length of the triangular interleaver, and \(E\) is the rate - matching length.

[0022] The technical solution adopted by the present invention to solve its technical problems is: to provide a parallel processing device for polar codes, including:

[0023] A triangular interleaving module, which is used to perform triangular interleaving operations on polar codes in parallel by using a triangular interleaving address table;

[0024] An initialization module, which is used to set a parity - check bit register with the same length as the mother code, and initialize the first 5 bits of the parity - check bit register as the first 5 bits of the input bit stream;

[0025] A first exclusive - OR operation module, which is used to perform an exclusive - OR operation on 5 bits of the \(n\) - th group of the parity - check bit register and 5 bits of the \((n + 1)\) - th group of the input bit stream, and store the obtained result into 5 bits of the \((n + 1)\) - th group of the parity - check bit register;

[0026] An AND operation module, which is used to perform an AND operation on the data stored in the parity - check bit register and the data stored in the mask register to obtain three parity - check bit values. Among them, the positions of the three parity - check bits in the data stored in the mask register are 1, and the remaining positions are 0;

[0027] Where \(n\) is a positive integer.

[0028] The above - mentioned parallel processing device for polar codes further includes:

[0029] A storage module, which is used to store the obtained three parity - check bit values into a value register with the same length as the mother code;

[0030] A second exclusive - OR operation module, which is used to perform an exclusive - OR operation on the data stored in the value register and the input bit stream to obtain information bits.

[0031] The triangular interleaving module includes:

[0032] A length calculation unit, which is used to calculate the length of the triangular interleaver used in the triangular interleaving operation according to the rate - matching length;

[0033] An address - table determination unit, which is used to determine the triangular interleaving address table according to the length of the triangular interleaver;

[0034] An interleaving operation unit is used to perform a triangular interleaving operation on the polar code and execute it in parallel according to the triangular interleaving address table during the triangular interleaving operation.

[0035] The technical solution adopted by the present invention to solve its technical problems is to provide an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the above-mentioned parallel processing method of the polar code are implemented.

[0036] The technical solution adopted by the present invention to solve its technical problems is to provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned parallel processing method of the polar code are implemented.

[0037] Beneficial effects

[0038] Due to the adoption of the above technical solution, compared with the prior art, the present invention has the following advantages and positive effects: The present invention adopts a parallel processing method, enabling three PC bits to be directly generated in parallel, thereby reducing the encoding delay of PC-polar. At the same time, the present invention also establishes a triangular interleaving address table, which can be executed in parallel according to this triangular interleaving address table during the triangular interleaving operation, thereby improving the throughput of the polar code and reducing the delay. Description of the drawings

[0039] Figure 1 is a standard flowchart of the triangular interleaving operation in the prior art;

[0040] Figure 2 is a flowchart of the parallel processing method of the polar code in the first embodiment of the present invention;

[0041] Figure 3 is a schematic diagram of the triangular interleaving address calculation in the first embodiment of the present invention;

[0042] Figure 4 is a schematic diagram of the parity check bit register in the first embodiment of the present invention. Specific embodiments

[0043] The following further elaborates the present invention in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and not to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims of this application.

[0044] The first embodiment of the present invention relates to a parallel processing method of a polar code, including a triangular interleaving parallel operation method and a parity check bit parallel generation method, as Figure 2As shown in the figure, it specifically includes:

[0045] Step 1: Perform triangular interleaving operation on the polar code in parallel using a triangular interleaving address table. The specific steps are as follows:

[0046] First, calculate the length of the triangular interleaver used in the triangular interleaving operation according to the rate matching length. The specific calculation method is as follows:

[0047]

[0048] where T is the length of the triangular interleaver, E is the rate matching length, represents rounding up.

[0049] Then, determine the triangular interleaving address table according to the length of the triangular interleaver. As Figure 3 shown, calculate the triangular interleaving address according to the length of the triangular interleaver. The calculation formula is: address(i,j) = iT + j - i*(i - 1) / 2, where i is the row index, j is the column index, and both i and j are natural numbers; then, when i + j < T and address(i,j) < E, store the triangular interleaving address into the triangular interleaving address table column by column.

[0050] Finally, perform triangular interleaving operation on the polar code and execute it in parallel according to the triangular interleaving address table during the triangular interleaving operation.

[0051] Through the triangular interleaving parallel operation method adopted in the above Step 1, it can be executed in parallel according to the triangular interleaving address table, thereby improving the throughput of the polar code and reducing the latency.

[0052] In the prior art, PC bits are generated serially in the protocol, which is equivalent to a linear feedback shift register in hardware, and its generating polynomial is x 5 + 1. Based on this, a method for parallel generation of parity check bits with a parallelism of 5 can be adopted, specifically as Steps 2 - 4.

[0053] Step 2: Set a parity check bit register with the same length as the mother code, and initialize the first 5 bits of the parity check bit register to the first 5 bits of the input bit stream. Taking the mother code length of 1024 as an example, the parity check bit register set in this embodiment is pc_reg[1023:0], and the first 5 bits of this parity check bit register are initialized to the first 5 bits Q_N[4:0] of the input bit stream, that is, pc_reg[4:0] = Q_N[4:0].

[0054] Step 3: Perform an exclusive OR operation on the 5 bits of the nth group of the parity check bit register and the K bits of the (n + 1)th group of the input bit stream, and store the obtained result in the 5 bits of the (n + 1)th group of the parity check bit register, where n is a positive integer. As Figure 4 shown, perform an exclusive OR operation on the 5 bits of the first group in the parity check bit register and the bits of the second group of the input bit stream, store the obtained result in the 5 bits of the second group of the parity check bit register, perform an exclusive OR operation on the 5 bits of the second group in the parity check bit register and the bits of the third group of the input bit stream, store the obtained result in the 5 bits of the third group of the parity check bit register, and so on until the mother code length is reached.

[0055] Step 4: Perform an AND operation on the data stored in the parity check bit register pc_reg[1023:0] and the data stored in the mask register pc_mask[1023:0], that is, pc_mask[1023:0] ∩ pc_reg[1023:0], to obtain three parity check bit values. Among them, the positions of the three parity check bits in the data stored in the mask register pc_mask[1023:0] are 1, and the remaining positions are 0.

[0056] After the operation in Step 4, three parity check bit values can be obtained. Store these three parity check bit values in the value register pc_val[1023:0]. Finally, perform an exclusive OR operation on the input bit stream Q_N[1023:0] and the data stored in the value register pc_val[1023:0] to obtain the information bits.

[0057] It is not difficult to find that this embodiment adopts a parallel processing method, enabling the direct parallel generation of three PC bits, thereby reducing the encoding delay of PC-polar. At the same time, this embodiment also establishes a triangular interleaving address table, which can be executed in parallel according to this triangular interleaving address table during the triangular interleaving operation, thereby improving the throughput of the polar code and reducing the delay.

[0058] The second embodiment of the present invention relates to a parallel processing device for a polar code, including:

[0059] A triangular interleaving module for parallelly completing the triangular interleaving operation on the polar code using the triangular interleaving address table;

[0060] An initialization module for setting a parity check bit register with the same length as the mother code and initializing the first 5 bits of the parity check bit register to the first 5 bits of the input bit stream;

[0061] The first exclusive OR operation module is used to perform an exclusive OR operation on 5 bits of the nth group of the parity check bit register and 5 bits of the (n + 1)th group of the input bit stream, and store the obtained result in 5 bits of the (n + 1)th group of the parity check bit register;

[0062] The AND operation module is used to perform an AND operation on the data stored in the parity check bit register and the data stored in the mask register to obtain three parity check bit values. Among them, the positions of the three parity check bits in the data stored in the mask register are 1, and the remaining positions are 0;

[0063] Where n is a positive integer.

[0064] The parallel processing device of the polar code further includes:

[0065] The storage module is used to store the obtained three parity check bit values in a value register of the same length as the mother code;

[0066] The second exclusive OR operation module is used to perform an exclusive OR operation on the data stored in the value register and the input bit stream to obtain information bits.

[0067] The triangular interleaving module includes:

[0068] The length calculation unit is used to calculate the length of the triangular interleaver used in the triangular interleaving operation according to the rate matching length;

[0069] The address table determination unit is used to determine the triangular interleaving address table according to the length of the triangular interleaver;

[0070] The interleaving operation unit is used to perform a triangular interleaving operation on the polar code and execute it in parallel according to the triangular interleaving address table during the triangular interleaving operation.

[0071] The length calculation unit calculates the length of the triangular interleaver, where T is the length of the triangular interleaver and E is the rate matching length.

[0072] The address table determination unit includes:

[0073] The address calculation sub-unit is used to calculate the triangular interleaving address according to the length of the triangular interleaver. The triangular interleaving address is expressed as: address(i, j) = iT + j - i*(i - 1) / 2;

[0074] The storage sub-unit is used to store the triangular interleaving address column by column in the triangular interleaving address table when i + j < T and address(i, j) < E;

[0075] Among them, address(i,j) is the triangular interleaving address, i is the row index, j is the column index, both i and j are natural numbers, T is the length of the triangular interleaver, and E is the rate matching length.

[0076] The third embodiment of the present invention relates to an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, the steps of the parallel processing method of the polarization code in the first embodiment are implemented.

[0077] The fourth embodiment of the present invention relates to a computer-readable storage medium, on which a computer program is stored. The computer program, when executed by a processor, implements the steps of the parallel processing method of the polarization code in the first embodiment.

[0078] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories and optical memories, etc.) containing computer-usable program code.

[0079] The present application is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0080] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured article including an instruction method that implements the functions specified in Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0081] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so as to cause a series of operational steps to be performed on the computer or other programmable apparatus to generate a computer-implemented process, thereby providing steps for implementing the functions specified in one flow Figure 1 one process or a plurality of processes and / or boxes Figure 1 steps of the functions specified in one box or a plurality of boxes.

[0082] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, and all should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A parallel processing method for polar codes, characterized by comprising the following steps: Perform triangular interleaving operation on the polar code in parallel using a triangular interleaving address table; Set a parity check bit register with the same length as the mother code, and initialize the first 5 bits of the parity check bit register to the first 5 bits of the input bit stream; Perform an exclusive OR operation on the 5 bits of the nth group of the parity check bit register and the 5 bits of the (n + 1)th group of the input bit stream, and store the obtained result in the 5 bits of the (n + 1)th group of the parity check bit register; Perform an AND operation on the data stored in the parity check bit register and the data stored in the mask register to obtain three parity check bit values, where the positions of the three parity check bits in the data stored in the mask register are 1 and the rest are 0; Where n is a positive integer.

2. The parallel processing method for polar codes according to claim 1, characterized in that after obtaining the three parity check bit values, it further includes: Store the obtained three parity check bit values in a value register with the same length as the mother code; Perform an exclusive OR operation on the data stored in the value register and the input bit stream to obtain information bits.

3. The parallel processing method for polar codes according to claim 1, characterized in that the step of performing triangular interleaving operation on the polar code in parallel using a triangular interleaving address table specifically includes: Calculate the length of the triangular interleaver used in the triangular interleaving operation according to the rate matching length; Determine the triangular interleaving address table according to the length of the triangular interleaver; Perform triangular interleaving operation on the polar code, and execute it in parallel according to the triangular interleaving address table during the triangular interleaving operation.

4. The parallel processing method for polar codes according to claim 3, characterized in that the length of the triangular interleaver is calculated by where T is the length of the triangular interleaver and E is the rate matching length.

5. The parallel processing method for polar codes according to claim 3, characterized in that the step of determining the triangular interleaving address table according to the length of the triangular interleaver specifically includes: Calculate the triangular interleaving address according to the length of the triangular interleaver, and the triangular interleaving address is expressed as: address(i,j) = iT + j - i*(i - 1) / 2; When i + j < T and address(i,j) < E, store the triangular interleaving address column by column into the triangular interleaving address table; where address(i,j) is the triangular interleaving address, i is the row index, j is the column index, both i and j are natural numbers, T is the length of the triangular interleaver, and E is the rate matching length.

6. A parallel processing device for polar codes, comprising: A triangular interleaving module for performing triangular interleaving operations on polar codes in parallel using a triangular interleaving address table; An initialization module for setting a parity check bit register of the same length as the mother code and initializing the first 5 bits of the parity check bit register to the first 5 bits of the input bit stream; A first exclusive OR operation module for performing an exclusive OR operation on 5 bits of the n-th group of the parity check bit register and 5 bits of the (n + 1)-th group of the input bit stream, and storing the obtained result into 5 bits of the (n + 1)-th group of the parity check bit register; An AND operation module for performing an AND operation on the data stored in the parity check bit register and the data stored in the mask register to obtain three parity check bit values, where the positions of the three parity check bits in the data stored in the mask register are 1 and the remaining positions are 0; where n is a positive integer.

7. The parallel processing device for polar codes according to claim 6, further comprising: A storage module for storing the obtained three parity check bit values into a value register of the same length as the mother code; A second exclusive OR operation module for performing an exclusive OR operation on the data stored in the value register and the input bit stream to obtain information bits.

8. The parallel processing device for polar codes according to claim 6, wherein the triangular interleaving module comprises: a length calculation unit for calculating the length of the triangular interleaver used in the triangular interleaving operation according to the rate matching length; An address table determination unit for determining the triangular interleaving address table according to the length of the triangular interleaver; An interleaving operation unit for performing triangular interleaving operations on the polar codes and executing in parallel according to the triangular interleaving address table during the triangular interleaving operation.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein when the processor executes the computer program, the steps of the parallel processing method for polar codes as described in any one of claims 1 - 5 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that when the computer program is executed by a processor, the steps of the parallel processing method of the polar code as described in any one of claims 1-5 are implemented.

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