Ferroelectric capacitor, preparation method thereof and ferroelectric random access memory
By optimizing the interface quality and crystal structure of ferroelectric capacitors, the durability and storage window limitation of FeRAM are solved, the performance and stability of ferroelectric capacitors are improved, and the integration needs of low thermal budgets are adapted.
Patent Information
- Application Number
- CN202510357344.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-25
- Publication Date
- 2025-07-11
AI Technical Summary
The existing ferroelectric random memory (FeRAM) has limitations in terms of durability and storage windows, affecting its performance and reliability, especially after multiple writes and erases, and the interface quality of the ferroelectric capacitor has an important impact on residual polarization and durability.
The lower plate is treated by chemical mechanical polishing to reduce surface undulations, form an oxide layer, and oxidize in an ozone atmosphere, deposit the seed layer and ferroelectric material of nano-ferroelectric microcrystals, combined with heat treatment to induce ferroelectric phase transformation, optimize interface quality and ferroelectric crystallization, and use hafnium oxide of doped elements as ferroelectric material.
It improves the residual polarization and durability of ferroelectric capacitors, enhances the stability of the storage window, improves the durability and performance of FeRAM, and adapts to the integration needs of low thermal budgets.
Smart Images
Figure CN120302648A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of microelectronics, and particularly relates to a ferroelectric capacitor, a preparation method thereof, and a ferroelectric random access memory. Background Art
[0002] The rapid development of artificial intelligence and machine learning has driven the demand for high-performance memories, especially those non-volatile memories that can provide speeds close to dynamic random access memory (DRAM). In this context, ferroelectric random access memory (FeRAM), as an emerging storage solution, has shown significant potential. FeRAM combines the non-volatility of ferroelectric materials and fast read / write capabilities, making it advantageous in many applications. Compared with traditional flash memory, FeRAM performs better in terms of speed and durability, and can achieve high-frequency read / write operations at lower power consumption. However, FeRAM still has certain limitations in terms of durability and storage window. Limited durability means that after multiple write and erase operations, its performance may degrade, resulting in storage reliability issues. In addition, the size of the storage window directly affects the stability of data storage, limiting its usability in some high-demand applications. As an important functional unit of ferroelectric random access memory (FeRAM), a ferroelectric capacitor (FeCAP) is usually a sandwich structure composed of metal-ferroelectric-metal (MFM). After rapid thermal annealing (RTP) at 400-600 °C, the ferroelectric layer forms ferroelectric phase crystallization, making the MFM exhibit ferroelectric polarization characteristics externally. During the read / write operation of the ferroelectric random access memory, it is necessary to change the relative voltage to flip the polarization direction of the ferroelectric capacitor and output a new electrical signal. In this process, the remanent polarization (2Pr) and durability of the ferroelectric capacitor are the key parameters determining the storage window and durability of FeRAM.
[0003] Therefore, comprehensively optimizing the remanent polarization (2Pr) and durability of the ferroelectric capacitor is of profound significance. Summary of the Invention
[0004] In view of this, to solve at least one technical problem in the related art and other aspects, the present disclosure provides a preparation method of a ferroelectric capacitor, including: performing chemical mechanical polishing treatment on the surface of the lower electrode plate to make the surface roughness of the lower electrode plate less than 0.3 nm, and performing oxidation treatment on the surface after chemical mechanical polishing treatment in an ozone atmosphere to form an oxide layer; depositing zirconia with nano-ferroelectric microcrystals on the surface of the oxide layer to form a first seed layer, depositing a ferroelectric material on the surface of the first seed layer, and the ferroelectric material adheres to the first seed layer to form regular ferroelectric phase crystallization to obtain a ferroelectric layer, and depositing zirconia with nano-ferroelectric microcrystals on the surface of the ferroelectric layer to form a second seed layer; depositing a metal material on the surface of the second seed layer to form an upper electrode plate, thereby obtaining a ferroelectric capacitor.
[0005] According to an embodiment of the present disclosure, the foregoing preparation method further includes: performing heat treatment on the ferroelectric capacitor to induce the crystal phase transition of the ferroelectric material to the ferroelectric phase.
[0006] According to an embodiment of the present disclosure, in the heat treatment, the heat treatment temperature is 200 - 400 °C, and the heat treatment time is 30 - 120 s.
[0007] According to an embodiment of the present disclosure, the foregoing preparation method further includes: performing photolithography and etching on the upper electrode plate in sequence to obtain the upper electrode plate with a target pattern.
[0008] According to an embodiment of the present disclosure, the deposition methods of the first seed layer, the second seed layer, and the ferroelectric layer are atomic layer deposition.
[0009] According to an embodiment of the present disclosure, in the oxidation treatment, the flow rate of ozone is 200 - 300 sccm, and the oxidation time is 5 - 20 min.
[0010] According to an embodiment of the present disclosure, the ferroelectric material is hafnium oxide with a doping element, and the doping element includes any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.
[0011] In another aspect of the present disclosure, a ferroelectric capacitor is further proposed, including a ferroelectric layer, a first seed layer, a second seed layer, an oxide layer, a lower electrode plate, and an upper electrode plate. Among them, the ferroelectric layer is applicable to use the change of polarization charge as stored information, and the polarization charge is affected by an externally applied voltage signal. The first seed layer and the second seed layer are respectively disposed on both sides of the ferroelectric layer, and the first seed layer and the second seed layer are applicable to provide a crystallization basis for the ferroelectric phase; the oxide layer is disposed on the surface of the first seed layer opposite to the ferroelectric layer, and is applicable to inhibit the formation of oxygen vacancies; the lower electrode plate is disposed on the lower surface of the oxide layer, and the surface roughness of the lower electrode plate is less than 0.3 nm; the upper electrode plate is disposed on the upper surface of the second seed layer.
[0012] According to an embodiment of the present disclosure, the thickness of the oxide layer is 0.5 - 1 nm; the thickness of the first seed layer is 0.5 - 1 nm; the thickness of the second seed layer is 0.5 - 1 nm; the thickness of the first seed layer is the same as that of the second seed layer.
[0013] In another aspect of the present disclosure, a ferroelectric random access memory is further proposed, wherein the functional unit of the ferroelectric random access memory includes the foregoing ferroelectric capacitor.
[0014] According to an embodiment of the present disclosure, the present disclosure proposes to planarize the flatness of the lower electrode plate by Chemical Mechanical Polishing (CMP) to reduce the peak electric field, thereby alleviating the generation of oxygen vacancies during the high-field cycling process. At the same time, the present disclosure also performs an oxidation treatment on the lower electrode plate to form an oxide layer, which on the one hand alleviates the lattice matching between the lower electrode plate and the ferroelectric layer, and on the other hand passivates the interface to prevent the lower electrode plate from absorbing oxygen in the ferroelectric layer and forming oxygen vacancy defects. Further, using the seed layer as the crystallization basis of the ferroelectric material can enable the ferroelectric material to grow in a form similar to epitaxy and form small-scale ferroelectric crystallization, thereby reducing the thermal budget of ferroelectric activation, reducing the aggregation of oxygen vacancies in the ferroelectric layer body, and adapting to the integration requirements of the low thermal budget in the back end. Description of the Drawings
[0015] Figure 1 is a cross-sectional schematic diagram of a ferroelectric capacitor according to an embodiment of the present disclosure;
[0016] Figure 2 is a cross-sectional schematic diagram of a ferroelectric random access memory according to another embodiment of the present disclosure;
[0017] Figure 3 is a cross-sectional schematic diagram of depositing the lower electrode plate in Embodiment 1 of the present disclosure;
[0018] Figure 4 is in Embodiment 1 of the present disclosure Figure 3 is a cross-sectional schematic diagram of the lower electrode plate after planarization on the basis of;
[0019] Figure 5 is in Embodiment 1 of the present disclosure Figure 4 is a cross-sectional schematic diagram of the oxidation treatment on the basis of;
[0020] Figure 6 is in Embodiment 1 of the present disclosure Figure 5 is a cross-sectional schematic diagram after depositing the second seed layer on the basis of;
[0021] Figure 7 is a cross-sectional schematic diagram of a ferroelectric capacitor according to Embodiment 1 of the present disclosure;
[0022] Figure 8 is a schematic diagram of the comparison of the metal material morphology before and after the CMP process treatment in Embodiment 1 of the present disclosure;
[0023] Figure 9 is a graph of the relationship between the remanent polarization and voltage of the ferroelectric capacitor in Embodiment 1 of the present disclosure;
[0024] Figure 10 is a durability cycle test diagram of the ferroelectric capacitor in Embodiment 1 of the present disclosure;
[0025] Figure 11It is a simulation diagram of the electric field distribution of the ferroelectric layer before and after chemical mechanical polishing in the embodiments of the present disclosure;
[0026] Figure 12 It is a schematic cross-sectional view of the select transistor in Embodiment 2 of the present disclosure;
[0027] Figure 13 It is in Embodiment 2 of the present disclosure Figure 12 Schematic cross-sectional view of depositing the lower electrode plate on the basis of;
[0028] Figure 14 It is in Embodiment 2 of the present disclosure Figure 13 Schematic cross-sectional view after the lower electrode plate is planarized on the basis of;
[0029] Figure 15 It is in Embodiment 2 of the present disclosure Figure 14 Schematic cross-sectional view of the oxidation treatment on the basis of;
[0030] Figure 16 It is in Embodiment 2 of the present disclosure Figure 15 Schematic cross-sectional view after depositing the second seed layer on the basis of;
[0031] Figure 17 It is in Embodiment 2 of the present disclosure Figure 16 Schematic cross-sectional view of preparing the ferroelectric capacitor on the basis of;
[0032] Figure 18 It is in Embodiment 2 of the present disclosure Figure 17 Schematic cross-sectional view of filling the isolation material and exposing the via on the basis of;
[0033] Figure 19 It is a schematic cross-sectional view of the ferroelectric random access memory in Embodiment 2 of the present disclosure.
[0034] In the accompanying drawings of the present disclosure specification, the meanings of the reference numerals are:
[0035] 1 - lower electrode plate; 11 - silicon wafer; 12 - tungsten; 2 - oxide layer; 3 - seed layer; 31 - first seed layer; 32 - second seed layer; 4 - ferroelectric layer; 5 - upper electrode plate; 6 - select transistor; 7 - SiO2 isolation layer; 8 - via; 9 - wiring metal layer. Detailed implementation manners
[0036] To make the objectives, technical solutions and advantages of the present disclosure clearer and more understandable, the present disclosure will be further described in detail below with reference to specific embodiments and the accompanying drawings.
[0037] In the present disclosure, the endpoints and any values of the disclosed ranges are not limited to the exact ranges or values. These ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the values between the endpoint values of each range, between the endpoint values and individual point values of each range, and between individual point values can be combined with each other to obtain one or more new numerical ranges, and these numerical ranges should be considered to be specifically disclosed in the present disclosure.
[0038] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0039] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those of ordinary skill in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted to have a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0040] Throughout the drawings, the same elements are denoted by the same or similar reference numerals. When it may cause confusion in the understanding of the present disclosure, conventional structures or configurations will be omitted. Also, the shapes, sizes, and positional relationships of the components in the drawings do not reflect the actual sizes, proportions, and actual positional relationships. Additionally, in the present disclosure, any reference signs located between parentheses should not be construed as limiting the present disclosure.
[0041] Similarly, in order to streamline the present disclosure and assist in understanding one or more of the various disclosed aspects, in the above description of the exemplary embodiments of the present disclosure, the various features of the present disclosure are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.
[0042] In addition, the technical solutions between various embodiments can be combined with each other, but it must be based on the ability of those of ordinary skill in the art to implement. When the combination of technical solutions results in contradictions or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present disclosure.
[0043] In the process of implementing the present disclosure, it is found that the interface quality is the main factor affecting the remanent polarization and durability of FeCAP. For example, problems such as the interfacial peak electric field caused by an uneven interface, inconsistent ferroelectric crystal axis arrangement, defects caused by oxygen diffusion at the interface, and thermal damage. Therefore, the present disclosure improves the remanent polarization and durability of ferroelectric capacitors by optimizing the interface quality of the electrode plate and designing a passivating oxide interface layer.
[0044] The present disclosure provides a method for preparing a ferroelectric capacitor, including: performing chemical mechanical polishing treatment on the surface of the lower electrode plate 1 to make the surface roughness of the lower electrode plate 1 less than 0.3 nm, and performing oxidation treatment on the surface after chemical mechanical polishing in an ozone atmosphere to form an oxide layer 2; depositing zirconia with nano-ferroelectric microcrystals on the surface of the oxide layer 2 to form a first seed layer 31, depositing a ferroelectric material on the surface of the first seed layer 31, and the ferroelectric material adheres to the first seed layer 31 to form regular ferroelectric phase crystallization to obtain a ferroelectric layer 4, depositing zirconia with nano-ferroelectric microcrystals on the surface of the ferroelectric layer 4 to form a second seed layer 32; depositing a metal material on the surface of the second seed layer 32 to form an upper electrode plate 5, thereby obtaining a ferroelectric capacitor.
[0045] According to an embodiment of the present disclosure, the present disclosure proposes to level the flatness of the lower electrode plate 1 through chemical mechanical polishing (CMP) to reduce the peak electric field, thereby alleviating the generation of oxygen vacancies during the high-field cycling process. At the same time, the present disclosure also performs oxidation treatment on the lower electrode plate 1 to form an oxide layer 2. On the one hand, it alleviates the lattice matching between the lower electrode plate 1 and the ferroelectric layer 4, and on the other hand, it also passivates the interface to prevent the lower electrode plate 1 from absorbing oxygen in the ferroelectric layer 4 to form oxygen vacancy defects. Further, using the seed layer as the crystallization basis of the ferroelectric material can enable the ferroelectric material to grow in a form similar to epitaxy and form small-scale ferroelectric crystallization, thereby reducing the thermal budget for ferroelectric activation, reducing the aggregation of oxygen vacancies in the ferroelectric layer 4, and adapting to the integration requirements of the backend low thermal budget.
[0046] According to an embodiment of the present disclosure, the flatness optimization of the interface is also beneficial for depositing a thinner ferroelectric material film. On the other hand, the flat interface enables the ferroelectric domains of the ferroelectric film to crystallize in the same direction and the crystal axes to be consistent, which can improve the remanent polarization.
[0047] According to an embodiment of the present disclosure, the foregoing preparation method further includes: performing heat treatment on the ferroelectric capacitor to induce the crystal phase of the ferroelectric material to transform into the ferroelectric phase.
[0048] According to an embodiment of the present disclosure, the present disclosure can further activate the ferroelectric phase of the ferroelectric layer 4 through heat treatment. At the same time, due to the presence of the seed layer 3, the thermal budget is reduced, thereby adapting to the backend integration process, alleviating the thermal damage of the ferroelectric layer 4, and reducing the concentration of oxygen vacancies in the body.
[0049] According to an embodiment of the present disclosure, in the heat treatment, the heat treatment temperature is 200 - 400 °C, for example, it can be 200 °C, 250 °C, 300 °C, 350 °C, 400 °C, etc.; the heat treatment time is 30 - 120 s, for example, it can be 30 s, 40 s, 50 s, 60 s, 70 s, 80 s, 90 s, 100 s, 110 s, 120 s, etc.
[0050] According to an embodiment of the present disclosure, the foregoing preparation method further includes: performing photolithography and etching on the upper electrode plate 5 in sequence to obtain the upper electrode plate 5 with a target pattern.
[0051] According to an embodiment of the present disclosure, the deposition methods of the first seed layer 31, the second seed layer 32, and the ferroelectric layer 4 are atomic layer deposition.
[0052] According to an embodiment of the present disclosure, a ZrO2 seed layer with a nano-ferroelectric microcrystalline phase is obtained by atomic layer deposition. Further, in the stage of ALD depositing a ferroelectric material, the ferroelectric material can form small-scale ferroelectric crystallization similar to epitaxy, which can reduce the thermal budget of subsequent ferroelectric activation.
[0053] According to an embodiment of the present disclosure, in the oxidation treatment, the flow rate of ozone is 200 - 300 sccm (standard cubic centimeters per minute), and the oxidation time is 5 - 20 min.
[0054] According to an embodiment of the present disclosure, the ferroelectric material is hafnium oxide with a doping element, and the doping element includes any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.
[0055] Figure 1 It is a cross-sectional schematic diagram of a ferroelectric capacitor in an embodiment of the present disclosure.
[0056] In another aspect of the present disclosure, a ferroelectric capacitor is further proposed, such as Figure 1As shown, it includes a ferroelectric layer 4, a first seed layer 31, a second seed layer 32, an oxide layer 2, a lower electrode plate 1 and an upper electrode plate 5. Among them, the ferroelectric layer 4 uses the change of polarization charge as stored information, and the polarization charge is affected by an externally applied voltage signal; the first seed layer 31 and the second seed layer 32 are respectively arranged on both sides of the ferroelectric layer 4, and the first seed layer 31 and the second seed layer 32 are suitable for providing a crystallization basis for the ferroelectric phase; the oxide layer 2 is arranged on the surface of the first seed layer 31 opposite to the ferroelectric layer 4, and is suitable for inhibiting the formation of oxygen vacancies; the lower electrode plate 1 is arranged on the lower surface of the oxide layer 2, and the surface roughness of the lower electrode plate 1 is less than 0.3 nm; the upper electrode plate 5 is arranged on the upper surface of the second seed layer 32. According to an embodiment of the present disclosure, the ferroelectric layer 4 is the core part of the capacitor, and it is suitable for representing the change of polarization charge as stored information according to the change of polarization charge caused by an externally applied voltage signal. This characteristic enables the ferroelectric capacitor to have unique advantages in storing and regulating current. The first seed layer 31 and the second seed layer 32 are respectively arranged on both sides of the ferroelectric layer 4, and they provide a crystallization basis for the ferroelectric phase. The existence of the seed layer helps the ferroelectric layer 4 to form a stable and orderly crystal structure, thereby improving the performance and stability of the ferroelectric capacitor. The oxide layer 2 is arranged on the lower surface of the first seed layer 31, and its main function is to relieve the oxygen scavenging effect of the lower electrode plate on the ferroelectric layer material, thereby inhibiting the formation of oxygen vacancies. Oxygen vacancies are common defects in ferroelectric materials, and they will affect the electrical properties and stability of the materials. By introducing the oxide layer 2, the number of oxygen vacancies can be effectively reduced, thereby improving the performance of the ferroelectric capacitor. The lower electrode plate 1 and the upper electrode plate 5 are respectively arranged at the bottom and top of the structure, and they provide electrodes for the capacitor and the stress required for ferroelectric crystallization. The surface roughness of the electrode plate has an important influence on the performance of the capacitor. In the present disclosure, the surface roughness of the lower electrode plate 1 is less than 0.3 nm, which helps to reduce the interface defects between the electrode plate and the ferroelectric layer 4 and improve the performance of the capacitor.
[0057] In some specific embodiments, the temperature of depositing the ferroelectric layer by atomic layer deposition is usually higher than the crystallization temperature of the materials of the first seed layer and the second seed layer.
[0058] According to an embodiment of the present disclosure, the thickness of the oxide layer 2 is 0.5 - 1 nm; the thickness of the first seed layer 31 is 0.5 - 1 nm; the thickness of the second seed layer 32 is 0.5 - 1 nm; the thickness of the first seed layer 31 is the same as that of the second seed layer 32.
[0059] According to an embodiment of the present disclosure, the thickness of the oxide layer 2 is 0.5 to 1 nm. This thickness range helps to effectively inhibit the formation of oxygen vacancies in the oxide layer 2 while avoiding the negative impact of an overly thick oxide layer 2 on the performance of the capacitor. For example, an overly thick oxide layer 2 may increase the series resistance of the capacitor, reduce its capacitance value, and also increase the cost. The thicknesses of both the first seed layer 31 and the second seed layer 32 are 0.5 to 1 nm. This thickness range enables the seed layer to fully play its role in providing the crystallization basis for the ferroelectric phase while avoiding the adverse effects of an overly thick seed layer on the performance of the capacitor. For example, an overly thick seed layer may increase the manufacturing cost and operating voltage of the capacitor. By precisely controlling the thickness of each layer, the overall structure of the ferroelectric capacitor becomes more compact. This helps to reduce the volume and operating voltage of the capacitor, improve its integration level and application range. For example, in small electronic devices, a compact ferroelectric capacitor can better meet the space limitations and performance requirements.
[0060] Figure 2 It is a cross-sectional schematic diagram of a ferroelectric random access memory in another embodiment of the present disclosure.
[0061] In another aspect of the present disclosure, a ferroelectric random access memory is also proposed, as Figure 2 shown, wherein the functional unit of the ferroelectric random access memory includes the aforementioned ferroelectric capacitor.
[0062] It should be noted that the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts all fall within the scope of protection of the present disclosure.
[0063] Embodiment 1
[0064] In this embodiment, a ferroelectric capacitor was completely fabricated, wherein the ferroelectric capacitor was obtained according to the aforementioned preparation method of the ferroelectric capacitor. Figures 3 to 7 They are respectively schematic diagrams of the preparation process in Embodiment 1.
[0065] Specifically:
[0066] As Figure 3 shown, the native oxide layer was removed from the silicon wafer 11, and tungsten metal 12 was deposited as the lower electrode 1.
[0067] As Figure 4 shown, back-end metal polishing was performed by CMP for 2 - 5 s to planarize the lower electrode 1. Figure 8 It is a schematic diagram comparing the morphologies of the metal materials before and after the CMP process in Embodiment 1 of the present disclosure.
[0068] As Figure 8As shown, before CMP treatment, the surface roughness Rq of the metal material was 0.384 nm. After CMP treatment, the surface roughness Rq of the metal material was 0.195. Among them, the surface roughness decreased by 49.2%.
[0069] As Figure 5 shown, in the ALD cavity, the lower electrode 1 was in-situ oxidized by ozone to form a WO3 thin film on the surface of the lower electrode 1 as the oxide layer 2.
[0070] As Figure 6 shown, ZrO2 was deposited by ALD as the first seed layer 31, and then Hf 1-x Zr x O(HZO) was deposited by ALD as the ferroelectric layer 4, and then ZrO2 was deposited by ALD as the second seed layer 32.
[0071] As Figure 7 shown, metal tungsten was deposited on the surface of the second seed layer 32 as the upper electrode 5, and patterning was performed to obtain a ferroelectric capacitor.
[0072] The ferroelectric capacitor prepared in Example 1 was subjected to performance testing.
[0073] Figure 9 is a graph showing the relationship between the remanent polarization (Pr) and voltage (V) of the ferroelectric capacitor in Example 1 of the present disclosure. Among them, the test data in Example 1 was denoted as CMP 2s; the test data of the control group without CMP treatment was denoted as W / 0. CMP.
[0074] As Figure 9 shown, the P-V relationship was measured using a 2.5V 1KHz PUND waveform. After the lower electrode was subjected to CMP treatment, the remanent polarization (2Pr) increased, and at the same time, the coercive voltage (Vc) decreased. Analyzing the reason for this change may be due to the flat lower electrode, which makes the subsequent ferroelectric domains align along a specific axis, reducing the non-axially aligned crystal axes, increasing 2Pr, and at the same time making it easier for the ferroelectric polarization to flip, reducing the coercive voltage.
[0075] Figure 10 is a durability cycle test diagram of the ferroelectric capacitor in Example 1 of the present disclosure. Among them, the test data in Example 1 was denoted as CMP 2s; the test data of the control group without CMP treatment was denoted as W / 0. CMP.
[0076] As Figure 10 shown, the ferroelectric capacitor was subjected to a cycle test under a 2.5V 1MHz square wave, and the remanent polarization was obtained using a 2.5V 1KHz PUND waveform. After the lower electrode was subjected to CMP treatment, the durability was improved. The sample without CMP treatment failed at 10 8Breakdown occurs before the first cycle. This may be due to the reduced interface roughness, which alleviates the distribution of the interfacial peak electric field and improves the durability.
[0077] Figure 11 It is a simulation diagram of the electric field distribution of the ferroelectric layer before and after chemical mechanical polishing in the embodiments of the present disclosure. As Figure 11 shown, it can be seen from the Sentaurus TCAD simulation that a peak electric field will appear at the rough hafnium zirconium oxide interface, and such an electric field will cause defects to be more likely to occur at this place during high-voltage cycling, resulting in premature hard breakdown.
[0078] Embodiment 2
[0079] In this embodiment, a ferroelectric random access memory is completely fabricated. Among them, the ferroelectric capacitor in the functional unit of the ferroelectric random access memory is obtained according to the preparation method of the aforementioned ferroelectric capacitor. Figures 12 to 19 They are partial schematic diagrams of the preparation process in Embodiment 2 respectively.
[0080] As Figure 12 shown, the select transistor 6 completes the front-end process and exposes the via position.
[0081] As Figure 13 shown, tungsten metal is deposited as the lower electrode 1.
[0082] As Figure 14 shown, back-end metal polishing is performed by CMP for 2 - 5 s to planarize the lower electrode 1.
[0083] As Figure 15 shown, the lower electrode 1 is in-situ oxidized by ozone in the ALD chamber to form a WO3 thin film on the surface of the lower electrode 1 as the oxide layer 2.
[0084] As Figure 16 shown, ZrO2 is deposited by ALD as the first seed layer 31, and then Hf 1-x Zr x O (HZO) is deposited by ALD as the ferroelectric layer 4, and then ZrO2 is deposited by ALD as the second seed layer 32. These three layers are sequentially integrated in the same ALD chamber.
[0085] As Figure 17 shown, tungsten metal is deposited on the surface of the second seed layer 32 as the upper electrode 5, and lithography and etching are performed to leave only the ferroelectric capacitor structure on one interconnection via.
[0086] As Figure 18 shown, an SiO2 isolation layer 7 is deposited, and the interconnection via 8 is etched; then TiN / W is filled in the via 8; and then CMP is performed to expose the via 8.
[0087] As Figure 19As shown, TiN is deposited and etched to form a wiring metal layer 9, obtaining a ferroelectric random access memory. The specific embodiments described above further elaborate on the purpose, technical solutions, and beneficial effects of the present disclosure. It should be understood that the above are only specific embodiments of the present disclosure and are not used to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included within the protection scope of the present disclosure.
Claims
1. A method for preparing a ferroelectric capacitor, characterized in that, Including: Chemically mechanically polish the surface of the lower electrode plate so that the undulation of the surface of the lower electrode plate is less than 0.3 nm. In an ozone atmosphere, oxidize the surface after the chemically mechanical polishing treatment to form an oxide layer. Deposit zirconia with nano-ferroelectric microcrystals on the surface of the oxide layer to form a first seed layer. Deposit a ferroelectric material on the surface of the first seed layer. The ferroelectric material adheres to the first seed layer to form a regular ferroelectric phase crystal to obtain a ferroelectric layer. Deposit zirconia with nano-ferroelectric microcrystals on the surface of the ferroelectric layer to form a second seed layer. Deposit a metal material on the surface of the second seed layer to form an upper electrode plate, and obtain a ferroelectric capacitor.
2. The preparation method according to claim 1 further comprises: Perform heat treatment on the ferroelectric capacitor to induce the crystal phase transformation of the ferroelectric material into a ferroelectric phase.
3. The preparation method according to claim 2, wherein In the heat treatment, the heat treatment temperature is 200 - 400 °C, and the heat treatment time is 30 - 120 s.
4. The preparation method according to claim 1 further comprises: Perform photolithography and etching on the upper electrode plate in sequence to obtain an upper electrode plate with a target pattern.
5. The preparation method according to claim 1, wherein, The deposition methods of the first seed layer, the second seed layer, and the ferroelectric layer are atomic layer deposition.
6. According to the preparation method described in claim 1, in the oxidation treatment, the ozone flow rate is 200 - 300 sccm, and the oxidation time is 5 - 20 min.
7. The preparation method according to claim 1, wherein, The ferroelectric material is hafnium oxide with doping elements, and the doping elements include any one or more of silicon, aluminum, zirconium, yttrium, cadmium, lanthanum, and strontium.
8. A ferroelectric capacitor, characterized in that, The ferroelectric capacitor includes: A ferroelectric layer that uses the change of polarization charge to store information, and the polarization charge is affected by an external voltage signal. A first seed layer and a second seed layer, which are respectively arranged on both sides of the ferroelectric layer. The first seed layer and the second seed layer are suitable for providing a crystallization basis for the ferroelectric phase. An oxide layer, which is arranged on the surface of the first seed layer and the lower electrode plate after the chemically mechanical polishing treatment, and is suitable for suppressing the formation of oxygen vacancies. A lower electrode plate, which is arranged on the lower surface of the oxide layer, and the undulation of the surface of the lower electrode plate is less than 0.3 nm. An upper electrode plate, which is arranged on the upper surface of the second seed layer.
9. According to the ferroelectric capacitor described in claim 8, wherein The thickness of the oxide layer is 0.5 - 1 nm. The thickness of the first seed layer is 0.5 - 1 nm. The thickness of the second seed layer is 0.5 - 1 nm. The thickness of the first seed layer is the same as that of the second seed layer.
10. A ferroelectric random access memory, characterized in that, The functional unit of the ferroelectric random access memory includes the ferroelectric capacitor described in claim 8 or 9.