Method for realizing metal interconnection through three-dimensional TSV-MIM process

Abstract

The invention discloses a method for achieving metal interconnection through a three-dimensional TSV-MIM technology. The method comprises the following steps of: forming a TSV (Through Silicon Via) on a silicon substrate on which an MIM (Metal Injection Molding) capacitor structure is formed, filling metal, and keeping a distance between the TSV and the MIM capacitor structure; forming a groove on the MIM capacitor structure and filling metal to lead out the MIM capacitor structure; and the TSV and the MIM capacitor structure are connected and conducted out through a metal interconnection mode of bulk copper, and metal interconnection of the rewiring layer is completed. Stress generated by copper in the TSV is effectively restrained, and the problem of copper cracking and layering is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for realizing metal interconnection by a three-dimensional TSV-MIM process. Background Art

[0002] Advanced packaging technologies dominated by the Through-Silicon Via (TSV) process play an increasingly important role in the manufacturing process of three-dimensional integrated circuits. Conventional TSV holes generally achieve metal interconnection through metal pads or micro-bump technologies. In the hybrid wafer bonding process, higher-density metal interconnection can be achieved through Cu-Cu bonding.

[0003] Currently, the mainstream manufacturing process mainly adopted by TSMC generally uses arrayed TSV holes to connect TSV holes and the Redistribution Layer (RDL), as Figure 1 shown. However, there is an obvious problem with this process, that is, there is a large stress mismatch between the copper in the TSV hole and the silicon nitride film above. In the subsequent annealing process, copper swelling is very likely to occur, squeezing the silicon nitride to form cracks, resulting in copper precipitation, and further leading to abnormal connection.

[0004] The coefficient of thermal expansion (CTE) of copper is 17 ppm / °C, which is much higher than that of silicon (2.6 ppm / °C) and silicon oxide (0.5 ppm / °C). During high-temperature process treatment, temperature changes will cause insufficient adhesion between copper and the dielectric layer, resulting in delamination, and seriously leading to device failure. Summary of the Invention

[0005] The present invention discloses a method for realizing metal interconnection by a three-dimensional TSV-MIM process, including the following steps: forming TSV vias on a silicon substrate with a MIM capacitor structure formed thereon and filling the vias with metal, maintaining a spacing from the MIM capacitor structure; forming trenches on the MIM capacitor structure and filling them with metal to lead out the MIM capacitor structure; connecting and conducting the TSV and the MIM capacitor structure through a large-piece copper metal interconnection method to complete the metal interconnection of the redistribution layer.

[0006] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the step of forming TSV vias includes forming a first silicon nitride film / second silicon oxide film dielectric layer on the silicon substrate with the MIM capacitor structure formed thereon; performing photolithography and etching to form TSV vias.

[0007] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, after forming TSV vias on the silicon substrate with the MIM capacitor structure formed thereon and filling the vias with metal, the following steps are further included: adopting a wafer edge etching process to remove metal residues at the wafer edge.

[0008] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the step of forming a trench on the MIM capacitor structure specifically includes: growing a second silicon nitride film, then spin-coating an anti-reflection layer and a photoresist for opening the MIM capacitor structure; etching a trench above the MIM capacitor structure with the photoresist as a masking layer, stopping the etching in the second silicon oxide film, and then removing the anti-reflection layer and the photoresist by an ashing process; etching the remaining second silicon oxide film, stopping the etching on the first silicon nitride film, and simultaneously retaining a part of the second silicon nitride film; etching to open the first silicon nitride film, and simultaneously etching away the second silicon nitride film to open the MIM capacitor structure.

[0009] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the etching amount of the second silicon oxide film is half of the total thickness.

[0010] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the thickness of the retained part of the second silicon nitride film is 50 nm.

[0011] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the LRM etching process is used to open the first silicon nitride film, and the bias power is 100 W to 200 W.

[0012] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, after forming a trench on the MIM capacitor structure and filling it with metal, the following steps are further included: using a wafer edge etching process to remove metal residues at the wafer edge.

[0013] In the method for realizing metal interconnection by the three-dimensional TSV-MIM process of the present invention, preferably, the depth of the through-silicon via is 100 - 150 μm, and the diameter is 10 - 15 μm.

[0014] Beneficial effects:

[0015] The improved structure avoids the contact between the TSV copper hole and the silicon nitride dielectric layer, and adopts the copper-copper ohmic contact method to avoid the problem of copper stress swelling out of the TSV.

[0016] The large block of copper in the redistribution layer can effectively suppress the stress problem generated by the copper of the TSV, and solve the problem of copper cracking and delamination. Description of the drawings

[0017] Figure 1 It is a schematic diagram of copper delamination caused by the existing manufacturing process that uses arrayed TSV holes to realize the connection between the TSV holes and the redistribution layer.

[0018] Figure 2 It is a flowchart of the method for realizing metal interconnection by the three-dimensional TSV-MIM process.

[0019] Figures 3 to 10 It is a schematic structural diagram of each stage of a method for realizing metal interconnection by a three-dimensional TSV-MIM process. Specific embodiments

[0020] In order to make the objectives, technical solutions and advantages of the present invention clearer and more understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. The described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts fall within the protection scope of the present invention.

[0021] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0022] In addition, many specific details of the present invention are described below, such as the structure, material, size, processing technology and technique of the device, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details. Unless specifically pointed out below, each part of the device can be made of materials well known to those skilled in the art, or materials with similar functions developed in the future can be used.

[0023] The present invention provides a method for realizing metal interconnection by a three-dimensional TSV-MIM process. By optimizing the process structure design, the local density of copper is adjusted to control the influence of the stress and thermal expansion of copper on the dielectric layer, thereby completely solving the problem of copper delamination and cracking in the TSV process. The following will be combined with Figure 2 , and a detailed description of the method for realizing metal interconnection by a three-dimensional TSV-MIM process will be given.

[0024] Step S1, form a MIM capacitor structure 200 on a silicon substrate 100, form a first silicon oxide thin film 101 on the MIM capacitor structure 200, and form a contact post 201, such as tungsten. Form a first silicon nitride thin film 102 / second silicon oxide thin film 103 dielectric layer, and prepare a through-silicon via (TSV) structure by using the bosch process and plasma etching method. The TSV structure is spaced from the MIM capacitor structure 200. The depth of this structure is about 100 - 150 μm, and the CD diameter is about 10 - 15 μm. The obtained structure is as shown in Figure 3 shown.

[0025] Step S2, fill a TaN buffer layer / Cu 104 inside the TSV through-silicon via, and perform copper planarization by using the CMP process. The obtained structure is as shown in Figure 4 shown.

[0026] Step S3, use the bevel etching process to etch away the metal residues on the wafer edge to avoid arcing caused by the metal residues on the wafer edge in the subsequent processes, resulting in wafer scrapping.

[0027] Step S4, grow a 100-nm-thick second silicon nitride thin film 105 by using the chemical vapor deposition (CVD) process, and then spin-coat an anti-reflection layer / photoresist 106 for opening the MIM capacitor structure 200. The obtained structure is as shown in Figure 5 shown.

[0028] Step S5, etch the trench above the MIM capacitor structure 200 through the photoresist as a masking layer, and stop the etching in the second silicon oxide thin film 103. Preferably, the etching amount of the second silicon oxide thin film 103 is half of the total thickness. Then use the ashing process to remove the anti-reflection layer / photoresist 106. The obtained structure is as shown in Figure 6 shown.

[0029] Step S6, etch the remaining second silicon oxide thin film 103 through the blank etching process, use C4F8 and C4F6 etching gases to ensure a high selectivity of silicon oxide to silicon nitride (generally, the selectivity > 5:1), stop the etching on the first silicon nitride thin film 102, and ensure that about 50 nm of the second silicon nitride thin film 105 remains. The obtained structure is as shown in Figure 7 shown.

[0030] Step S7, open the first silicon nitride thin film 102 through the LRM etching process, and at the same time etch away the second silicon nitride thin film 105 to expose the contact post 201 and open the MIM capacitor structure 200. The obtained structure is as shown in Figure 8 shown. Among them, the LRM etching process uses a low-power setting, the bias power is 100 W - 200 W, and the gas uses a combination gas of CF4 + CHF3.

[0031] Step S8, copper deposition is carried out through an electrochemical copper plating process (ECP), the trench above the MIM capacitor structure 200 is filled with copper 202, and chemical mechanical polishing (CMP) is used for planarization. Meanwhile, a bevel etching process is added to remove the metal residue on the wafer edge. The obtained structure is as Figure 9 shown.

[0032] Step S9, a third silicon nitride film 107 / a third silicon oxide film 108 is formed, and then the TSV and the metal of the MIM are simultaneously opened by the method of opening copper together. Then, the TSV and the MIM capacitor are connected and conducted through the metal interconnection of the large copper block 109 to complete the metal interconnection process of the redistribution layer (RDL). The obtained structure is as Figure 10 shown.

[0033] In the conventional process manufacturing method, the MIM capacitor connection and the TSV connection holes are manufactured separately, which is convenient for process control. There are great technical difficulties in simultaneously opening the MIM capacitor and the TSV holes. It is very difficult in the process to ensure that both sides are opened simultaneously and have the same over-etching to ensure the same large process window on both sides. The present invention patent adopts the method of combining a photoresist mask layer and a planar etching process to well control the thickness difference between the two sides, ensuring that the MIM area and the TSV area can be etched to the bottom simultaneously and have the same over-etching ratio, ensuring that the process windows on both sides are the same size.

[0034] The above is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A method for realizing metal interconnection by a three-dimensional TSV-MIM process, characterized in that: The method comprises the following steps: Form TSV vias on a silicon substrate with a MIM capacitor structure formed thereon and fill the vias with metal, keeping a spacing from the MIM capacitor structure; Form trenches on the MIM capacitor structure and fill the trenches with metal to lead out the MIM capacitor structure; Connect and conduct the TSV and the MIM capacitor structure through the metal interconnection method of bulk copper to complete the metal interconnection of the redistribution layer.

2. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 1, characterized in that: The step of forming the TSV vias includes forming a first silicon nitride thin film / second silicon oxide thin film dielectric layer on the silicon substrate with the MIM capacitor structure formed thereon; Perform photolithography and etching to form the TSV vias.

3. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 1, characterized in that: After forming the TSV vias on the silicon substrate with the MIM capacitor structure formed thereon and filling the vias with metal, the following steps are further included: adopting a wafer edge etching process to remove the metal residue at the wafer edge.

4. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 2, characterized in that: The step of forming trenches on the MIM capacitor structure specifically includes: Grow a second silicon nitride thin film, then spin-coat an anti-reflection layer and a photoresist for opening the MIM capacitor structure; Etch the trenches above the MIM capacitor structure with the photoresist as a masking layer, stop etching in the second silicon oxide thin film, and then adopt an ashing process to remove the anti-reflection layer and the photoresist; Etch the remaining second silicon oxide thin film, stop etching on the first silicon nitride thin film, and at the same time retain a part of the second silicon nitride thin film; Etch to open the first silicon nitride thin film, and at the same time etch away the second silicon nitride thin film to open the MIM capacitor structure.

5. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 4, characterized in that: The etching amount of the second silicon oxide thin film is half of the total thickness.

6. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 4, characterized in that: The thickness of the retained part of the second silicon nitride thin film is 50 nm.

7. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 4, characterized in that Adopt the LRM etching process to open the first silicon nitride thin film, and the bias power is 100 W to 200 W.

8. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 1, characterized in that: After forming trenches on the MIM capacitor structure and filling the trenches with metal, the following steps are further included: adopting a wafer edge etching process to remove the metal residue at the wafer edge.

9. The method for realizing metal interconnection by a three-dimensional TSV-MIM process according to claim 1, characterized in that: The depth of the silicon through hole is 100 - 150 μm, and the diameter is 10 - 15 μm.

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