Heterojunction bipolar transistor device

Abstract

The invention provides a heterojunction bipolar transistor device. The heterojunction bipolar transistor device comprises a substrate, a metal secondary collector layer, a collector layer, a base layer, an emitter layer, a base electrode and a plurality of emitter strips, a metal secondary collector layer is formed over the substrate. A collector layer is formed over the metal secondary collector layer. A base layer is formed over the collector layer. An emitter layer is formed over the base layer. The base electrode is formed over the base layer and includes a plurality of base fingers. A plurality of emitter strips are formed over the emitter layer and alternately arranged with the plurality of base fingers.

Description

Technical Field

[0001] Some embodiments of the present application relate to semiconductor technology, particularly to heterojunction bipolar transistor devices. Background Art

[0002] The semiconductor industry has experienced exponential growth. Technological advancements in semiconductor design have resulted in several generations of semiconductor devices (e.g., transistors), each of which can operate more efficiently than the previous generation. This advancement generally provides some benefits by increasing production efficiency and reducing related costs. To achieve these advancements, developments in semiconductor design and manufacturing are required.

[0003] However, while existing semiconductor devices generally meet the requirements, they are not satisfactory in every aspect. For example, in a heterojunction bipolar transistor device, multiple unit cells can be connected in parallel to fabricate a power cell. However, this increases the required area. Therefore, there is a need to further improve the heterojunction bipolar transistor device. Summary of the Invention

[0004] A heterojunction bipolar transistor device is provided. An exemplary embodiment of the heterojunction bipolar transistor device includes a substrate, a metal subcollector layer, a collector layer, a base layer, an emitter layer, a base electrode, and a plurality of emitter bars. The metal subcollector layer is formed over the substrate. The collector layer is formed over the metal subcollector layer. The base layer is formed over the collector layer. The emitter layer is formed over the base layer. The base electrode is formed over the base layer and includes a plurality of base fingers. The plurality of emitter bars are formed over the emitter layer and are alternately arranged with the plurality of base fingers.

[0005] Another embodiment of the heterojunction bipolar transistor device includes a substrate, a collector mesa, a base mesa, a plurality of emitter mesas, and a base electrode. The collector mesa is formed on the substrate and includes a metal subcollector layer. The base mesa is formed on the collector mesa. The plurality of emitter mesas are formed on the base mesa. The base electrode is formed on the base mesa and includes a plurality of base fingers that are alternately arranged with the plurality of emitter mesas. Brief Description of the Drawings

[0006] The present application can be more fully understood by reading the following detailed description and examples with reference to the accompanying drawings, in which:

[0007] Figure 1 is a cross-sectional view of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application;

[0008] Figures 2A to 2G is a cross-sectional view of various manufacturing stages of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application;

[0009] Figure 3 is a top view of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application;

[0010] Figure 4 is a top view of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application;

[0011] Figure 5 is a cross-sectional view of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application; and

[0012] Figure 6 is a top view of an exemplary heterojunction bipolar transistor device according to some embodiments of the present application.

[0013]

Description of Symbols

[0014] 10, 100, 300, 400: Heterojunction bipolar transistor device

[0015] 12, 114: Substrate

[0016] 14: Sub-collector layer

[0017] 16, 110: Collector layer

[0018] 18, 108: Base layer

[0019] 20, 106: Emitter layer

[0020] 22, 122: Base electrode

[0021] 24, 118, 118b, 118c, 128, 130, 132, 406: Metal layer

[0022] 100a: First structure

[0023] 100b: Second structure

[0024] 102: Carrier substrate

[0025] 104: Release layer

[0026] 112: First metal layer

[0027] 116: Second metal layer

[0028] 118a: Metal sub-collector layer

[0029] 119: Opening

[0030] 120: Emitter electrode

[0031] 120a: First short edge

[0032] 120b: Second short edge

[0033] 122a: Base strip

[0034] 122b: Base finger

[0035] 124: Dielectric layer

[0036] 126: Passivation layer

[0037] 134, 136: Conductive bump

[0038] 402: Back via

[0039] 404: Back metal layer

[0040] A - A’, B - B’: Line

[0041] C: Passive component

[0042] D: Distance

[0043] D1: First direction

[0044] D2: Second direction Detailed implementation manners

[0045] The following description is made to illustrate the general principles of the present application and should not be considered as a limitation. The scope of the present application is most appropriately determined by referring to the appended claims for patent.

[0046] The present application will be described with respect to specific embodiments and with reference to certain drawings, but the present application is not limited thereto and is only limited by the claims for patent. The described drawings are only schematic and not restrictive. In the drawings, the sizes of some elements may be enlarged for illustrative purposes and are not drawn to scale. These sizes and relative sizes do not correspond to the actual sizes when implementing the present application.

[0047] It should be understood that when an element (such as a layer, a region or a substrate) is referred to as "on another element" or extends "onto another element", this element can be directly on another element or directly extend onto another element, or there may also be an intermediate element. It should also be understood that when an element is referred to as "connected" or "coupled" to another element, this element can be directly connected or coupled to another element, or there may be an intermediate element.

[0048] It should be understood that although terms such as "first", "second", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section without departing from the teachings of the present application.

[0049] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should be further understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0050] The term "overlying" can be defined as at least partially overlapping when viewed from above. Multiple components of multiple embodiments can be modified or recombined to form a new combination as a new embodiment. In addition, the description of "the first element extends through the second element" can include embodiments in which the first element is disposed in the second element and extends from one side of the second element to the opposite side of the second element, where the surface of the first element can be substantially flush with the surface of the second element, or the surface of the first element can be outside the surface of the second element.

[0051] The spatially relative description of one element and another element can change as the structure is operated or used in different directions. In addition, this application may repeat reference numerals and / or letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not represent a specific relationship between the different embodiments discussed.

[0052] In describing one or more of these embodiments, this application may provide several advantages over prior art devices. In the following discussion of advantages or benefits, it should be noted that these benefits and / or results may exist in some embodiments but are not required.

[0053] A heterojunction bipolar transistor (HBT) device including a metal subcollector layer is described according to some embodiments of the present application. The heterojunction bipolar transistor device can include a plurality of emitter electrodes directly disposed above a single metal subcollector layer, such that a power cell can be achieved without increasing parasitic capacitance. In addition, emitter shunting and collector shunting can be achieved simultaneously. Additionally, the occupied area and number of collector contacts can be reduced.

[0054] Figure 1FIG. 0 is a cross-sectional view of a heterojunction bipolar transistor device 10 according to some embodiments. The heterojunction bipolar transistor device 10 may include a substrate 12, a sub-collector layer 14, a collector layer 16, a base layer 18, an emitter layer 20, a base electrode 22, and a metal layer 24. The sub-collector layer 14, the collector layer 16, the base layer 18, and the emitter layer 20 may be formed sequentially over the substrate 12. The base electrode 22 may be formed on the base layer 18 and adjacent to the emitter layer 20. The metal layer 24 may be formed on the emitter layer 20.

[0055] In some embodiments, the sub-collector layer 14 is formed of a metal such that the resistance contributed by lateral epitaxy is substantially absent, and the parasitic capacitance between the metal layer 24 and the metal of the sub-collector layer 14 will be reduced. In addition, emitter shunting can be achieved from above the heterojunction bipolar transistor device 10, while collector shunting can be achieved from below the heterojunction bipolar transistor device 10.

[0056] Figures 2A to 2G FIG. 7 is a cross-sectional view of various manufacturing stages of a heterojunction bipolar transistor (HBT) device 100 according to some embodiments of the present application. Additional components may be added to the heterojunction bipolar transistor device 100. For different embodiments, some of the components described below may be replaced or eliminated. For simplicity of illustration, only a part of the heterojunction bipolar transistor device 100 is shown.

[0057] According to some embodiments, as Figure 2A shown, a first structure 100a is provided. The first structure 100a may include a carrier substrate 102, which may be formed of a III-V compound semiconductor material, including GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, similar materials, or combinations thereof, or any suitable material. As used herein, the term "III-V semiconductor" may refer to a semiconductor compound formed between group III elements and group V elements of the periodic table, including aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), similar materials, or combinations thereof. This term may also refer to ternary and quaternary compounds, such as AlGaN, AlInGaN, or similar materials. In some embodiments, the carrier substrate 102 may be made of GaAs.

[0058] A release layer 104 can be formed on a carrier substrate 102. The release layer 104 can be formed of a material that can be selectively removed (e.g., etched or dissolved) faster than an overlying layer. In some embodiments, the release layer 104 is formed of AlAs. Then, according to some embodiments, an emitter layer 106 is formed on the release layer 104. The emitter layer 106 can be formed of a group III-V semiconductor, including GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, similar materials, or a combination of the foregoing.

[0059] The emitter layer 106 can have a first conductivity type, e.g., n-type. The formation of the emitter layer 106 can be by a deposition process, including molecular-beam epitaxy (MBE), liquid phase epitaxy (LPE), metalorganic chemical vapor deposition (MOCVD), chemical vapor deposition (CVD), hydride vapor phase epitaxy (HVPE), metal organic vapor phase epitaxy (MOVPE), similar methods, or a combination of the foregoing.

[0060] In some embodiments, the emitter layer 106 is an n-type InGaP layer. In some other embodiments, the emitter layer 106 is a multi-layer structure with different doping concentrations. For example, the emitter layer 106 can include a vertically stacked n-type InGaP layer and a heavily doped n-type GaAs layer.

[0061] Next, according to some embodiments, a base layer 108 is formed on the emitter layer 106. The base layer 108 can be formed of a group III-V semiconductor, including GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, similar materials, or a combination of the foregoing. The emitter layer 106 and the base layer 108 can be formed of different materials with different bandgaps such that a heterojunction can be formed at the interface therebetween.

[0062] The base layer 108 may have a second conductivity type different from the first conductivity type, such as p-type. The base layer 108 may be doped with C, Mg, Zn, Ca, Be, Sr, Ba, Ra, or any suitable material. In some embodiments, the base layer 108 comprises a heavily doped p-type GaAs layer. The formation of the base layer 108 may be by a deposition process, including molecular beam epitaxy, liquid phase epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, hydride vapor epitaxy, metalorganic vapor epitaxy, similar methods, or combinations of the foregoing.

[0063] Then, according to some embodiments, a collector layer 110 is formed on the base layer 108. The collector layer 110 may be formed of a group III-V semiconductor, including GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, GaSb, similar materials, or combinations of the foregoing. The collector layer 110 may have the first conductivity type, such as n-type. The formation of the collector layer 110 may be by a deposition process, including molecular beam epitaxy, liquid phase epitaxy, metalorganic chemical vapor deposition, chemical vapor deposition, hydride vapor epitaxy, metalorganic vapor epitaxy, similar methods, or combinations of the foregoing.

[0064] In some embodiments, the collector layer 110 is an n-type GaAs layer. In some other embodiments, the collector layer 110 is a multi-layer structure with different doping concentrations. For example, the collector layer 110 may comprise a vertically stacked n-type GaAs layer and a heavily doped n-type InGaAs layer.

[0065] Next, according to some embodiments, a first metal layer 112 is formed on the collector layer 110. The first metal layer 112 may be formed of gold (Au), copper (Cu), any suitable material, an alloy of the foregoing, or a combination of the foregoing. The formation of the first metal layer 112 may be by electroplating, sputtering, electron beam evaporation, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), similar methods, or combinations of the foregoing.

[0066] Then, according to some embodiments, as Figure 2B shown, a second structure 100b is provided. The second structure 100b may comprise a substrate 114. The substrate 114 may be a semiconductor substrate. The substrate 114 may be formed of a group III-V semiconductor, including GaN, AlGaN, AlN, GaAs, AlGaAs, InP, InAlAs, InGaAs, similar materials, or combinations of the foregoing. In some embodiments, the substrate 114 is formed of undoped GaAs.

[0067] Next, according to some embodiments, a second metal layer 116 is formed on the substrate 114. The second metal layer 116 can be formed of Au, Cu, any suitable material, an alloy of the foregoing, or a combination of the foregoing. The formation of the second metal layer 116 can be by electroplating, sputtering, electron beam evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, a similar method, or a combination of the foregoing.

[0068] Then, according to some embodiments, as Figure 2C shown, the first structure 100a is turned upside down and disposed above the second structure 100b. The second metal layer 116 of the second structure 100b can contact the first metal layer 112 of the first structure 100a. The second metal layer 116 and the first metal layer 112 can comprise the same material. Next, the first structure 100a can be bonded to the second structure 100b, and the second metal layer 116 and the first metal layer 112 can form a metal layer 118.

[0069] Then, according to some embodiments, as Figure 2D shown, the carrier substrate 102 and the release layer 104 are removed from the emitter layer 106. The carrier substrate 102 and the release layer 104 can be removed by etching away the release layer 104 during a lift-off process. In some embodiments, the release layer 104 is etched via a wet etchant (comprising hydrofluoric acid (HF) or any suitable etchant). The emitter layer 106 can be exposed.

[0070] Next, according to some embodiments, a material for the emitter electrode 120 is formed on the emitter layer 106. The material for the emitter electrode 120 can be formed of titanium (Ti), aluminum (Al), cobalt (Co), nickel (Ni), Au, palladium (Pd), platinum (Pt), Cu, tungsten (W), a similar material, an alloy of the foregoing, or a combination of the foregoing. The material for the emitter electrode 120 can be formed by electroplating, sputtering, electron beam evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, a similar method, or a combination of the foregoing.

[0071] Then, according to some embodiments, as Figure 2EAs shown, the materials of the emitter electrode 120, the emitter layer 106, the base layer 108, and the collector layer 110 are patterned by photolithography and etching processes. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking (PEB), photoresist development, cleaning, drying (e.g., hard baking), other suitable techniques, or combinations of the foregoing. The etching process may include a dry etching process, a wet etching process, or a combination of the foregoing. For example, the dry etching process may include reactive ion etching (RIE), inductively-coupled plasma (ICP) etching, neutral beam etching (NBE), electron cyclotron resonance (ECR) etching, similar methods, or combinations of the foregoing. The wet etching process may use, for example, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or any suitable etchant.

[0072] It should be noted that Figure 2D the six emitter electrodes 120 in [[]] are for illustrative purposes only, and different numbers of emitter electrodes 120 may be formed on the base layer 108. Specifically, the power unit according to the present application should include at least five emitter electrodes 120. For example, eight emitter electrodes 120 may be formed on the base layer 108.

[0073] The sidewalls of the emitter electrode 120 may be substantially aligned with the sidewalls of the emitter layer 106. The emitter electrode 120 and the emitter layer 106 may be included in an emitter mesa. The sidewalls of the base layer 108 may be substantially aligned with the sidewalls of the collector layer 110. The collector layer 110 and the base layer 108 may be included in a base mesa.

[0074] Next, according to some embodiments, a base electrode 122 is formed on the base layer 108 and between the emitter electrodes 120. The base electrode 122 may be formed of Ti, Al, Co, Ni, Au, Pd, Pt, Cu, W, similar materials, alloys of the foregoing, or combinations of the foregoing. The formation of the base electrode 122 may be by electroplating, sputtering, electron beam evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, similar methods, or combinations of the foregoing. Then, the base electrode 122 may be patterned by photolithography and etching processes. Examples of the photolithography and etching processes may be the same or similar to those described above and will not be repeated.

[0075] Next, according to some embodiments, the metal layer 118 is patterned to form an opening 119. The opening 119 can extend through the metal layer 118 and can expose the substrate 114, such that the metal layer 118 can be divided into a metal sub-collector layer 118a and a metal layer 118b. The metal layer 118 can be patterned by photolithography and etching processes. The metal sub-collector layer 118a can be included in the collector mesa. The base electrode 122 and the emitter electrode 120 can overlap with the base layer 108, the collector layer 110, and the metal sub-collector layer 118a.

[0076] Then, according to some embodiments, as Figure 2F shown, a dielectric layer 124 is conformally formed on the metal sub-collector layer 118a, the metal layer 118b, the emitter electrode 120, the base layer 108, the base electrode 122, and the substrate 114. The dielectric layer 124 can protect the underlying layers and provide physical isolation and structural support. The dielectric layer 124 can be formed of a dielectric material including silicon nitride (S i 3N4), silicon dioxide (S i O2), silicon oxynitride (S i O x N y ), similar materials, or combinations of the foregoing. The dielectric layer 124 can be formed by a deposition process including spin coating, chemical vapor deposition, atomic layer deposition, metal-organic chemical vapor deposition, similar methods, or combinations of the foregoing.

[0077] Then, according to some embodiments, a passivation layer 126 is formed on the dielectric layer 124. The passivation layer 126 can be formed of an organic or inorganic insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), similar materials, or combinations of the foregoing. In some embodiments, the materials for the dielectric layer 124 and the passivation layer 126 can be different. The passivation layer 126 can be formed by a deposition process including spin coating, chemical vapor deposition, atomic layer deposition, metal-organic chemical vapor deposition, similar methods, or combinations of the foregoing.

[0078] Next, according to some embodiments, the passivation layer 126 is patterned to partially expose the top surface of the emitter electrode 120, the top surface of the dielectric layer 124, and the top surface of the metal sub-collector layer 118a. The passivation layer 126 can be patterned by photolithography and etching processes. Examples of the photolithography and etching processes can be the same as or similar to those described above and will not be repeated.

[0079] Then, according to some embodiments, as Figure 2GAs shown, a metal material layer is formed on the passivation layer 126, the dielectric layer 124, the emitter electrode 120, and the metal sub - collector layer 118a, and then patterned into a plurality of metal layers 128, 130, and 132. The metal material layer can be formed of Ti, Al, Co, Ni, Au, Pd, Pt, Cu, W, similar materials, alloys of the foregoing, or combinations of the foregoing. The formation of the metal material layer can be by electroplating, sputtering, electron beam evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, similar methods, or combinations of the foregoing, and it can be patterned by photolithography and etching processes. Examples of the photolithography and etching processes can be the same as or similar to those described above and will not be repeated here.

[0080] The metal layer 128 can be electrically connected to the metal sub - collector layer 118a and can thus also be referred to as the collector contact. The metal layer 130 can be electrically connected to each emitter electrode 120.

[0081] The metal layer 132, the metal layer 118b, and the dielectric layer 124 disposed therebetween can form a passive component C, such as a capacitor, without the need for additional processes. The metal layer 118b (i.e., the bottom metal layer of the passive component C) can be formed of the same material as the metal sub - collector layer 118a. The passive component C and the collector contact 128 can be disposed on opposite sides of the base layer 108, as Figure 2G shown, but the present application is not limited thereto. The position of the passive component C can be adjusted by a mask pattern.

[0082] The shortest distance D from each emitter electrode 120 to the metal sub - collector layer 118a can be substantially the same. Specifically, the distance D from one of the emitter electrodes 120 to the metal sub - collector layer 118a can be the sum of the thicknesses of the emitter layer 106, the base layer 108, and the collector layer 110.

[0083] As Figure 2G shown, a plurality of emitter electrodes 120 can be vertically disposed above the metal sub - collector layer 118a such that a power unit can be realized without increasing the parasitic capacitance (Cce) between the emitter electrode 120 and the metal sub - collector layer 118a. In addition, emitter shunting can be realized from above the heterojunction bipolar transistor device 100, while collector shunting can be realized from below the heterojunction bipolar transistor device 100.

[0084] In addition, the resistance contributed by the lateral epitaxy in the current path from the metal subcollector 118a to each emitter electrode 120 will be substantially absent. Therefore, the performance of each emitter will be substantially the same, resulting in better performance uniformity of the power cell heterojunction bipolar transistor device 100. In addition, compared with the embodiment in which multiple collector contacts are provided between multiple emitter electrodes, the heterojunction bipolar transistor device 100 according to some embodiments of the present application may include one collector contact 128 disposed on one side of the emitter electrode 120. Therefore, the occupied area and the number of the collector contacts 128 can be reduced, thereby reducing the wafer size or the die size. In addition, the metal subcollector layer 118a can also be used for PN diodes, PIN diodes, or any suitable devices.

[0085] Next, according to some embodiments, a plurality of conductive bumps 134 and 136 are formed on the metal layers 128 and 130, respectively. The conductive bumps 134 and 136 can be formed of a conductive material, including solder, Cu, Al, Au, Ni, Ag, Pd, tin (Sn), tin-lead (Sn-Pb), indium (In), similar materials, or a combination of the foregoing. The formation of the conductive bumps 134 and 136 can be achieved by electroplating, electroless plating, sputtering, printing, evaporation, chemical vapor deposition, similar methods, or a combination of the foregoing. The conductive bump 134 can be electrically connected to the metal subcollector layer 118a via the metal layer 128. The conductive bump 136 can be electrically connected to the emitter electrode 120 via the metal layer 130.

[0086] According to some embodiments, the metal layer 128 is not formed between the conductive bump 134 and the metal subcollector layer 118a. The conductive bump 134 can contact the metal subcollector layer 118a. The conductive bump 134 can extend on the sidewalls of the dielectric layer 124 and the passivation layer 126.

[0087] Figure 3 is of a Figure 2G heterojunction bipolar transistor device 100 according to some embodiments. Figure 2G is a cross-sectional view of the heterojunction bipolar transistor device 100 taken along the line A-A' shown in Figure 3 . For simplicity of the drawing, Figure 3 some components in Figure 2G are omitted. For example, the passive component C, the substrate 114, and the dielectric layer 124 are not shown in Figure 3 .

[0088] As shown in Figure 3As shown, the metal sub - collector layer 118a can extend along a first direction D1. The conductive bumps 134 and 136 can be arranged along the first direction D1. For clarity, the conductive bumps 134 and 136 are shown in dashed lines to reveal the underlying components. The emitter electrode 120 can extend in a second direction D2 and can be arranged along the first direction D1. The second direction D2 can be perpendicular to the first direction D1. The angle between the first direction D1 and the second direction D2 can be from 85 degrees to 95 degrees. Each emitter electrode 120 can have a strip shape and thus can also be referred to as an emitter strip.

[0089] The base electrode 122 can have a comb shape, which can include a plurality of base fingers 122b connected by a base strip 122a. Each base finger 122b can extend in the second direction D2, and the base strip 122a can extend in the first direction D1. The base fingers 122b can be arranged in an alternating manner with the emitter electrodes 120. The emitter electrode 120 can have a first short edge 120a surrounded by the base strip 122a and an exposed second short edge 120b. The second short edge 120b of the emitter electrode 120 can be substantially aligned with the edge of the base finger 122b.

[0090] Figure 4 is a top view of a heterojunction bipolar transistor device 300 according to some embodiments. It should be noted that the heterojunction bipolar transistor device 300 can include components that are the same as or similar to those of the Figure 3 heterojunction bipolar transistor device 100 shown, and for simplicity, these components will not be discussed in detail again. In the following embodiments, the base electrode 122 and the emitter electrode 120 are arranged in different directions.

[0091] As Figure 4 shown, the conductive bumps 134 and 136 can be arranged along the first direction D1. The emitter electrode 120 can extend in the first direction D1 and can be arranged along the second direction D2. The base electrode 122 can include a plurality of base fingers 122b connected by a base strip 122a. Each base finger 122b can extend in the first direction D1, and the base strip 122a can extend in the second direction D2. The base fingers 122b can be configured in an alternating manner with the emitter electrodes 120. The base strip 122a can be arranged closer to the conductive bump 134 than the base fingers 122b.

[0092] The emitter electrode 120 can have a first short edge 120a surrounded by the base strip 122a and an exposed second short edge 120b. The distance between the second short edge 120b of the emitter electrode 120 and the conductive bump 134 can be greater than the distance between the first short edge 120a of the emitter electrode 120 and the conductive bump 134.

[0093] Figure 5 is a cross-sectional view of a heterojunction bipolar transistor device 400 according to some embodiments. It should be noted that the heterojunction bipolar transistor device 400 may include components that are the same as or similar to those of the heterojunction bipolar transistor device 100 shown in Figure 2G , and for simplicity, these components will not be discussed in detail again. In the following embodiments, the emitter electrode is electrically connected to the backside metal layer via a backside via.

[0094] According to some embodiments, as Figure 5 shown, the metal layer 118 shown in Figure 2D is patterned into a metal sub-collector layer 118a, a metal layer 118b, and a metal layer 118c. The metal layer 118b and the metal layer 118c may be formed of the same material as the metal sub-collector layer 118a. The metal layer 118b and the metal layer 118c may be disposed on opposite sides of the metal sub-collector layer 118a. A backside via 402 may be formed in the substrate 114 by an etching process. The backside via 402 may extend through the substrate 114 and may partially expose the bottom surface of the metal layer 118c.

[0095] A backside metal layer 404 may be formed on the bottom surface of the substrate 114 and may extend along the sidewall of the backside via 402 to the metal layer 118c. The backside metal layer 404 may be connected to the metal layer 118c. The backside metal layer 404 may be formed of Ti, Al, Co, Ni, Au, Pd, Pt, Cu, W, similar materials, alloys of the foregoing, or combinations of the foregoing. The formation of the backside metal layer 404 may be by electroplating, sputtering, electron beam evaporation, physical vapor deposition, chemical vapor deposition, atomic layer deposition, similar methods, or combinations of the foregoing. In some embodiments, the backside metal layer 404 is patterned to form one or more thermal vias.

[0096] The metal material layer formed on the passivation layer 126 may be patterned into a metal layer 132 and a metal layer 406. The metal layer 406 may electrically connect the emitter electrode 120 to the metal layer 118c and may further be electrically connected to the backside metal layer 404.

[0097] Figure 6 is a top view of the heterojunction bipolar transistor device 400 according to some embodiments of Figure 5 . Figure 5 is a cross-sectional view of the heterojunction bipolar transistor device 400 taken along the line B - B' shown in Figure 6 . For simplicity of the drawing, Figure 6 some components in Figure 5 are omitted. For example, in Figure 6The passive component C, the substrate 114, the dielectric layer 124, and the backside metal layer 404 are not shown. Figure 6 The heterojunction bipolar transistor device 400 in Figure 3 may include components that are the same as or similar to those of the heterojunction bipolar transistor device 100 in

[0098] As Figure 6 shown, the metal subcollector layer 118a and the metal layer 118c may be arranged along the first direction D1. The metal layer 406 may extend in the first direction D1 and may overlap with the metal subcollector layer 118a, the metal layer 118c, and the backside via 402. However, the position of the backside via 402 is for illustrative purposes only. For example, the backside via 402 may be disposed closer to the base bar 122a between the base bar 122a and the base finger 122b.

[0099] In summary, the heterojunction bipolar transistor device according to the present application includes a metal subcollector layer and a plurality of emitter electrodes that vertically overlap the metal subcollector layer. As a result, better performance uniformity of the power unit heterojunction bipolar transistor can be achieved. In addition, both emitter shunting and collector shunting can be achieved. Additionally, the occupied area and the number of collector contacts can be reduced, thereby reducing the wafer size or the die size. Furthermore, one or more passive components can be formed without additional processes.

[0100] Although the present application has been described by way of examples and in terms of the preferred embodiments, it is to be understood that the application is not limited to the disclosed embodiments. On the contrary, the application is intended to cover various modifications and similar configurations (which would be apparent to those of ordinary skill in the art). Therefore, the scope of the appended claims should be given the broadest interpretation so as to cover all such modifications and similar configurations.

Claims

1. A heterojunction bipolar transistor device, characterized in that, Comprising: A substrate; A metal sub - collector layer formed above the substrate; A collector layer formed above the metal sub - collector layer; A base layer formed above the collector layer; An emitter layer formed above the base layer; A base electrode formed above the base layer and including a plurality of base fingers; And A plurality of emitter bars formed above the emitter layer and arranged alternately with the plurality of base fingers.

2. The heterojunction bipolar transistor device according to claim 1, wherein Further comprising: A single base mesa including the collector layer and the base layer, wherein the plurality of emitter bars are disposed above the single base mesa.

3. The heterojunction bipolar transistor device as described in claim 1, wherein, Further comprising: A metal layer formed above the plurality of emitter bars and electrically connected to the plurality of emitter bars.

4. The heterojunction bipolar transistor device according to claim 1, wherein Further comprising: A first conductive bump formed above the plurality of emitter bars and electrically connected to the plurality of emitter bars.

5. The heterojunction bipolar transistor device according to claim 4, wherein Further comprising: A second conductive bump formed above the metal sub - collector layer in a region outside the collector layer and electrically connected to the metal sub - collector layer.

6. The heterojunction bipolar transistor device according to claim 5, characterized in that, Further comprising: A collector contact formed between the metal sub - collector layer and the second conductive bump.

7. The heterojunction bipolar transistor device according to claim 5, characterized in that, The plurality of emitter bars are arranged along a first direction, and the first conductive bump and the second conductive bump are arranged along a second direction different from the first direction.

8. The heterojunction bipolar transistor device according to claim 5, wherein, The plurality of emitter bars are arranged along a direction, and the first conductive bump and the second conductive bump are arranged along the direction.

9. The heterojunction bipolar transistor device according to claim 1, wherein Further comprising: A passive component formed above the substrate in a region outside the collector layer, wherein the passive component includes a bottom metal layer formed of the same material as the metal sub - collector layer.

10. The heterojunction bipolar transistor device according to claim 1, wherein, Further comprising: A dielectric layer formed above the substrate and covering the sidewalls of the collector layer, the base layer, the emitter layer, and the metal sub - collector layer.

11. The heterojunction bipolar transistor device according to claim 10, wherein, The dielectric layer also covers a sidewall and a top surface of the base electrode.

12. The heterojunction bipolar transistor device according to claim 1, wherein The plurality of emitter bars and the plurality of base fingers are arranged along the width direction of the base layer.

13. The heterojunction bipolar transistor device according to claim 1, wherein, Each of the plurality of emitter bars overlaps with the metal sub - collector layer.

14. The heterojunction bipolar transistor device according to claim 1, wherein Wherein the shortest distance from each of the plurality of emitter bars to the metal sub - collector layer is substantially the same.

15. The heterojunction bipolar transistor device according to claim 1, wherein, Further comprising: A back - side via formed in the substrate; And A back - side metal layer extending from a top surface of the substrate to a bottom surface of the substrate along the sidewall of the back - side via and connected to a metal layer formed of the same material as the metal sub - collector layer.

16. The heterojunction bipolar transistor device according to claim 15, characterized in that, Further comprising: A metal layer electrically connected to the plurality of emitter bars and vertically overlapping with the back - side via.

17. A heterojunction bipolar transistor device, characterized in that, Comprising: A substrate; A collector mesa formed on the substrate and including a metal sub - collector layer; A base mesa formed on the collector mesa; A plurality of emitter mesas formed on the base mesa; And A base electrode formed on the base mesa and including a plurality of base fingers arranged alternately with the plurality of emitter mesas.

18. The heterojunction bipolar transistor device as described in claim 17, characterized in that, Further comprising: A passive component formed above the substrate and located on one side of the base mesa, and including a bottom metal layer formed of the same material as the metal sub - collector layer.

19. The heterojunction bipolar transistor device according to claim 17, characterized in that, Further comprising: A collector contact is formed above the metal sub-collector layer and on one side of the base mesa.

20. The heterojunction bipolar transistor device according to claim 17, wherein Wherein the plurality of emitter mesas overlap the base mesa and the metal sub-collector layer.

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