High-electron-mobility transistor chip with inclined grid electrode and preparation method of high-electron-mobility transistor chip
By designing a high electron mobility transistor with a tilted gate structure, the problem of electric field peak at the voltage of the transverse gallium nitride HEMT is solved, and higher voltage withstand performance and reliability are achieved, enhancing the device's electric field distribution and driving voltage range.
Patent Information
- Application Number
- CN202510445222.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-07-11
AI Technical Summary
The existing lateral gallium nitride HEMT has an electric field peak at the gate edge when it is subjected to voltage, resulting in early failure of the device and limited voltage blocking capability. The local electric field concentration still exists using step-type field plate technology.
A high electron mobility transistor with an inclined gate is designed, and the gate is composed of a first inclined segment, a connecting segment and a second inclined segment. The inclined angle is designed as an asymmetric structure, which weakens the channel electric field concentration effect and forms an inclined field plate through physical vapor deposition.
Effectively suppress local heat production, improve the device's voltage withstand performance and long-term reliability, increase the device's gate driving voltage range, and improve the electric field distribution.
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Figure CN120302671A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and particularly to a high electron mobility transistor chip with an inclined gate and a manufacturing method thereof. Background Art
[0002] HEMT (High Electron Mobility Transistor) is a heterojunction field effect transistor, which is widely used in fields such as aerospace, communication technology, automotive electronics, and switching power supplies. In particular, it has received wide attention in high-power and high-frequency application fields. The HEMT chip is the basis for manufacturing HEMT.
[0003] In the related art, there is a lateral gallium nitride HEMT, which will have an electric field peak at the edge of the gate when bearing voltage. If the structure design is improper, it will lead to early device failure and limited voltage blocking ability. To avoid the above problems, the field plate technology is used in the design to improve the electric field distribution in the device channel, thereby reducing the electric field concentration effect of the device.
[0004] However, in the process of applying the field plate technology, a stepped field plate is usually designed. The stepped field plate has obvious vertical and horizontal contours, and there is a right angle at the connection between the vertical and horizontal contours. Therefore, local electric field concentration still occurs in the channel. Summary of the Invention
[0005] Embodiments of the present disclosure provide a high electron mobility transistor chip with an inclined gate and a manufacturing method thereof, which can weaken the electric field concentration effect in the channel, thereby suppressing local heat generation, and further improving the breakdown voltage performance and long-term reliability. The technical solutions are as follows:
[0006] On the one hand, embodiments of the present disclosure provide a high electron mobility transistor chip with an inclined gate, including an epitaxial layer, a first dielectric layer, a second dielectric layer, a source electrode, a drain electrode, and a gate electrode;
[0007] The first dielectric layer and the second dielectric layer are sequentially stacked on one side of the epitaxial layer;
[0008] The source electrode and the drain electrode are spaced apart from each other, and both the source electrode and the drain electrode penetrate through the first dielectric layer and the second dielectric layer and are in contact with the epitaxial layer;
[0009] The gate includes a first inclined segment, a connection segment, and a second inclined segment that are connected in sequence. The connection segment is flush with and in contact with a surface of the first dielectric layer facing away from the epitaxial layer. In the epitaxial growth direction, the first inclined segment inclines in the direction from the drain to the source, and the second inclined segment inclines in the direction from the source to the drain. An inclination angle of the first inclined segment is greater than an inclination angle of the second inclined segment.
[0010] In one implementation of the present disclosure, the inclination angle of the second inclined segment is not greater than 30°.
[0011] In one implementation of the present disclosure, a line connecting an end of the first inclined segment far from the connection segment and an end of the second inclined segment far from the connection segment is parallel to the connection segment.
[0012] In one implementation of the present disclosure, both the first dielectric layer and the second dielectric layer are SiN layers or SiO layers;
[0013] The thickness of the first dielectric layer is 20 - 60 nm, and the thickness of the second dielectric layer is 0.1 - 2 μm.
[0014] In one implementation of the present disclosure, the first inclined segment, the connection segment, and the second inclined segment are an integral structural member.
[0015] On the other hand, an embodiment of the present disclosure provides a method for manufacturing a high electron mobility transistor chip with an inclined gate. The manufacturing method is used to manufacture the high electron mobility transistor chip as described in the above aspect. The manufacturing method includes:
[0016] Manufacture an epitaxial layer;
[0017] Sequentially manufacture a first dielectric layer and a second dielectric layer on one surface of the epitaxial layer;
[0018] Manufacture a source and a drain such that both the source and the drain penetrate through the first dielectric layer and the second dielectric layer and are in contact with the epitaxial layer;
[0019] Manufacture a gate. The gate includes a first inclined segment, a connection segment, and a second inclined segment that are connected in sequence. The connection segment is flush with and in contact with a surface of the first dielectric layer facing away from the epitaxial layer. In the epitaxial growth direction, the first inclined segment inclines in the direction from the drain to the source, and the second inclined segment inclines in the direction from the source to the drain. An inclination angle of the first inclined segment is greater than an inclination angle of the second inclined segment.
[0020] In one implementation of the present disclosure, manufacturing the gate includes:
[0021] Perform a first etching on the second dielectric layer to obtain a first etching hole. The longitudinal cross-section of the first etching hole is an isosceles trapezoid. The upper base of the first etching hole is close to the first dielectric layer, and the lower base of the first etching hole is far from the first dielectric layer.
[0022] Perform a second etching on the edge of the second dielectric layer corresponding to the first etching hole to obtain a second etching hole. The longitudinal cross-section of the second etching hole is a trapezoid. The upper base of the second etching hole is close to the first dielectric layer, the lower base of the second etching hole is far from the first dielectric layer, and one upper base angle of the second etching hole is greater than the other upper base angle.
[0023] Deposit the gate at the second etching hole.
[0024] In one implementation of the present disclosure, performing the first etching on the second dielectric layer includes:
[0025] Prepare a first photoresist layer on the side of the second dielectric layer facing away from the first dielectric layer. The first photoresist layer has a first photoresist hole. The longitudinal cross-section of the first photoresist hole is an isosceles trapezoid. The upper base of the first photoresist hole is close to the second dielectric layer.
[0026] Etch the second dielectric layer based on the first photoresist layer to obtain the first etching hole.
[0027] Remove the excess first photoresist layer.
[0028] In one implementation of the present disclosure, performing the second etching on the edge of the second dielectric layer corresponding to the first etching hole includes:
[0029] Prepare a second photoresist layer on the side of the second dielectric layer facing away from the first dielectric layer. The second photoresist layer has a second photoresist hole. The longitudinal cross-section of the second photoresist hole is an isosceles trapezoid. The upper base of the second photoresist hole is located at the edge of the first etching hole.
[0030] Etch the second dielectric layer based on the second photoresist layer to obtain the second etching hole.
[0031] Remove the excess second photoresist layer.
[0032] In one implementation of the present disclosure, preparing the second photoresist layer on the side of the second dielectric layer facing away from the first dielectric layer includes:
[0033] The upper base length of the second photoresist hole is less than 500 nm, and the overlay error is less than 100 nm.
[0034] The beneficial effects brought by the technical solutions provided by the embodiments of the present disclosure at least include:
[0035] On one side of the epitaxial layer, a first dielectric layer and a second dielectric layer are sequentially deposited. Among them, the first dielectric layer serves as the dielectric under the gate, which is used to ensure that the gate leakage current can be maintained within a relatively low range during the operation of the device. At the same time, it can also improve the breakdown voltage of the device gate, making the range of the device gate drive voltage larger. The second dielectric layer is used to provide a foundation for the deposition of the gate. The gate includes a first inclined section, a connection section, and a second inclined section that are sequentially connected. Among them, the connection section is flush with the side of the first dielectric layer facing away from the epitaxial layer. Both the first inclined section and the second inclined section are inclined with respect to the epitaxial layer. Therefore, there are no obvious vertical and horizontal profiles in the gate, effectively weakening the channel electric field concentration effect, thereby suppressing local heat generation, and further improving the breakdown voltage performance and long-term reliability.
[0036] That is to say, by designing the gate as a three-section structure, the first inclined section and the second inclined section are inclined field plates, and the first inclined section and the second inclined section are smoothly transitioned through the connection section, so that there are no obvious vertical and horizontal profiles in the gate like in the stepped field plate, effectively weakening the channel electric field concentration effect, thereby suppressing local heat generation, and further improving the breakdown voltage performance and long-term reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0038] Figure 1 is a schematic structural diagram of a high electron mobility transistor with an inclined gate provided by an embodiment of the present disclosure;
[0039] Figure 2 is a flowchart of a preparation method of a high electron mobility transistor with an inclined gate provided by an embodiment of the present disclosure;
[0040] Figure 3 is a flowchart of another preparation method of a high electron mobility transistor with an inclined gate provided by an embodiment of the present disclosure;
[0041] Figure 4 is a schematic diagram of the preparation process provided by an embodiment of the present disclosure;
[0042] Figure 5 is a schematic diagram of the preparation process provided by an embodiment of the present disclosure;
[0043] Figure 6 is a schematic diagram of the preparation process provided by an embodiment of the present disclosure;
[0044] Figure 7 It is a schematic diagram of the preparation process provided by an embodiment of the present disclosure;
[0045] Figure 8 It is a schematic diagram of the preparation process provided by an embodiment of the present disclosure;
[0046] Figure 9 It is a schematic diagram of the preparation process provided by an embodiment of the present disclosure.
[0047] Reference numerals in the accompanying drawings:
[0048] 10. Epitaxial layer;
[0049] 20. First dielectric layer;
[0050] 30. Second dielectric layer;
[0051] 40. Source electrode;
[0052] 50. Drain electrode;
[0053] 60. Gate electrode; 610. First inclined section; 620. Connection section; 630. Second inclined section;
[0054] 710. First etching hole; 720. Second etching hole;
[0055] 810. First photoresist layer; 811. First photoresist hole; 820. Second photoresist layer; 821. Second photoresist hole;
[0056] 90. Third dielectric layer. Detailed implementation manners
[0057] To make the objectives, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.
[0058] As a representative of the third-generation semiconductor materials, GaN is an important semiconductor material that emerged after Si and GaAs materials. Due to its excellent properties such as a large bandgap, high critical field strength, high carrier saturation velocity, and high temperature and radiation resistance, it has received extensive attention.
[0059] For a GaN-based high electron mobility transistor, a conductive channel is generated by forming a two-dimensional electron gas (2DEG) with a high concentration and high mobility at the heterojunction, thereby realizing the conduction of the device. Due to its excellent properties such as high thermal conductivity, low on-resistance, and tolerance to high-frequency and high-voltage conditions, in recent years, GaN-based high electron mobility transistors have become a research hotspot in the fields of high-frequency and high-power devices and switching devices.
[0060] In the related art, there is a lateral gallium nitride HEMT, which will have an electric field peak at the gate edge when subjected to voltage. If the structure is not designed properly, it will lead to early failure of the device and limited voltage blocking capability. In order to avoid the above problems, field plate technology is used in the design to improve the electric field distribution of the device channel, thereby reducing the electric field concentration effect of the device.
[0061] However, in the process of applying field plate technology, a stepped field plate is usually designed. The stepped field plate has obvious vertical and horizontal profiles, and there is a right angle at the connection between the vertical and horizontal profiles, so local electric field concentration will still occur in the channel.
[0062] In order to solve the above technical problems, the present disclosure provides a high electron mobility transistor with a tilted gate. Figure 1 is a schematic diagram of the structure of the high electron mobility transistor, combined with Figure 1 In this embodiment, the high electron mobility transistor includes an epitaxial layer 10 , a first dielectric layer 20 , a second dielectric layer 30 , a source 40 , a drain 50 and a gate 60 .
[0063] The first dielectric layer 20 and the second dielectric layer 30 are sequentially stacked on one side of the epitaxial layer 10 , the source 40 and the drain 50 are spaced apart from each other, and both the source 40 and the drain 50 penetrate the first dielectric layer 20 and the second dielectric layer 30 and contact the epitaxial layer 10 .
[0064] The gate 60 includes a first inclined section 610, a connecting section 620, and a second inclined section 630 connected in sequence. The connecting section 620 is flush with and in contact with a side of the first dielectric layer 20 facing away from the epitaxial layer 10. In the epitaxial growth direction, the first inclined section 610 is inclined along the direction from the drain 50 to the source 40, and the second inclined section 630 is inclined along the direction from the source 40 to the drain 50. The inclination angle of the first inclined section 610 is greater than the inclination angle of the second inclined section 630.
[0065] A first dielectric layer 20 and a second dielectric layer 30 are sequentially deposited on one side of the epitaxial layer 10, wherein the first dielectric layer 20 is used as a gate dielectric to ensure that the gate 60 leakage current can be maintained within a relatively low range when the device is working, and at the same time, it can also improve the withstand voltage of the device gate 60, so that the driving voltage range of the device gate 60 becomes larger. The second dielectric layer 30 is used to provide a basis for the deposition of the gate 60. The gate 60 includes a first inclined section 610, a connecting section 620 and a second inclined section 630 connected in sequence, wherein the connecting section 620 is flush with the side of the first dielectric layer 20 facing away from the epitaxial layer 10, and the first inclined section 610 and the second inclined section 630 are both inclined to the epitaxial layer 10, so there is no obvious vertical profile and horizontal profile in the gate 60, which effectively weakens the channel electric field concentration effect, thereby suppressing local heat generation, and further improving the withstand voltage performance and long-term reliability.
[0066] That is to say, by designing the gate 60 as a three-section structure, the first inclined section 610 and the second inclined section 630 are inclined field plates, and the first inclined section 610 and the second inclined section 630 are smoothly transitioned through the connecting section 620, so that there is no obvious vertical profile and horizontal profile in the step-type field plate in the gate 60, which effectively weakens the channel electric field concentration effect, thereby suppressing local heat generation, and further improving the voltage resistance performance and long-term reliability.
[0067] In addition, since the distance between the gate 60 and the source 40 is relatively short, in the actual process, the inclination angle of the first inclined section 610 needs to be increased to avoid the gate metal being unable to cover the opening of the second dielectric layer 30 due to the angle being too small, resulting in dielectric cracks, causing the gate 60 and the source 40 to leak electricity through the cracks or even short circuit. The inclination angle of the second inclined section 630 is reduced in order to optimize the device electric field distribution and alleviate the electric field concentration effect, so the process requirements of the first inclined section 610 and the second inclined section 630 are different. Therefore, in this embodiment, the inclination angle of the first inclined section 610 is designed to be greater than the inclination angle of the second inclined section 630.
[0068] It is worth noting that the inclination angle of the first inclined section 610 refers to the acute angle between the first inclined section 610 and the connecting section 620 , and the inclination angle of the second inclined section 630 refers to the acute angle between the second inclined section 630 and the connecting section 620 .
[0069] Continue to see Figure 1 , exemplarily, the inclination angle of the second inclined section 630 is not greater than 30°.
[0070] In the above implementation, since the inclination angle of the first inclined section 610 is greater than the inclination angle of the second inclined section 630, the field plate shape of the gate 60 is asymmetric. Such a design can be more conducive to weakening the electric field concentration effect.
[0071] According to simulation data, it is better when the inclination angle of the first inclination section 610 and the inclination angle of the second inclination section 630 are in the range of 10° to 30°, which is the most effective in regulating the electric field in the device.
[0072] In this embodiment, the inclination angle of the first inclined section 610 is 45°, and the inclination angle of the second inclined section 630 is 25°. Of course, in other embodiments, the inclination angles of the first inclined section 610 and the second inclined section 630 can be designed to other values according to requirements, and the present disclosure does not limit this.
[0073] Continue to see Figure 1, in this embodiment, the connection line between one end of the first inclined section 610 far from the connection section 620 and one end of the second inclined section 630 far from the connection section 620 is parallel to the connection section 620.
[0074] In the above implementation, one end of the first inclined section 610 far from the connection section 620 and one end of the second inclined section 630 far from the connection section 620 are located on the same straight line ( Figure 1 the dotted line in the figure), and this straight line is parallel to the connection section 620. Designed in this way, it is beneficial to wire bonding in subsequent packaging operations, thereby improving the reliability of the device.
[0075] Exemplarily, the first inclined section 610, the connection section 620 and the second inclined section 630 are an integral structural member.
[0076] In this embodiment, the gate 60 is prepared by a physical vapor deposition device or an evaporation device. The integral gate 60 can be well attached to the first dielectric layer 20 and the second dielectric layer 30, and form an inclined field plate structure, effectively improving the reliability of the device.
[0077] In this embodiment, both the first dielectric layer 20 and the second dielectric layer 30 are SiN layers or SiO layers. The thickness of the first dielectric layer 20 is 20 - 60 nm, and the thickness of the second dielectric layer 30 is 0.1 - 2 μm.
[0078] In the above implementation, the materials of the first dielectric layer 20 and the second dielectric layer 30 can be the same or different. The thinner the thickness of both, the more positive the threshold voltage; the thicker the thickness of both, the more negative the threshold voltage. Designing the thickness of the first dielectric layer 20 as the above value can effectively improve the breakdown voltage of the device gate 60 and make the driving voltage range of the device gate 60 larger. Designing the thickness of the second dielectric layer 30 as the above value can provide sufficient space for the lithography process based on the second dielectric layer 30, so as to deposit the gate 60 with the required thickness.
[0079] In this embodiment, the high electron mobility transistor chip further includes a third dielectric layer 90, and the third dielectric layer 90 is a SiN layer or a SiO layer.
[0080] In the above implementation, the third dielectric layer 90 is used to protect the source electrode 40, the drain electrode 50 and the gate 60.
[0081] Figure 2 The flowchart of a preparation method for a high electron mobility transistor chip with an inclined gate provided by an embodiment of the present disclosure, in combination with Figure 2 , in this embodiment, this preparation method is used to prepare Figure 1 the high electron mobility transistor chip shown, and this preparation method includes:
[0082] Step 201: Prepare the epitaxial layer 10.
[0083] Step 202: Sequentially prepare the first dielectric layer 20 and the second dielectric layer 30 on one side of the epitaxial layer 10;
[0084] Step 203: Prepare the source electrode 40 and the drain electrode 50 such that both the source electrode 40 and the drain electrode 50 penetrate through the first dielectric layer 20 and the second dielectric layer 30 and are in contact with the epitaxial layer 10;
[0085] Step 204: Prepare the gate 60, the gate 60 includes a first inclined section 610, a connection section 620, and a second inclined section 630 that are sequentially connected. The connection section 620 is flush with and in contact with the side of the first dielectric layer 20 facing away from the epitaxial layer 10. In the epitaxial growth direction, the first inclined section 610 is inclined along the direction from the drain electrode 50 to the source electrode 40, the second inclined section 630 is inclined along the direction from the source electrode 40 to the drain electrode 50, and the inclination angle of the first inclined section 610 is greater than the inclination angle of the second inclined section 630.
[0086] Since this preparation method can prepare Figure 1 the high electron mobility transistor chip shown, the prepared high electron mobility transistor chip has Figure 1 all the beneficial effects of the high electron mobility transistor chip shown, which will not be elaborated here.
[0087] Figure 3 The flowchart of another preparation method of a high electron mobility transistor chip with an inclined gate provided by the present disclosure. In combination with Figure 3 , in this embodiment, this preparation method is used to prepare Figure 1 the high electron mobility transistor chip shown. This preparation method includes:
[0088] Step 301: Prepare the epitaxial layer 10.
[0089] In this embodiment, the epitaxial layer 10 includes a channel layer, a barrier layer, and a cap layer stacked in sequence.
[0090] Among them, the channel layer is a GaN layer, the barrier layer is an AlGaN layer, and the cap layer is a GaN layer.
[0091] In the above implementation manner, an AlGaN / GaN heterojunction is formed between the channel layer and the barrier layer.
[0092] Step 302: Prepare the first dielectric layer 20 on one side of the epitaxial layer 10.
[0093] Exemplarily, the first dielectric layer 20 is prepared on one side of the epitaxial layer 10 through a MOCVD (Metal-organic Chemical Vapor Deposition) device.
[0094] Exemplarily, the first dielectric layer 20 is a SiN layer or a SiO layer.
[0095] Step 303: Prepare a second dielectric layer 30 on a side of the first dielectric layer 20 facing away from the epitaxial layer 10.
[0096] Exemplarily, the second dielectric layer 30 is prepared on a side of the first dielectric layer 20 facing away from the epitaxial layer 10 by an LPCVD (Low Pressure Chemical Vapor Deposition) device or a PECVD (Plasma Enhanced Chemical Vaper Deposition) device.
[0097] Exemplarily, the second dielectric layer 30 is a SiN layer or a SiO layer, and the thickness of the second dielectric layer 30 is 0.1 - 2 μm.
[0098] Step 304: Prepare a source electrode 40 and a drain electrode 50 (see Figure 4 ).
[0099] In this embodiment, the source electrode 40 and the drain electrode 50 are spaced apart from each other, and both the source electrode 40 and the drain electrode 50 penetrate through the first dielectric layer 20 and the second dielectric layer 30 and are in contact with the epitaxial layer 10.
[0100] Step 305: Perform a first etching on the second dielectric layer 30 to obtain a first etching hole 710.
[0101] In this embodiment, step 305 includes the following steps:
[0102] Step 3051: Prepare a first photoresist layer 810 on a side of the second dielectric layer 30 facing away from the first dielectric layer 20 (see Figure 5 ).
[0103] The first photoresist layer 810 has a first photoresist hole 811, and the longitudinal cross-section of the first photoresist hole 811 is an isosceles trapezoid, and the upper base of the first photoresist hole 811 is close to the second dielectric layer 30.
[0104] Exemplarily, in step 3051, the following steps are performed:
[0105] First, apply a photoresist on a side of the second dielectric layer 30 facing away from the first dielectric layer 20.
[0106] Exemplarily, the thickness of the photoresist is 3 - 5 μm.
[0107] Then, dry and expose the photoresist.
[0108] Finally, develop the photoresist to obtain the first photoresist layer 810.
[0109] Exemplarily, after development, the photoresist angle of the first photoresist layer 810 is 50° - 80°.
[0110] The photoresist angle is the inclination angle of the inner wall of the first photoresist hole 811.
[0111] Step 3052: Based on the first photoresist layer 810, etch the second dielectric layer 30 to obtain the first etched hole 710 (see Figure 6 ).
[0112] The longitudinal section of the first etched hole 710 is an isosceles trapezoid, the upper base of the first etched hole 710 is close to the first dielectric layer 20, and the lower base of the first etched hole 710 is far from the first dielectric layer 20.
[0113] Exemplarily, etch the second dielectric layer 30 by ICP (Inductively Couple Plasma) technology. Since there is loss of photoresist during the etching process, a certain photoresist recession effect will be formed (the inner wall of the first photoresist hole 811 expands outwards, and the size of the first photoresist hole 811 increases. The solid arrow in the figure is the direction of photoresist recession). Through this effect, the inner wall of the etched second dielectric layer 30 can present a certain angle, that is, the first etched hole 710 is formed.
[0114] Step 3053: Remove the redundant first photoresist layer 810.
[0115] Step 306: Perform a second etch on the edge of the second dielectric layer 30 corresponding to the first etched hole 710 to obtain the second etched hole 720.
[0116] In this embodiment, step 306 includes the following steps:
[0117] Step 3061: Prepare a second photoresist layer 820 on the side of the second dielectric layer 30 facing away from the first dielectric layer 20 (see Figure 7 ).
[0118] The second photoresist layer 820 has a second photoresist hole 821. The longitudinal section of the second photoresist hole 821 is an isosceles trapezoid, and the upper base of the second photoresist hole 821 is located at the edge of the first etched hole 710.
[0119] Exemplarily, in step 3061, perform the following steps:
[0120] First, coat photoresist on the side of the first dielectric layer 20 facing away from the epitaxial layer 10 and on the side of the second dielectric layer 30 facing away from the first dielectric layer 20.
[0121] Exemplarily, the thickness of the photoresist is 3 to 5 μm.
[0122] Next, the photoresist is dried and exposed.
[0123] Finally, the photoresist is developed to obtain the second photoresist layer 820.
[0124] Exemplarily, after development, the photoresist angle of the second photoresist layer 820 is less than 60°.
[0125] Since the thickness and angle of the photoresist will significantly affect the morphology after etching, a smaller photoresist angle is required after the second exposure. The purpose is to enhance the photoresist recession effect during ICP etching and meet the morphological requirements of the inner wall angle of the smaller second etching hole 720.
[0126] Exemplarily, the upper base length of the second photoresist hole 821 is less than 500 nm, and the overlay error is less than 100 nm.
[0127] With such a design, it is beneficial to form the inclined field plate (the second inclined section 630) and avoid an excessive length of the etching platform, which affects the angle consistency of the inclined field plate.
[0128] Step 3062: Based on the second photoresist layer 820, the second dielectric layer 30 is etched to obtain the second etching hole 720 (see Figure 8 ).
[0129] The longitudinal section of the second etching hole 720 is trapezoidal. The upper base of the second etching hole 720 is close to the first dielectric layer 20, the lower base of the second etching hole 720 is far from the first dielectric layer 20, and one upper base angle a of the second etching hole 720 is greater than the other upper base angle b.
[0130] The second photoresist layer 820 has a second photoresist hole 821. The longitudinal section of the second photoresist hole 821 is an isosceles trapezoid, and the upper base of the second photoresist hole 821 is located at the edge of the first etching hole 710.
[0131] Exemplarily, the second dielectric layer 30 is etched by ICP technology. This etching is the second etching, which is different from the first etching. During the second etching, due to the morphological differences of the dielectric on both sides of the second photoresist hole 821 (at Figure 7In the figure, there is a first etching hole 710 on the left side of the second photoresist hole 821, but none on the right side. As a result, the photoresist recession effect caused by photoresist loss is asymmetric on the left and right sides. For the left side of the second photoresist hole 821, the inner sidewall of the first etching hole 710 formed by the first etching will cause the photoresist to have a larger angle when receding to the inner sidewall slope, and the recession effect will become weaker during the etching process. For the right side of the second photoresist hole 821, the photoresist of the second dielectric layer 30 will recede at a relatively faster speed due to the smaller angle, thereby etching away the exposed second dielectric layer 30. Finally, by controlling the etching time, an inclined dielectric sidewall structure, that is, the second etching hole 720, is formed.
[0132] It should be noted that the second etching hole 720 is formed on the basis of the first etching hole 710. That is to say, the second etching hole 720 includes the first etching hole and the new hole formed during the second etching, and the two together form the second etching hole 720.
[0133] Step 3063: Remove the redundant second photoresist layer 820 (see Figure 9 ).
[0134] Step 307: Deposit the gate 60 at the second etching hole 720 (see Figure 1 ).
[0135] Step 308: Prepare the third dielectric layer 90 (see Figure 1 ).
[0136] The third dielectric layer is used to protect the source electrode 40, the drain electrode 50, and the gate 60.
[0137] The third dielectric layer 90 is a SiN layer or a SiO layer.
[0138] Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of this patent application of the disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom" etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.
[0139] The above is not any form of limitation to the disclosure. Although the disclosure has been disclosed as above through embodiments, it is not intended to limit the disclosure. Any person skilled in the art, without departing from the scope of the technical solutions of the disclosure, may make some changes or modifications using the technical content disclosed above as equivalent embodiments of equivalent changes. However, as long as the content does not depart from the technical solutions of the disclosure, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the disclosure still fall within the scope of the technical solutions of the disclosure.
Claims
1. A high electron mobility transistor chip with an inclined gate, characterized in that, It includes an epitaxial layer (10), a first dielectric layer (20), a second dielectric layer (30), a source electrode (40), a drain electrode (50), and a gate electrode (60); The first dielectric layer (20) and the second dielectric layer (30) are sequentially stacked on one side of the epitaxial layer (10); The source electrode (40) and the drain electrode (50) are spaced apart from each other, and both the source electrode (40) and the drain electrode (50) penetrate through the first dielectric layer (20) and the second dielectric layer (30) and are in contact with the epitaxial layer (10); The gate electrode (60) includes a first inclined segment (610), a connection segment (620), and a second inclined segment (630) connected in sequence. The connection segment (620) is flush with and in contact with the side of the first dielectric layer (20) facing away from the epitaxial layer (10). In the epitaxial growth direction, the first inclined segment (610) is inclined along the direction from the drain electrode (50) to the source electrode (40), the second inclined segment (630) is inclined along the direction from the source electrode (40) to the drain electrode (50), and the inclination angle of the first inclined segment (610) is greater than the inclination angle of the second inclined segment (630).
2. The high electron mobility transistor chip according to claim 1, wherein The inclination angle of the second inclined segment (630) is not greater than 30°.
3. The high electron mobility transistor chip according to claim 1, characterized in that, The line connecting the end of the first inclined segment (610) far from the connection segment (620) and the end of the second inclined segment (630) far from the connection segment (620) is parallel to the connection segment (620).
4. The high electron mobility transistor chip according to claim 1, characterized in that, Both the first dielectric layer (20) and the second dielectric layer (30) are SiN layers or SiO layers; The thickness of the first dielectric layer (20) is 20 - 60 nm, and the thickness of the second dielectric layer (30) is 0.1 - 2 μm.
5. The high electron mobility transistor chip according to claim 1, wherein The first inclined segment (610), the connection segment (620), and the second inclined segment (630) are an integral structural member.
6. A method for fabricating a high electron mobility transistor chip with an inclined gate, characterized in that, The preparation method is used to prepare the high electron mobility transistor chip according to any one of claims 1 to 5, and the preparation method includes: Preparing an epitaxial layer (10); Sequentially preparing a first dielectric layer (20) and a second dielectric layer (30) on one side of the epitaxial layer (10); Preparing a source electrode (40) and a drain electrode (50) such that both the source electrode (40) and the drain electrode (50) penetrate through the first dielectric layer (20) and the second dielectric layer (30) and are in contact with the epitaxial layer (10); Preparing a gate electrode (60), the gate electrode (60) includes a first inclined segment (610), a connection segment (620), and a second inclined segment (630) connected in sequence. The connection segment (620) is flush with and in contact with the side of the first dielectric layer (20) facing away from the epitaxial layer (10). In the epitaxial growth direction, the first inclined segment (610) is inclined along the direction from the drain electrode (50) to the source electrode (40), the second inclined segment (630) is inclined along the direction from the source electrode (40) to the drain electrode (50), and the inclination angle of the first inclined segment (610) is greater than the inclination angle of the second inclined segment (630).
7. The preparation method according to claim 6, wherein, Preparing the gate electrode (60) includes: Perform a first etching on the second dielectric layer (30) to obtain a first etching hole (710). The longitudinal cross-section of the first etching hole (710) is an isosceles trapezoid. The upper base of the first etching hole (710) is close to the first dielectric layer (20), and the lower base of the first etching hole (710) is far from the first dielectric layer (20). Perform a second etching on the edge of the second dielectric layer (30) corresponding to the first etching hole (710) to obtain a second etching hole (720). The longitudinal cross-section of the second etching hole (720) is a trapezoid. The upper base of the second etching hole (720) is close to the first dielectric layer (20), and the lower base of the second etching hole (720) is far from the first dielectric layer (20). One upper base angle of the second etching hole (720) is greater than the other upper base angle. Deposit the gate (60) at the second etching hole (720).
8. The preparation method according to claim 7, wherein Performing the first etching on the second dielectric layer (30) includes: Prepare a first photoresist layer (810) on the side of the second dielectric layer (30) facing away from the first dielectric layer (20). The first photoresist layer (810) has a first photoresist hole (811). The longitudinal cross-section of the first photoresist hole (811) is an isosceles trapezoid. The upper base of the first photoresist hole (811) is close to the second dielectric layer (30). Based on the first photoresist layer (810), etch the second dielectric layer (30) to obtain the first etching hole (710). Remove the excess first photoresist layer (810).
9. The preparation method according to claim 7, characterized in that, Performing the second etching on the edge of the second dielectric layer (30) corresponding to the first etching hole (710) includes: Prepare a second photoresist layer (820) on the side of the second dielectric layer (30) facing away from the first dielectric layer (20). The second photoresist layer (820) has a second photoresist hole (821). The longitudinal cross-section of the second photoresist hole (821) is an isosceles trapezoid. The upper base of the second photoresist hole (821) is located at the edge of the first etching hole (710). Based on the second photoresist layer (820), etch the second dielectric layer (30) to obtain the second etching hole (720). Remove the excess second photoresist layer (820).
10. The preparation method according to claim 9, characterized in that, Preparing the second photoresist layer (820) on the side of the second dielectric layer (30) facing away from the first dielectric layer (20) includes: The upper base length of the second photoresist hole (821) is less than 500 nm, and the overlay error is less than 100 nm.