Junction field effect transistor device and manufacturing method thereof

Abstract

The invention provides a junction field effect transistor device and a manufacturing method thereof. The device comprises a substrate, a first deep well region, a second deep well region, a gate region, a source region, a drain region and a well region. The substrate has a first conductivity type. The first deep well region is disposed over the substrate and has a first conductivity type. The second deep well region is arranged above the first deep well region and has a second conductive type, and the second conductive type is different from the first conductive type. The first deep well region extends between the second deep well region and the substrate. The gate region, the source region and the drain region are disposed in the second deep well region. The well region is disposed in the second deep well region below the gate region and has the first conductivity type.

Description

Technical Field

[0001] This application relates to semiconductor manufacturing technology, and particularly to a junction gate field-effect transistor device and a method for manufacturing the same. Background Art

[0002] A junction gate field-effect transistor (JFET) device is a voltage-controlled device used as a voltage-variable resistor. In circuit design, this resistor can be used to control the voltage value of the subsequent circuit, amplify low-noise signals, provide gain, and other functions.

[0003] Normally, a reverse bias voltage is used to control the gate terminal. When the reverse voltage is increased to a certain level, the width of the depletion region under the gate becomes larger, the internal conductive charges are emptied, and the current is cut off. The voltage at this time is called the pinch-off voltage (Vp). However, the pinch-off voltage is affected by the structural design and thus affects the circuit design and stability. Therefore, it is necessary to continuously improve the junction gate field-effect transistor device and its manufacturing method to improve the stability of the pinch-off voltage. Summary of the Invention

[0004] According to some embodiments of the present application, a junction gate field-effect transistor device is provided. The junction gate field-effect transistor device includes a substrate, a first deep well region, a second deep well region, a gate region, a source region, a drain region, and a well region. The substrate has a first conductivity type. The first deep well region is disposed above the substrate and has the first conductivity type. The second deep well region is disposed above the first deep well region and has a second conductivity type, which is different from the first conductivity type. The first deep well region extends between the second deep well region and the substrate. The gate region, the source region, and the drain region are disposed in the second deep well region. The well region is disposed in the second deep well region under the gate region and has the first conductivity type.

[0005] According to other embodiments of the present application, a junction gate field-effect transistor device is provided. The junction gate field-effect transistor device includes a substrate, a first deep well region, a second deep well region, a gate region, a source region, and a drain region. The substrate has a first conductivity type. The first deep well region is disposed above the substrate and has the first conductivity type. The second deep well region is disposed above the first deep well region and has a second conductivity type, which is different from the first conductivity type. The first deep well region separates the second deep well region from the substrate. The gate region, the source region, and the drain region are disposed in the second deep well region. The second deep well region directly contacts the entire bottom surface of the gate region.

[0006] According to still other embodiments of the present application, a method for manufacturing a junction field effect transistor device is provided. The method for manufacturing the junction field effect transistor device includes forming a first deep well region above a substrate, where the substrate and the first deep well region have a first conductivity type; forming a second deep well region in the first deep well region, where the second deep well region has a second conductivity type, the second conductivity type is different from the first conductivity type, and the depth of the second deep well region is less than the depth of the first deep well region; and forming a gate region, a source region, and a drain region in the second deep well region, where the second deep well region has a substantially uniform concentration from below the drain region to below the gate region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the embodiments of the present application can be better understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be emphasized that, in accordance with industry standard practice, many components are not drawn to scale. In fact, for the sake of clear discussion, the dimensions of various components may be arbitrarily increased or decreased.

[0008] Figures 1A to 1D are cross-sectional views showing various stages of forming a junction field effect transistor device according to some embodiments.

[0009] Figure 2 is a cross-sectional view showing a junction field effect transistor device according to some embodiments.

[0010] Figure 3 is a cross-sectional view showing a junction field effect transistor device according to some embodiments.

[0011] Symbol Explanation

[0012] 100, 200, 300: Junction field effect transistor device

[0013] 102: Substrate

[0014] 104: First deep well region

[0015] 106: Second deep well region

[0016] 108: Isolation structure

[0017] 110, 202: Well region

[0018] 112: Gate region

[0019] 114: Source region

[0020] 116: Drain region

[0021] D: Drain terminal

[0022] D1, D2, D3, D4, D5, D6: Depth

[0023] G: Gate terminal

[0024] Gnd: Ground terminal

[0025] S: Source terminal

[0026] S1: Spacing

[0027] T1, T2: Thickness

[0028] W: Width Detailed implementation manners

[0029] The following outlines some embodiments to make it easier for those skilled in the art to which this application pertains to understand this application. However, these embodiments are merely examples and are not used to limit this application. It can be understood that those skilled in the art to which this application pertains can adjust the embodiments described below according to requirements, such as changing the process sequence and / or including more or fewer steps than those described herein, and these adjustments do not exceed the scope of this application.

[0030] In addition, other components can be added based on the embodiments described below. For example, the description of "forming a second component on a first component" may include embodiments where the first component and the second component are in direct contact, and may also include embodiments where there are other components between the first component and the second component such that the first component and the second component are not in direct contact, and the up-and-down relationship between the first component and the second component may change as the device operates or is used in different orientations. Additionally, this application may repeat reference numerals and / or letters in different embodiments, and this repetition is for simplicity and clarity and is not used to indicate the relationship between the different embodiments discussed.

[0031] The following describes a junction field effect transistor device and a method for manufacturing the same according to some embodiments of this application. According to some embodiments of this application, the part of the junction field effect transistor device that is grounded is moved from the substrate to the epitaxial layer and connected by a deep well region, thereby avoiding the influence of the substrate resistance value on the junction field effect transistor device and causing instability of the pinch-off voltage, and it is easy to modulate and control the pinch-off voltage. For example, the concentration, depth parameters, etc. of the dopant can be adjusted.

[0032] Figures 1A to 1D is a cross-sectional view showing the various stages of forming a junction field effect transistor device 100 according to some embodiments of this application. Additional components can be added to the junction field effect transistor device 100. For different embodiments, some of the components and / or steps described below can be replaced or eliminated. For simplicity of the drawing, only a part of the junction field effect transistor device 100 is shown.

[0033] Refer to Figure 1A, a substrate 102 is provided. The substrate 102 may comprise any substrate material suitable for junction field effect transistor devices. For example, the material of the substrate 102 may comprise an element or a compound, such as sapphire, aluminum nitride, aluminum gallium nitride, gallium nitride, silicon, germanium, silicon carbide, gallium arsenide, zinc oxide, indium phosphide, similar materials or combinations of the foregoing. The substrate 102 may be a bulk substrate or a composite substrate formed of different materials. The substrate 102 may comprise a semiconductor-on-insulator (SOI) substrate formed by disposing a semiconductor material on an insulating layer.

[0034] The substrate 102 may have a first conductivity type. The first conductivity type is, for example, P-type. In this text, an N-type junction field effect transistor device is taken as an example for illustration, but it should be understood that the embodiments of the present application can also be applied to P-type junction field effect transistor devices or similar devices. The substrate 102 may be doped with a P-type or N-type dopant. For example, the P-type dopant may be boron, boron difluoride (BF2), gallium or combinations of the foregoing, and the N-type dopant may be phosphorus, arsenic or combinations of the foregoing.

[0035] One or more semiconductor elements (including active elements and / or passive elements) may be pre-formed on the substrate 102. Here, for the sake of simplifying the drawings, only the flat substrate 102 is shown. In the description of the present application, the term "substrate" may include the elements formed on a semiconductor wafer and various coatings covering the semiconductor wafer.

[0036] According to some embodiments, an epitaxial layer is formed above the substrate 102, and a first deep well region 104 is formed in the epitaxial layer. The first deep well region 104 may have the same first conductivity type as the substrate 102, for example, P-type. The dopant concentration of the first deep well region 104 may be about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , for example, about 5×10 15 atoms / cm 3 .

[0037] Then, as Figure 1B shown, according to some embodiments, a second deep well region 106 is formed in the first deep well region 104. The second deep well region 106 may have a second conductivity type different from that of the first deep well region 104, for example, N-type. In some embodiments, a patterned mask layer is formed above the first deep well region 104 to cover a part of the first deep well region 104, and then an ion implantation process is performed on another exposed part of the first deep well region 104 to form the second deep well region 106.

[0038] For example, the mask layer may include a photoresist, such as a positive photoresist or a negative photoresist. In some embodiments, the mask layer may include a hard mask and may be formed of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, similar materials, or a combination of the foregoing. The mask layer may be a single-layer or multi-layer structure. The formation of the mask layer may include a deposition process, a lithography process, other suitable processes, or a combination of the foregoing. In some embodiments, the deposition process includes spin coating, chemical vapor deposition, atomic layer deposition, similar processes, or a combination of the foregoing. For example, the lithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking (PEB), development, cleaning, drying (e.g., hard baking), other suitable processes, or a combination of the foregoing.

[0039] The depth D2 of the second deep well region 106 may be less than the depth D1 of the first deep well region 104 such that the second deep well region 106 does not contact the substrate 102. Specifically, the first deep well region 104 may separate the second deep well region 106 from the substrate 102. Therefore, the resistance value of the substrate 102 can be prevented from affecting the element and causing instability of the pinch-off voltage, thereby affecting circuit design, stability, etc.

[0040] For example, the depth D2 of the second deep well region may be about 3 μm to about 4.5 μm, such as about 4 μm. The ratio of the depth D2 of the second deep well region to the depth D1 of the first deep well region 104 may be about 70% to about 90%, such as about 80%. Compared with an embodiment in which the second deep well region directly contacts the substrate, in the embodiment of the present application, the first deep well region 104 separates the second deep well region 106 from the substrate 102, causing the channel of the second deep well region 106 to become narrower. Therefore, the implantation conditions of the second deep well region 106 need to be adjusted to achieve the desired characteristics. Setting the depth D2 of the second deep well region 106 within the above range can achieve a stable pinch-off voltage while avoiding the problem that the current may become smaller due to too small a depth D2 (i.e., the channel of the junction field effect transistor becomes narrower).

[0041] The dopant concentration of the second deep well region 106 may be about 1×10 15 atoms / cm 3 to about 1×10 16 atoms / cm 3 , such as about 5×10 15 atoms / cm 3 . The desired characteristics, such as the desired current amount, pinch-off voltage, etc., can be achieved by adjusting the dopant concentration, depth D2, etc. of the second deep well region 106. The first deep well region 104 may cover one edge of the second deep well region 106.

[0042] Then, according to some embodiments, such as Figure 1CAs shown, a plurality of isolation structures 108 are formed on the top surface of the first deep well region 104 and the top surface of the second deep well region 106. One of the isolation structures 108 may be located at the interface between the first deep well region 104 and the second deep well region 106. In some embodiments, the isolation structure 108 includes a local oxidation of silicon (LOCOS) isolation structure, and a part of the isolation structure 108 is embedded in the first deep well region 104 and the second deep well region 106. In other embodiments, the isolation structure 108 includes a shallow trench isolation (STI) structure.

[0043] In some embodiments, the isolation structure 108 is made of silicon oxide, silicon nitride, silicon oxynitride, similar materials, or a combination of the foregoing. In some embodiments, the formation of the isolation structure 108 includes a thermal oxidation process, a chemical vapor deposition (CVD) process, similar processes, or a combination of the foregoing. For example, the formation of the isolation structure 108 can be achieved by etching a plurality of trenches in the substrate 102 using an etching process, and then filling the trenches with the material of the isolation structure 108 by a chemical vapor deposition process.

[0044] Then, according to some embodiments, as Figure 1D shown, a well region 110 is formed in the second deep well region 106 below the region where the gate region 112 is expected to be formed. The well region 110 may have the same first conductivity type as the first deep well region 104, for example, P-type. In some embodiments, the well region 110 is formed by forming a patterned mask layer over a part of the second deep well region 106 and then performing an ion implantation process on another exposed part of the second deep well region 106. The formation method and examples of the materials of the patterned mask layer are as described above, so they will not be elaborated here.

[0045] The dopant concentration of the well region 110 can be about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 For example, about 5×10 16 atoms / cm 3 . The depth D3 of the well region 110 can be less than the depth D2 of the second deep well region 106. For example, the depth D3 of the well region 110 can be about 3 μm to about 4 μm, for example, about 3.5 μm. The ratio of the depth D3 of the well region 110 to the depth D2 of the second deep well region can be about 75% to about 90%, for example, about 85%.

[0046] Then, according to some embodiments, a gate region 112 is formed above the well region 110. The edge of the well region 110 may generally correspond to the edge of the gate region 112. The gate region 112 may have the same first conductivity type as the well region 110, such as P-type. In some embodiments, a patterned mask layer is formed above the second deep well region 106 to cover a part of the second deep well region 106, and then another part of the exposed second deep well region 106 is subjected to an ion implantation process to form the gate region 112. Examples of the formation method and materials of the patterned mask layer are as described above, so details are not repeated here.

[0047] The dopant concentration of the gate region 112 may be greater than that of the well region 110. For example, the dopant concentration of the gate region 112 may be about 1×10 19 atoms / cm 3 to about 1×10 20 atoms / cm 3 For example, about 5×10 19 atoms / cm 3 . The depth D4 of the gate region 112 may be less than the depth D3 of the well region 110. For example, the depth D4 of the gate region 112 may be about 0.3 μm to about 0.6 μm, such as about 0.5 μm. The ratio of the depth D4 of the gate region 112 to the depth D3 of the well region 110 may be about 10% to about 20%, such as about 15%.

[0048] Then, according to some embodiments, a source region 114 and a drain region 116 are formed on the top surface of the second deep well region 106. The source region 114 and the drain region 116 may have the same second conductivity type as the second deep well region 106, such as N-type. In some embodiments, a patterned mask layer is formed above the second deep well region 106 to cover a part of the second deep well region 106, and then another part of the exposed second deep well region 106 is subjected to an ion implantation process to form the source region 114 and the drain region 116. Examples of the formation method and materials of the patterned mask layer are as described above, so details are not repeated here. The source region 114 and the drain region 116 may be formed simultaneously by a single ion implantation process. Alternatively, the source region 114 and the drain region 116 may be formed separately in different processes.

[0049] The dopant concentration of the source region 114 and the drain region 116 may be higher than that of the second deep well region 106. The source region 114 and the drain region 116 may have substantially the same dopant concentration. For example, the dopant concentration of the source region 114 and the drain region 116 may be about 1×10 20 atoms / cm 3 to about 1×10 21 atoms / cm 3 For example, about 5×10 20 atoms / cm3 。

[0050] The source region 114 and the drain region 116 may have substantially the same depth D5. The depth D5 of the source region 114 or the drain region 116 may be less than the depth D2 of the second deep well region 106. As Figure 1D shown, the depth D5 of the source region 114 or the drain region 116 may be substantially equal to the depth D4 of the gate region 112 and less than the depth D3 of the well region 110, but the present application is not limited thereto. The respective depths may be adjusted according to design requirements, for example, to achieve a desired pinch-off voltage and current, etc. For example, the depth D5 of the source region 114 or the drain region 116 may be less than the depth D4 of the gate region 112.

[0051] According to some embodiments, since the depth D3 of the well region 110 and the depth D5 of the source region 114 or the drain region 116 are both less than the depth D2 of the second deep well region 106, the second deep well region 106 has a substantially uniform concentration from below the drain region 116 to below the source region 114 (including below the well region 110). Specifically, the second deep well region 106 has a substantially uniform concentration at the bottom of the second deep well region 106.

[0052] Although the well region 110, the gate region 112 are shown to be formed first herein, and then the source region 114 and the drain region 116 are formed, the present application is not limited thereto. The process sequence may be adjusted. For example, the source region 114 and the drain region 116 may be formed first, and then the well region 110 and the gate region 112 may be formed.

[0053] Then, according to some embodiments, an interconnection structure is formed above the second deep well region 106 to electrically connect the first deep well region 104 to the ground terminal Gnd, electrically connect the source region 114 to the source terminal S, electrically connect the gate region 112 to the gate terminal G, and connect the drain region 116 to the drain terminal D. Then, the junction field effect transistor device 100 is formed.

[0054] In the above embodiments, since the ground terminal Gnd is electrically connected to the epitaxial layer (i.e., the first deep well region 104) instead of the substrate 102, the influence of the resistance fluctuation of the substrate 102 caused by the dopant concentration can be reduced, thereby improving the stability of the pinch-off voltage of the junction field effect transistor device 100.

[0055] Figure 2 is a cross-sectional view of a junction field effect transistor device 200 shown according to some embodiments. It should be noted that the junction field effect transistor device 200 may include components that are the same as or similar to those of the Figures 1A to 1D junction field effect transistor device 100 shown, and for simplicity, those components will not be discussed in detail again. In the following embodiments, the well region includes multiple parts.

[0056] According to some embodiments, asFigure 2 As shown, the junction field effect transistor device 200 includes a well region 202, and the well region 202 includes a plurality of portions separated from each other by a spacing S1. The well region 202 is disposed in a second deep well region 106 below the region where the gate region 112 is expected to be formed. The well region 202 may have the same first conductivity type as the substrate 102, such as P-type.

[0057] In some embodiments, the well region 202 is formed by forming a patterned mask layer over a part of the second deep well region 106 and then performing an ion implantation process on another part of the exposed second deep well region 106. Examples of the formation method and materials of the patterned mask layer are as described above, and thus will not be elaborated here. Although the well region 202 is shown herein as including four separate portions, the present application is not limited thereto. For example, the patterned mask layer can be adjusted such that the well region 202 includes more or fewer portions.

[0058] The channel region becomes narrower due to the upward movement of the bottom surface of the second deep well region 106, resulting in limited modulation space for the pinch-off voltage, which can be compensated by adjusting the well region 202, such as by adjusting the spacing S1, width W, dopant concentration, depth D6, etc. between the plurality of portions of the well region 202. The dopant concentration of the well region 202 can be about 1×10 16 atoms / cm 3 to about 1×10 17 atoms / cm 3 For example, about 5×10 16 atoms / cm 3 . The spacing S1 can be about 1 μm to about 3 μm, such as about 2 μm. The width W can be about 1 μm to about 3 μm, such as about 2 μm. The depth D6 can be about 3 μm to about 4 μm, such as about 3.5 μm. The spacing S1, respective widths W, dopant concentration, depth D6, etc. between the plurality of portions of the well region 202 can be the same or different.

[0059] The gate region 112 can be disposed over the plurality of portions of the well region 202. The edges of the well region 202 can generally correspond to the edges of the gate region 112. The second deep well region 106 can extend between the plurality of portions of the well region 202 and can contact the bottom surface of the gate region 112.

[0060] Figure 3 is a cross-sectional view showing a junction field effect transistor device 300 according to some embodiments. It should be noted that the junction field effect transistor device 300 may include components the same as or similar to those of the Figures 1A to 1D junction field effect transistor device 100 shown, and for simplicity, those components will not be discussed in detail hereinafter. In the following embodiments, no well region is provided between the second deep well region and the gate region.

[0061] According to some embodiments, as Figure 3 shown, no well region of the first conductivity type is provided between the second deep well region 106 and the gate region 112. In other words, the second deep well region 106 of the junction field effect transistor device 300 directly contacts the entire bottom surface of the gate region 112. As a result, the cross-sectional area of the channel region can be increased, further alleviating the problem of space limitation.

[0062] As Figure 3 shown, the second deep well region 106 may have a thickness T1 below the gate region 112 and a thickness T2 below the source region 114 or the drain region 116. The thickness T1 may be substantially equal to or less than the thickness T2.

[0063] In summary, the junction field effect transistor device provided by the embodiments of the present application separates the second deep well region from the substrate with the first deep well region, which can prevent the junction field effect transistor device from being affected by the resistance value of the substrate and causing the pinch-off voltage to be unstable. In addition, the junction field effect transistor device provided by the embodiments of the present application is easy to adjust and control the pinch-off voltage. For example, the pinch-off voltage can be adjusted by adjusting the concentration, depth, etc. of the dopant.

[0064] The above outlines the components of multiple embodiments, enabling those skilled in the art to better understand the various aspects of the embodiments of the present application. Those skilled in the art should understand that they can easily design or modify other processes and structures based on the embodiments of the present application to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent structures do not depart from the spirit and scope of the embodiments of the present application, and they can make various changes, substitutions, and adjustments without departing from the spirit and scope of the embodiments of the present application.

Claims

1. A junction field effect transistor device, characterized in that, Comprising: A substrate having a first conductivity type; A first deep well region disposed above the substrate and having the first conductivity type; A second deep well region disposed above the first deep well region and having a second conductivity type different from the first conductivity type, wherein the first deep well region extends between the second deep well region and the substrate; A gate region, a source region, and a drain region disposed in the second deep well region; and A well region disposed in the second deep well region below the gate region and having the first conductivity type.

2. The junction field effect transistor device according to claim 1, wherein The first deep well region separates the second deep well region from the substrate and covers an edge of the second deep well region.

3. The junction field effect transistor device according to claim 1, characterized in that, The second deep well region has a substantially uniform concentration from below the drain region to below the source region.

4. The junction field effect transistor device according to claim 1, characterized in that, The well region includes a plurality of portions spaced apart from each other by a distance.

5. The junction field effect transistor device according to claim 1, wherein, The edge of the well region substantially corresponds to the edge of the gate region.

6. A junction field effect transistor device, characterized in that, Comprising: A substrate having a first conductivity type; A first deep well region disposed above the substrate and having the first conductivity type; A second deep well region disposed above the first deep well region and having a second conductivity type different from the first conductivity type, wherein the first deep well region separates the second deep well region from the substrate; And A gate region, a source region, and a drain region disposed in the second deep well region, wherein the second deep well region directly contacts the entire bottom surface of the gate region.

7. A method for manufacturing a junction field effect transistor device, characterized in that, Comprising: Forming a first deep well region above a substrate, wherein the substrate and the first deep well region have a first conductivity type; Forming a second deep well region in the first deep well region, wherein the second deep well region has a second conductivity type different from the first conductivity type, and the depth of the second deep well region is less than the depth of the first deep well region; And Forming a gate region, a source region, and a drain region in the second deep well region, wherein the second deep well region has a substantially uniform concentration from below the drain region to below the gate region.

8. The manufacturing method of the junction field effect transistor device according to claim 7, characterized in that, Further comprising: Forming a well region in the second deep well region, wherein the well region has the first conductivity type; and Forming the gate region above the well region.

9. The manufacturing method of the junction field effect transistor device according to claim 8, characterized in that, The well region includes a plurality of portions, and the second deep well region extends between the portions.

10. The manufacturing method of the junction field effect transistor device as described in claim 7, characterized in that, The thickness of the second deep well region below the gate region is greater than the thickness below the source region.

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