Cell structure of MOSFET device and preparation method thereof

Abstract

The invention provides a cell structure of an MOSFET device and a preparation method thereof, and the structure comprises a substrate which comprises a first surface and a second surface which are opposite to each other; the epitaxial layer is located on the first surface, the surface, away from the substrate, of the epitaxial layer is a third surface, and the doping type of the epitaxial layer is the same as that of the substrate; the cellular region is located on the portion, close to the third surface, of the epitaxial layer, the cellular region comprises source electrode structures and grid electrode structures, the source electrode structures and the grid electrode structures are nonlinear in the first direction, the source electrode structures and the grid electrode structures are alternately arranged in the second direction, and the first direction and the second direction are perpendicular to the thickness direction of the substrate. The technical problem that the conduction characteristic and the short-circuit characteristic of an MOSFET device in the prior art need to be compromised and optimized is solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and more particularly, to a cell structure of a MOSFET device and a method for manufacturing the cell structure of a MOSFET device. Background Art

[0002] Silicon Carbide (SiC), as a wide-bandgap semiconductor material, has broad application prospects in high-voltage, high-power, high-temperature, and high-frequency application fields due to its advantages such as wide bandgap, high critical electric field strength, high thermal conductivity, and high saturation drift velocity.

[0003] Compared with planar MOS, the trench-gate MOSFET of silicon carbide has a significantly reduced on-state characteristic resistance because the channel is vertically arranged with a small cell size and a high channel density, and can be applied to the low-voltage high-frequency field. In the traditional trench cell scheme, mainly strip cells are used. The total length of the strips in the cell area is the channel width. After the cell size is determined, the channel width is correspondingly determined. For the same cell area, the smaller the size width, the larger the channel width, and thus the better the conduction characteristics. However, the minimum value of the size width is often limited by the process level rather than the design requirements. For example, the width of the contact hole is limited by the minimum lithography line width level and the metal filling process level, but from the perspective of device performance, the requirement for the contact hole can be smaller. Therefore, the process level limits the improvement of device performance. From the perspective of device performance, when the cell size is appropriately reduced, the channel width can be increased, the conduction characteristics can be improved, and the short-circuit characteristics can be optimized. When the cell size is too small, the distance between the P-well regions becomes smaller, increasing the resistance of the JFET region and resulting in worse conduction characteristics. Summary of the Invention

[0004] The main object of the present invention is to provide a cell structure of a MOSFET device and a method for manufacturing the cell structure of a MOSFET device to supplement a new design solution that requires trade-off optimization of the conduction characteristics and short-circuit characteristics of MOSFET devices in the prior art.

[0005] To achieve the above object, according to one aspect of the present invention, there is provided a cell structure of a MOSFET device, including: a substrate, the substrate including opposite first and second surfaces; an epitaxial layer located on the first surface, a surface of the epitaxial layer away from the substrate being a third surface, the epitaxial layer having the same doping type as the substrate; a cell area located in a portion of the epitaxial layer close to the third surface, the cell area including a source structure and a gate structure, in a first direction, the source structure and the gate structure being non-linear, and in a second direction, the source structure and the gate structure being alternately arranged, the first direction and the second direction being perpendicular to the thickness direction of the substrate respectively.

[0006] Optionally, the epitaxial layer has a first groove and a second groove; the gate structure is located in the first groove, and the source structure is located in the second groove.

[0007] Optionally, the angle between the side wall and the bottom surface of the first groove is 0° to 180°, and the angle between the side wall and the bottom surface of the second groove is 0° to 180°.

[0008] Optionally, the number of stages of the first groove is 0 to 3, and the number of stages of the second groove is 0 to 4.

[0009] Optionally, in the second direction, the distance between any two adjacent source structures and gate structures is equal or unequal.

[0010] Optionally, the orthographic projection of the gate structure on the second surface includes a first wide portion and a first narrow portion, the orthographic projection of the source structure on the second surface includes a second wide portion and a second narrow portion, the first wide portion and the first narrow portion are alternately arranged in the first direction, the second wide portion and the second narrow portion are alternately arranged in the first direction, the first wide portion and the second narrow portion are alternately arranged in the second direction, and the second wide portion and the first narrow portion are alternately arranged in the second direction.

[0011] Optionally, the cell region further includes: a first doped region, located on a side of the gate structure close to the substrate, and the projection of the first doped region on the substrate overlaps with the first wide portion, and the doping type of the first doped region is different from the doping type of the substrate; a second doped region, located on a side of the source structure close to the substrate, and the projection of the second doped region on the substrate overlaps with the second wide portion, and the doping type of the first doped region is different from the doping type of the substrate.

[0012] Optionally, in the second direction, in the epitaxial layer between the first groove and the second groove, a third doped region, a fourth doped region, and a fifth doped region are configured, the doping type of the third doped region is the same as the doping type of the substrate, the doping types of the fourth doped region and the fifth doped region are different from the doping type of the substrate, in the second direction, at least part of the third doped region is located between the source structure and the fifth doped region, and at least part of the fifth doped region is located between the fourth doped region and the second doped region.

[0013] Optionally, the cell structure further includes: a sixth doped region located on a sidewall of the source structure, the doping type of the sixth doped region being the same as that of the first doped region. In a second direction, a part of the sixth doped region is located between the third doped region and the source structure, a part of the sixth doped region is located between the fourth doped region and the source structure, and a part of the sixth doped region is located between the fifth doped region and the source structure.

[0014] Optionally, in a direction of the thickness of the substrate, at least a part of the third doped region is located between a part of the third surface and the fourth doped region, and at least a part of the third doped region is located between a part of the third surface and the fifth doped region.

[0015] Optionally, the cell structure of the MOSFET device further includes: a seventh doped region located on a side of the fourth doped region away from the third surface and a side of the fifth doped region away from the third surface, wherein the doping type of the seventh doped region is the same as that of the substrate, the doping concentration of the seventh doped region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the seventh doped region is less than the doping concentration of the third doped region.

[0016] Optionally, the source structure includes a stacked first metal layer and second metal layer, the second metal layer being located on a side of the first metal layer away from the epitaxial layer, and the first metal layer forming an ohmic contact with the epitaxial layer.

[0017] To achieve the above object, according to one aspect of the present invention, there is provided a method for manufacturing a cell structure of a MOSFET device, including: providing a substrate; forming a preliminary epitaxial layer on one side surface of the substrate, a surface of the preliminary epitaxial layer away from the substrate being a preliminary surface, the doping type of the preliminary epitaxial layer being the same as that of the substrate; removing a part of the preliminary epitaxial layer, and the remaining preliminary epitaxial layer being an epitaxial layer, a surface of the epitaxial layer away from the substrate being a third surface; and forming a gate structure and a source structure in a part of the epitaxial layer close to the third surface.

[0018] Applying the technical solution of the present invention, a cell structure of a MOSFET device is provided, including: a substrate, the substrate includes opposite first and second surfaces; an epitaxial layer, located on the first surface, the surface of the epitaxial layer away from the substrate is the third surface, and the doping type of the epitaxial layer is the same as that of the substrate; a cell region, located in the part of the epitaxial layer close to the third surface, the cell region includes a source structure and a gate structure. In the first direction, the source structure and the gate structure are non-linear, and in the second direction, the source structure and the gate structure are alternately arranged, and the first direction and the second direction are respectively perpendicular to the thickness direction of the substrate. The above-mentioned source structure and gate structure are non-linear. In the case of the same cell region area, the channel width can be increased, thereby improving the conduction characteristics of the MOSFET device. In addition, by adopting the non-linear source contact method, the contact area of the source can be increased, and the size in the width direction of the cell structure can be saved. At the same time, due to the reduction of the current density and the change of the current path, the highest hot spot is far from the substrate surface, which is beneficial to improving the stress and strain between the surface multi-layer materials during short circuit, thereby improving the short-circuit characteristics. A new idea for the compromise optimization design of the conduction characteristics and short-circuit characteristics of the MOSFET device is proposed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings forming a part of this specification are used to provide a further understanding of the present invention, and the schematic embodiments and descriptions thereof of the present invention are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 Shows a schematic structural diagram of a cell region provided according to an embodiment of the present invention;

[0021] Figure 2 Shows Figure 1 A cross-sectional view along the AA` direction;

[0022] Figure 3 Shows Figure 1 A cross-sectional view along the BB` direction;

[0023] Figure 4 Shows a schematic structural diagram of another cell region provided according to an embodiment of the present invention;

[0024] Figure 5 Shows Figure 4 A cross-sectional view along the CC` direction;

[0025] Figure 6 Shows Figure 4 A cross-sectional view along the DD` direction;

[0026] Figure 7 Shows Figure 1 Another cross-sectional view along the AA` direction;

[0027] Figure 8 shows Figure 1 Another sectional view along the BB` direction;

[0028] Figure 9 shows Figure 1 Another sectional view along the AA` direction;

[0029] Figure 10 shows Figure 1 Another sectional view along the BB` direction;

[0030] Figure 11 shows Figure 1 Another sectional view along the AA` direction;

[0031] Figure 12 shows Figure 1 Another sectional view along the BB` direction;

[0032] Figure 13 shows a schematic structural diagram of another cell region provided according to an embodiment of the present invention;

[0033] Figure 14 shows Figure 13 A sectional view along the EE` direction;

[0034] Figure 15 shows Figure 13 A sectional view along the FF` direction;

[0035] Figure 16 shows a schematic flow chart of a method for preparing a cell structure of a MOSFET device provided according to an embodiment of the present application.

[0036] Among them, the above-mentioned drawings include the following reference numerals:

[0037] 10. Substrate; 11. Epitaxial layer; 12. Cell region; 121. Source structure; 122. Gate structure; 1211. Second wide portion; 1212. Second narrow portion; 1221. First wide portion; 1222. First narrow portion; 123. First doping region; 124. Second doping region; 125. Third doping region; 126. Fourth doping region; 127. Fifth doping region; 128. Sixth doping region; 129. Seventh doping region; 1213. First metal layer; 1214. Second metal layer; 130. Gate oxide layer. Detailed implementation manners

[0038] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0039] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0040] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to describe the embodiments of the present invention here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0041] As introduced in the background art, in the prior art, it is impossible to simultaneously take into account the on-state characteristics and short-circuit characteristics of MOSFET devices. To solve the above problems, embodiments of the present application provide a cell structure of a MOSFET device and a preparation method of the cell structure of a MOSFET device.

[0042] Figure 1 It is a schematic structural diagram of a cell structure of a MOSFET device according to an embodiment of the present application. As Figures 1 to 15 shown, it includes:

[0043] A substrate 10, the substrate 10 includes opposite first and second surfaces;

[0044] An epitaxial layer 11, located on the first surface, the surface of the epitaxial layer 11 away from the substrate 10 is the third surface, and the doping type of the epitaxial layer 11 is the same as that of the substrate 10;

[0045] A cell region 12, located in a part of the epitaxial layer 11 close to the third surface, the cell region 12 includes a source structure 121 and a gate structure 122. In the first direction D1, the source structure 121 and the gate structure 122 are non-linear, and in the second direction D2, the source structure 121 and the gate structure 122 are alternately arranged. The first direction D1 and the second direction D2 are respectively perpendicular to the thickness direction of the substrate 10.

[0046] Specifically, the material of the substrate 10 can be silicon carbide, for example, 4H-SiC. The doping concentration range of the substrate 10 can be 5e 18 ~1e 21 cm -3 , and the thickness of the substrate 10 can be 50 - 500 μm. The epitaxial layer 11 can be a single-layer structure or a double-layer structure. For example, the epitaxial layer can include a buffer layer and a drift layer in a double-layer structure. For example, the doping concentration of the buffer layer can be 5e 15 ~1e 19 cm -3 , and the thickness can be 5 - 50 μm; the doping concentration of the drift layer can be 1e 14 ~5e 17 cm -3 , and the thickness can be 5 - 150 μm. And the doping types of the substrate 10 and the epitaxial layer 11 are the same, that is, when the substrate 10 is of N-type, the epitaxial layer 11 is also of N-type. The source structure 121 and the gate structure 122 can be planar structures or trench structures.

[0047] Through this embodiment, a cell structure of a MOSFET device is provided, including: a substrate, the substrate includes opposite first and second surfaces; an epitaxial layer, located on the first surface, the surface of the epitaxial layer away from the substrate is the third surface, and the doping type of the epitaxial layer is the same as that of the substrate; a cell region, located in a part of the epitaxial layer close to the third surface, the cell region includes a source structure and a gate structure, in a first direction, the source structure and the gate structure are non-linear, in a second direction, the source structure and the gate structure are arranged alternately, and the first direction and the second direction are respectively perpendicular to the thickness direction of the substrate. The source structure and the gate structure are non-linear. In the case of the same cell region area, the channel width can be increased, thereby improving the on-state characteristics of the MOSFET device. In addition, by adopting the non-linear source contact method, the contact area of the source can be increased, saving the size in the width direction of the cell structure. At the same time, due to the reduction of the current density and the change of the current path, the highest hot spot is far from the substrate surface, which is beneficial to improving the stress and strain between the surface multi-layer materials during short circuit, thereby improving the short-circuit characteristics. A new idea for the trade-off optimization design of the on-state characteristics and short-circuit characteristics of the MOSFET device is proposed.

[0048] In other embodiments, as shown in Figure 2 and Figure 3 , the epitaxial layer has a first groove and a second groove; the gate structure 122 is located in the first groove, and the source structure 121 is located in the second groove. Compared with the planar gate structure or the planar source structure, the trench structure formed by the first groove and the second groove can further improve the on-resistance and channel density of the MOSFET device.

[0049] Specifically, the above source structure and gate structure can be formed by etching source trenches and depositing source metal or gate metal. There is no limitation on the specific shapes of the above source structure and gate structure, which can be regular or irregular. The width of the above source structure and gate structure can be 0.5 - 5 μm, and the depth can be 0.5 - 2 μm.

[0050] In some embodiments, the angle between the side wall and the bottom surface of the first groove is 0° - 180°, and the angle between the side wall and the bottom surface of the second groove is 0° - 180°. That is to say, the opening of the first groove can be larger than the bottom surface of the first groove or smaller than the bottom surface of the first groove, and the same applies to the second groove. When the opening of the first groove or the second groove is larger than the corresponding bottom surface, the gate oxide layer at the corner can be further protected, the stress concentration can be reduced, and the reliability of the MOSFET device can be further improved. When the opening of the first groove or the second groove is smaller than the corresponding bottom surface, the crystal plane at the bottom of the groove can have a higher atomic arrangement density, so that a thicker gate oxide layer can be formed after thermal oxidation, and the breakdown voltage of the MOSFET device can be further increased.

[0051] In other embodiments, the number of stages of the first groove is 0 - 3, and the number of stages of the second groove is 0 - 4. The multi-stage trench structure can further reduce the on-resistance of the device by increasing the channel density and optimizing the current path.

[0052] Specifically, the number of stages of the above groove is the number of steps of the groove. When the gate structure is a planar structure, the number of stages of the first groove is 0. Similarly, when the source structure is a planar structure, the number of stages of the second groove is also 0. The number of stages of the first groove can be the same as or different from the number of stages of the second groove. As Figure 2 and Figure 3 shown, the above gate structure 122 is located in the first groove, and the above source structure 121 is located in the second groove. The number of stages of the first groove is 1, and the number of stages of the second groove is 1. Another schematic diagram of the cell region structure is as shown in Figure 4 shown. Along Figure 4 CC` in Figure 5 the cross-sectional schematic diagram shown is obtained, and along Figure 4 DD` in Figure 6 the cross-sectional schematic diagram shown is obtained. As Figure 5 shown, the above gate structure 122 is located in the first groove, and the above source structure 121 is located in the second groove. The number of stages of the first groove is 1, and the number of stages of the second groove is 2. As Figure 6As shown, the above-mentioned gate structure 122 is located in the above-mentioned first groove, the above-mentioned source structure 121 is located in the above-mentioned second groove, the number of stages of the first groove is 1, and the number of stages of the second groove is 1. As Figure 4 and Figure 5 As shown, by the above-mentioned method of step doping the source structure 121, on the one hand, the sixth doping region 128 is only distributed within a limited range of the stepped trench and will not affect the doping concentration at the channel; on the other hand, the deeper the position within the source structure 121, through the stepped configuration and away from the gate structure 122, the JFET resistance effect can be further reduced; on the further hand, the stepped source structure 121 is distributed in one stage within the fifth doping region 127, and the resistivity of the fifth doping region 127 can be reduced through the injection of the sixth doping region 128, and the length of the ohmic contact region from the second doping region 124 to the third doping region 125 is elongated with the design of the stepped source structure 121, and more holes are directly conducted away through ohmic contact from the sixth doping region 128, while further avoiding the occurrence of BJT punch-through.

[0053] In some embodiments, in the above-mentioned second direction, the distance between any two adjacent above-mentioned source structures and above-mentioned gate structures is equal or unequal. The above-mentioned second direction is the direction in which the source structures and gate structures are alternately arranged.

[0054] It should be noted that Figure 1 and Figure 4 only show some source structures and some gate structures in the cell region. In fact, the cell region also includes a plurality of other source structures 121 and gate structures 122 that are not shown. As Figure 1 As shown, in the second direction D2, the distance between two adjacent above-mentioned source structures 121 and above-mentioned gate structures 122 is equal.

[0055] As Figure 1 As shown, the positive projection of the above-mentioned gate structure 122 on the above-mentioned second surface includes a first wide portion 1221 and a first narrow portion 1222, the positive projection of the above-mentioned source structure 121 on the above-mentioned second surface includes a second wide portion 1211 and a second narrow portion 1212, the above-mentioned first wide portion 1221 and the above-mentioned first narrow portion 1222 are alternately arranged in the above-mentioned first direction D1, the above-mentioned second wide portion 1211 and the above-mentioned second narrow portion 1212 are alternately arranged in the above-mentioned first direction D1, the above-mentioned first wide portion 1221 and the above-mentioned second narrow portion 1212 are alternately arranged in the second direction D2, and the above-mentioned second wide portion 1211 and the above-mentioned first narrow portion 1222 are alternately arranged in the above-mentioned second direction D2. Moreover, the source structure 121 and the gate structure 122 are simultaneously grooved, and their positions correspond to the positions of the source contact regions, and the relative positions between the side walls of the source structure 121 and the channel remain unchanged. With the above-mentioned setting method, the process is simple and the relative positions remain unchanged, which can further ensure the uniformity of the avalanche hole current distribution.

[0056] In some other embodiments, such as Figure 2 , Figure 3 , Figures 5 to 12 shown, the above-mentioned cell region 12 further includes: a first doping region 123, located on the side of the above-mentioned gate structure 122 close to the above-mentioned substrate 10, and the projection of the first doping region 123 on the substrate 10 overlaps with the first wide portion, and the doping type of the first doping region 123 is different from that of the substrate 10; a second doping region 124, located on the side of the above-mentioned source structure 121 close to the above-mentioned substrate 10, and the projection of the second doping region 124 on the substrate 10 overlaps with the second wide portion, and the doping type of the first doping region 123 is different from that of the substrate 10. The above-mentioned first doping region 123 can be used as the gate cut-off region of the gate structure 122, and the above-mentioned second doping region 124 can be used as the source cut-off region of the above-mentioned source structure 121. By providing a source cut-off region in the above-mentioned source structure 121 and a gate cut-off region in the above-mentioned gate structure 122, better blocking robustness can be provided, the short-circuit current of the MOSFET device can be further reduced, and the short-circuit characteristics can be improved.

[0057] Specifically, a relatively high doping concentration can be set for the above-mentioned source cut-off region. Below the source structure, a highly doped field stop layer is configured discontinuously. Due to its discontinuity, the resistance of the JFET region can be improved. In addition, the length from the source cut-off region to the ohmic contact region of the second doping structure is elongated, and more holes are directly conducted away from the P++ ohmic contact, both of which avoid the occurrence of BJT punch-through. The doping concentration range of the source cut-off region can be 8e 16 -5e 19 cm -3 , and the implantation depth can be 0.5 to 3 μm. A relatively high doping concentration can be set for the above-mentioned gate cut-off region. Below the gate structure, a highly doped field stop layer is configured discontinuously. Due to its discontinuity, the resistance of the JFET region can be improved. In addition, since the gate cut-off region and the source cut-off region are configured at equal intervals, the blocking characteristics can be ensured; at the same time, a part of the JFET pinch-off function is retained, which can limit the excessive increase of the short-circuit current. The doping concentration range of the gate cut-off region can be 8e 16 -5e 19 cm -3 , and the implantation depth can be 0.5 to 3 μm. In practical applications, the above-mentioned first doping region can be located on a part of the surface or the entire surface of the above-mentioned gate structure close to the above-mentioned substrate. Similarly, the second doping region can also be located on a part of the surface or the entire surface of the above-mentioned source structure close to the above-mentioned substrate.

[0058] In practical applications, such as Figure 7 and Figure 8As shown in the figure, a first doped region 123 is disposed on the side of the gate structure 122 close to the substrate 10. At the same time, a second doped region 124 is disposed on the side of the source structure 121 close to the substrate 10. That is, cut-off regions are disposed on the sides of the gate structure 122 and the source structure 121 close to the substrate 10, and there is a gap between the two cut-off regions, which can partially increase the width of the JFET resistance region and improve the conduction characteristics, and partially retain the width of the small JFET resistance region to ensure the short-circuit current peak clamping characteristics. In addition, the cut-off regions of the gate structure 122 and the source structure 121 are alternately arranged, and the high JFET resistance region is located at the corner channel position (where the electric field is concentrated), which can reduce the current stress here, thereby further reducing the overall power stress concentration of the device, and further improving the reliability of the device.

[0059] In order to further improve the conduction characteristics of the MOSFET device, in some embodiments, a schematic structural diagram of another cell region is as Figure 13 shown, along Figure 13 in EE` in Figure 14 the cross-sectional schematic diagram shown is obtained, and along Figure 13 in FF` in Figure 15 the cross-sectional schematic diagram shown is obtained. As Figures 13 to 15 shown, the source structure 121 only opens a deep trench at the position corresponding to the second doped region 124, and only opens a contact trench on the fifth doped region 127 at other positions; that is, the positive projection of the source structure 121 on the substrate 10 overlaps with the projection of the second doped region 124 on the substrate 10.

[0060] Specifically, as Figure 2 , Figure 3 , Figures 5 to 12 , Figure 14 and Figure 15 shown, the cell structure further includes: a gate oxide layer 130, which is located on the side of the gate structure 122 close to the substrate 10 and on the sidewalls of the gate structure 122. The gate oxide layer 130 is used to isolate the gate structure 122 from the substrate 10 and prevent impurities in the substrate 10 from diffusing into the gate structure 122.

[0061] In some other embodiments, as Figure 2 , Figure 3 , Figures 5 to 12 , Figure 14 and Figure 15As shown, in the above-mentioned second direction D2, in the epitaxial layer 11 between the first groove and the second groove, a third doping region 125, a fourth doping region 126, and a fifth doping region 127 are disposed. The doping type of the third doping region 125 is the same as that of the substrate 10. The doping types of the fourth doping region 126 and the fifth doping region 127 are different from that of the substrate 10. In the second direction D2, at least part of the third doping region 125 is located between the source structure 121 and the fifth doping region 127, and at least part of the fifth doping region 127 is located between the fourth doping region 126 and the second doping region 124. The third doping region 125 can further reduce the contact resistance and improve the conduction characteristics.

[0062] Specifically, the doping concentration range of the third doping region can be 1e 18 ~5e 21 cm -3 , and the implantation depth can be 0.1 - 3 μm. Designing a contact region on the side of the third doping region can further increase the contact area of the third doping region, which is beneficial to further reducing the contact resistance and improving the conduction characteristics. In addition, the downward shift of the source structure potential is also beneficial to improving the conduction and short-circuit characteristics of the MOSFET device. The third doping region is in contact with the first doping region in the first direction. The doping concentration range of the fourth doping region can be 5e 15 ~2e 18 cm -3 , and the thickness can be 0.2 - 3 μm. The fifth doping region can be in a regular shape or an irregular shape. The doping concentration range of the fifth doping region can be 2e 17 ~8e 19 cm-3, and the implantation depth can be 0 - 3 μm.

[0063] To further improve the conduction characteristics of the MOSFET device, in some other embodiments, a contact region can also be designed on the side of the third doping region. As Figure 9 and Figure 10 shown, in the second direction, the third doping region 125 is in direct contact with the source structure 121, which can further increase the contact area of the third doping region, is beneficial to reducing the contact resistance, and can further improve the conduction characteristics. In addition, due to the downward shift of the potential of the source structure 121, the conduction and short-circuit characteristics can also be further improved.

[0064] In still some other embodiments, as Figure 11 and Figure 12As shown, in the second direction D2, the third doping region 125 directly contacts the fifth doping region 127, and the fifth doping region 127 extends to the side surface of the third doping region 125, which can reduce the ohmic contact resistivity and further improve the short-circuit characteristics.

[0065] As Figure 2 , Figure 3 , Figures 7 to 12 and Figure 14 shown, the cell structure further includes: a sixth doping region 128 located on the sidewall of the source structure 121. The doping type of the sixth doping region 128 is the same as that of the first doping region 123. In the second direction D2, part of the sixth doping region 128 is located between the third doping region 125 and the source structure 121, part of the sixth doping region 128 is located between the fourth doping region 126 and the source structure 121, and part of the sixth doping region 128 is located between the fifth doping region 127 and the source structure 121.

[0066] Specifically, the doping concentration of the sixth doping region is greater than that of the fifth doping region. The doping concentration range of the sixth doping region can be 4e 17 ~1e 20 cm -3 , and the implantation depth is 0.2 - 2 μm. It should be noted that the position setting of the sixth doping region can be adjusted according to the actual situation. As Figure 2 , Figure 3 , Figure 7 and Figure 8 shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the source structure 121 away from the substrate 10, and in the second direction, the sixth doping region 128 contacts the third doping region 125 and the source structure 121 respectively. As Figure 9 and Figure 10 shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the fifth doping region 127 away from the substrate 10, and in the second direction, the sixth doping region 128 contacts the fifth doping region 127 and the source structure 121 respectively. Figure 11 and Figure 12 shown, the surface of the sixth doping region 128 away from the substrate 10 is flush with the surface of the source structure 121 away from the substrate 10, and in the second direction, the sixth doping region 128 contacts the fifth doping region 127 and the source structure 121 respectively.

[0067] In some other embodiments, such as Figure 2 , Figure 3 and Figures 5 to 12 , Figure 14 and Figure 15As shown, in the thickness direction of the above-mentioned substrate 10, at least a part of the above-mentioned third doping region 125 is located between a part of the above-mentioned third surface and the above-mentioned fourth doping region 126, and at least a part of the above-mentioned third doping region 125 is located between a part of the above-mentioned third surface and the above-mentioned fifth doping region 127. That is to say, the third doping region 125 is located on the side of the fourth doping region 126 away from the substrate 10 and on the side of the fifth doping region 127 away from the substrate 10.

[0068] In some specific embodiments, such as Figure 2 , Figure 3 and Figures 7 to 12 , Figure 14 and Figure 15 As shown, the cell structure of the above-mentioned MOSFET device further includes: a seventh doping region 129, located on the side of the fourth doping region 126 away from the third surface and on the side of the fifth doping region 127 away from the third surface. Among them, the doping type of the seventh doping region 129 is the same as that of the substrate 10, the doping concentration of the seventh doping region 129 is greater than the doping concentration of the epitaxial layer 11, and the doping concentration of the seventh doping region 129 is less than the doping concentration of the third doping region 125. The seventh doping region 129 can be used as the JFET region of the MOSFET device.

[0069] Such as Figure 2 , Figure 3 , Figures 6 to 12 and Figure 14 As shown, the above-mentioned source electrode structure 121 includes a stacked first metal layer 1213 and a second metal layer 1214. The second metal layer 1214 is located on the side of the first metal layer 1213 away from the epitaxial layer 11, and the first metal layer 1213 forms an ohmic contact with the epitaxial layer 11.

[0070] The embodiment of the present application also provides a manufacturing method for the cell structure of a MOSFET device. Figure 16 It is a schematic flow chart of the manufacturing method for the cell structure of a MOSFET device according to the embodiment of the present application. Such as Figure 16 As shown, the method includes:

[0071] Step S701, providing a substrate, the above-mentioned substrate includes opposite first and second surfaces;

[0072] Step S702, forming a preliminary epitaxial layer on one side surface of the above-mentioned substrate. The surface of the preliminary epitaxial layer away from the substrate is a preliminary surface, and the doping type of the preliminary epitaxial layer is the same as that of the substrate.

[0073] Step S703: Remove a part of the above-mentioned preliminary epitaxial layer, and the remaining preliminary epitaxial layer is the epitaxial layer. The surface of the epitaxial layer away from the substrate is the third surface.

[0074] Step S704: Form a gate structure and a source structure in a part of the above-mentioned epitaxial layer close to the third surface.

[0075] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0076] The cell structure of the MOSFET device of the present application includes: a substrate, the substrate includes opposite first and second surfaces; an epitaxial layer located on the first surface, the surface of the epitaxial layer away from the substrate is the third surface, and the doping type of the epitaxial layer is the same as that of the substrate; a cell region located in a part of the epitaxial layer close to the third surface, the cell region includes a source structure and a gate structure. In the first direction, the source structure and the gate structure are non-linear, and in the second direction, the source structure and the gate structure are arranged alternately. The first direction and the second direction are respectively perpendicular to the thickness direction of the substrate. Since the above-mentioned source structure and gate structure are non-linear, in the case of the same cell region area, the channel width can be increased, thereby improving the conduction characteristics of the MOSFET device. In addition, by adopting the non-linear source contact method, the contact area of the source can be increased, and the size in the width direction of the cell structure can be saved. At the same time, due to the reduction of the current density and the change of the current path, the highest hot spot is far from the substrate surface, which is beneficial to improving the stress and strain between the surface multi-layer materials during short circuit, thereby improving the short-circuit characteristics. A new idea for the compromise optimization design of the conduction characteristics and short-circuit characteristics of the MOSFET device is proposed.

[0077] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A cell structure of a MOSFET device, characterized in that, Comprising: A substrate, the substrate comprising opposite first and second surfaces; An epitaxial layer located on the first surface, a surface of the epitaxial layer away from the substrate being a third surface, and the epitaxial layer having the same doping type as the substrate; A cell region located in a portion of the epitaxial layer close to the third surface, the cell region comprising a source structure and a gate structure. In a first direction, the source structure and the gate structure are non-linear, and in a second direction, the source structure and the gate structure are alternately arranged, the first direction and the second direction being perpendicular to the thickness direction of the substrate respectively.

2. The cell structure of the MOSFET device according to claim 1, characterized in that, The epitaxial layer has a first groove and a second groove; the gate structure is located in the first groove, and the source structure is located in the second groove.

3. The cell structure of the MOSFET device according to claim 2, wherein, An angle between a side wall and a bottom surface of the first groove is in the range of 0° to 180°, and an angle between a side wall and a bottom surface of the second groove is in the range of 0° to 180°.

4. The cell structure of the MOSFET device according to claim 2, wherein The number of stages of the first groove is from 0 to 3, and the number of stages of the second groove is from 0 to 4.

5. The cell structure of the MOSFET device according to claim 1, characterized in that In the second direction, a distance between any two adjacent source structures and gate structures is equal or unequal.

6. The cell structure of the MOSFET device according to claim 1, characterized in that, A positive projection of the gate structure on the second surface includes a first wide portion and a first narrow portion, a positive projection of the source structure on the second surface includes a second wide portion and a second narrow portion, the first wide portion and the first narrow portion are alternately arranged in the first direction, the second wide portion and the second narrow portion are alternately arranged in the first direction, the first wide portion and the second narrow portion are alternately arranged in the second direction, and the second wide portion and the first narrow portion are alternately arranged in the second direction.

7. The cell structure of the MOSFET device according to claim 6, characterized in that, The cell region further comprises: A first doped region located on a side of the gate structure close to the substrate, and a projection of the first doped region on the substrate overlaps with the first wide portion, and the doping type of the first doped region is different from the doping type of the substrate; A second doped region located on a side of the source structure close to the substrate, and a projection of the second doped region on the substrate overlaps with the second wide portion, and the doping type of the first doped region is different from the doping type of the substrate.

8. The cell structure of the MOSFET device according to claim 7, characterized in that, In the second direction, in the epitaxial layer between the first groove and the second groove, a third doped region, a fourth doped region and a fifth doped region are arranged. The doping type of the third doped region is the same as the doping type of the substrate, the doping types of the fourth doped region and the fifth doped region are different from the doping type of the substrate. In the second direction, at least a part of the third doped region is located between the source structure and the fifth doped region, and at least a part of the fifth doped region is located between the fourth doped region and the second doped region.

9. The cell structure of the MOSFET device according to claim 8, characterized in that, The cell structure further comprises: The sixth doped region is located on the sidewall of the source structure. The doping type of the sixth doped region is the same as that of the first doped region. In the second direction, part of the sixth doped region is located between the third doped region and the source structure, part of the sixth doped region is located between the fourth doped region and the source structure, and part of the sixth doped region is located between the fifth doped region and the source structure.

10. The cell structure of the MOSFET device according to claim 8, characterized in that, In the direction of the thickness of the substrate, at least part of the third doped region is located between part of the third surface and the fourth doped region, and at least part of the third doped region is located between part of the third surface and the fifth doped region.

11. The cell structure of the MOSFET device according to claim 8, characterized in that, The cell structure of the MOSFET device further includes: A seventh doped region is located on the side of the fourth doped region away from the third surface and on the side of the fifth doped region away from the third surface. Wherein, the doping type of the seventh doped region is the same as that of the substrate, the doping concentration of the seventh doped region is greater than the doping concentration of the epitaxial layer, and the doping concentration of the seventh doped region is less than the doping concentration of the third doped region.

12. The cell structure of the MOSFET device according to claim 1, characterized in that, The source structure includes a stacked first metal layer and a second metal layer. The second metal layer is located on the side of the first metal layer away from the epitaxial layer, and the first metal layer forms an ohmic contact with the epitaxial layer.

13. A method for preparing a cell structure of the MOSFET device according to any one of claims 1 to 12, characterized in that, including: Providing a substrate including opposite first and second surfaces; Forming a preliminary epitaxial layer on one side surface of the substrate. The surface of the preliminary epitaxial layer away from the substrate is the preliminary surface, and the doping type of the preliminary epitaxial layer is the same as that of the substrate; Removing part of the preliminary epitaxial layer, and the remaining preliminary epitaxial layer is the epitaxial layer. The surface of the epitaxial layer away from the substrate is the third surface; Forming a gate structure and a source structure in part of the epitaxial layer close to the third surface.

Images