High-yield vertical LED chip and preparation method thereof

Abstract

The invention provides a high-yield vertical LED chip and a preparation method thereof, and the method comprises the steps: providing a substrate, and preparing an epitaxial wafer on the substrate; processing the epitaxial wafer until the substrate is removed to form a PSS pit; the PSS pit is coated with negative photoresist, and exposure heating is carried out; coating a positive photoresist, exposing and developing the positive photoresist by using a mask plate, and removing part of the photoresist to form a positive photoresist opening; carrying out a first sub-etching program, and removing the negative photoresist at the positive photoresist opening and a part of the epitaxial layer; performing a second sub-etching program, removing the residual epitaxial layer and a part of the current blocking layer, and forming a current blocking layer opening; removing the residual negative photoresist and positive photoresist to form an isolation groove; in the first sub-etching procedure, the power of the upper electrode is 1000W-1500W, the power of the lower electrode is 500W-750W, and the ratio of the upper electrode to the lower electrode is (2-2.5): 1; in the second sub-etching procedure, the upper electrode is 350-550W, the lower electrode is 100-150W, and the ratio of the upper electrode to the lower electrode is (3.5-5): 1.

Description

Technical Field

[0001] The present invention relates to the technical field of LED production and manufacturing, and particularly relates to a vertical LED chip with a high yield and a preparation method thereof. Background Art

[0002] Light-emitting diode chips are widely used in the two fields of lighting and display due to their energy-saving and high efficiency. Many aspects involve applications with extremely high power, such as outdoor lighting and automotive lighting, etc. These high-power chips require the use of vertical-structured light-emitting diode chips.

[0003] In the prior art, during the preparation process of vertical-structured light-emitting diode chips, an inductively coupled plasma etching process is required to etch the epitaxial layer to prepare isolation grooves. However, during the preparation of the isolation grooves, due to the formation of PSS pits after laser lift-off, most of the current blocking layer under the epitaxial layer will be etched away during the process of using the inductively coupled plasma etching process to etch the epitaxial layer to prepare the isolation grooves. Eventually, the etching ions will react with the metal layer under the current blocking layer, resulting in the failure of the light-emitting diode chip. The existing solution to this problem is to thicken the current blocking layer, but this will reduce the light emission brightness of the light-emitting diode chip.

[0004] In view of the above problems, there is an urgent need to design a preparation method of a vertical LED chip with a high yield and the chip itself to address the problem of easy failure of vertical LED chips. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a vertical LED chip with a high yield and a preparation method thereof, aiming to solve the technical problems mentioned in the background art.

[0006] To achieve the above purpose, the present invention is implemented through the following technical solutions:

[0007] A preparation method of a vertical LED chip with a high yield includes the following steps:

[0008] Provide a substrate and prepare an epitaxial wafer on the substrate;

[0009] Process the epitaxial wafer until the substrate is removed by a laser lift-off process to form PSS pits;

[0010] Coat a negative photoresist on the PSS pits, expose the negative photoresist completely, and then heat the exposed negative photoresist;

[0011] Coat a positive photoresist on the surface of the negative photoresist after heating, and then use a mask plate to perform exposure and development on part of the positive photoresist to remove the exposed part of the photoresist to form a positive photoresist opening;

[0012] Based on the inductively coupled plasma etching process, perform a first sub-etching process to remove the negative photoresist at the positive photoresist opening and part of the epitaxial layer below this part of the negative photoresist;

[0013] Based on the inductively coupled plasma etching process, perform a second sub-etching process to remove the remaining epitaxial layer below this part of the negative photoresist and part of the current blocking layer in contact with the epitaxial layer to form a current blocking layer opening;

[0014] Remove the remaining negative photoresist and positive photoresist to form an isolation groove;

[0015] In the first sub-etching process, the power of the upper electrode is 1000W - 1500W, the power of the lower electrode is 500W - 750W, and the ratio of the power of the upper electrode to the power of the lower electrode is (2 - 2.5):1;

[0016] In the second sub-etching process, the power of the upper electrode is 350W - 550W, the power of the lower electrode is 100W - 150W, and the ratio of the power of the upper electrode to the power of the lower electrode is (3.5 - 5):1.

[0017] According to one aspect of the above technical solution, in the step of coating a negative photoresist on the pit and performing full exposure on the negative photoresist, and then heating the exposed negative photoresist, the heating temperature is 115 - 120°C and the heating time is 90S - 120S.

[0018] According to one aspect of the above technical solution, in the first sub-etching process, the thickness of the epitaxial layer removed for the first time below part of the negative photoresist is 90% - 95%.

[0019] According to one aspect of the above technical solution, the step of removing the substrate by the laser lift-off process to form a PSS pit specifically includes:

[0020] Through the laser lift-off process, irradiate the laser on the sapphire surface of the substrate so that the substrate and part of the epitaxial layer combined with the substrate are decomposed, and metal gallium and nitrogen are generated to remove the substrate.

[0021] According to one aspect of the above technical solution, the laser spot radius of the laser lift-off process is 12um - 16um, the moving speed of the laser spot is 2500mm / S - 3000mm / S, and the power of the laser is 80W - 100W.

[0022] The present invention also provides a vertical LED chip with a high yield, which is prepared by the preparation method of the vertical LED chip with a high yield as described above.

[0023] According to one aspect of the above technical solution, an included angle α is formed between the isolation groove and the plane of the epitaxial layer, and an included angle β is formed between the opening of the current blocking layer and the plane of the epitaxial layer at the low end of the isolation groove.

[0024] According to one aspect of the above technical solution, the included angle β is smaller than the included angle α, and the difference between the included angle β and the included angle α is greater than 40°.

[0025] According to one aspect of the above technical solution, the depth of the opening of the current blocking layer is less than or equal to 1000 Å.

[0026] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0027] In the present invention, a negative photoresist is coated on the PSS pit, and a positive photoresist is coated on the negative photoresist. Then, part of the positive photoresist is subjected to exposure and development treatment by using a mask plate, and the exposed part of the photoresist is removed to form an opening of the positive photoresist. In this way, a blocking layer for developing the positive photoresist can be formed by using the exposed negative photoresist, so that only the positive photoresist is developed during the development process to form an opening of the positive photoresist. Then, through the first sub-etching process, the negative photoresist at the opening of the positive photoresist and part of the epitaxial layer under this part of the negative photoresist are removed first. And in the first sub-etching process, through specific etching parameters, the etching rate ratio between the negative photoresist and the epitaxial layer is made to be between 0.95 and 1.05, thereby ensuring that the depth of the opening of the current blocking layer is not greater than 1000 Å, and avoiding the failure of the light-emitting diode chip caused by most of the current blocking layer being etched. Then, through the second sub-etching process, the remaining epitaxial layer under this part of the negative photoresist and part of the current blocking layer in contact with the epitaxial layer are removed to form an opening of the current blocking layer. Then, the remaining negative photoresist and positive photoresist are removed to form an isolation groove. After this step, an included angle α is formed between the isolation groove and the plane of the epitaxial layer, and an included angle β is formed between the opening of the current blocking layer and the plane of the epitaxial layer at the low end of the isolation groove. And in the second sub-etching process, through specific etching parameters, the included angle β can be made smaller than the included angle α, and the difference between the included angle β and the included angle α is made greater than 40°, thereby ensuring that the insulating protective layer will not fall off at the included angle β in the subsequent process and improving the yield of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a flowchart of the preparation method of the vertical LED chip with a high yield in the first embodiment of the present invention;

[0029] Figure 2 For carrying out Figure 1 The structural schematic diagram during steps S30 and S40 in

[0030] Figure 3 For carrying out Figure 1 The structural schematic diagram during steps S50 and S60 in

[0031] Figure 4 For Figure 3 The enlarged view of part A in

[0032] Main component symbol description:

[0033] Conductive silicon wafer 19 N-type conductive metal layer 17 Current blocking layer 13 Current spreading layer 12 P-type GaN layer 113 Active light-emitting layer 112 N-type GaN layer 111 Negative photoresist 20 Positive photoresist 21 Positive photoresist opening 211 Current blocking layer via hole 131 First insulating protective layer 16 P-type conductive metal layer 15 P-type reflective metal layer 14 Bonding layer 18 Isolation groove 114 Current blocking layer opening 132

[0034] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific embodiments

[0035] For the convenience of understanding the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0036] It should be noted that when an element is referred to as being "fixedly provided on" another element, it can be directly on the other element or there can also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are only for the purpose of illustration.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0038] Please refer to Figures 1 to 4 , showing a method for preparing a high-yield vertical LED chip in the first embodiment of the present invention, including the following steps:

[0039] S10, providing a substrate and preparing an epitaxial wafer on the substrate;

[0040] S20, processing the epitaxial wafer until the substrate is removed by a laser lift-off process to form PSS pits;

[0041] S30. Coating a negative photoresist 20 on the PSS pit, exposing all of the negative photoresist 20, and then heating the exposed negative photoresist 20;

[0042] S40. Coating a positive photoresist 21 on the surface of the heated negative photoresist 20, and then performing an exposure and development process on a part of the positive photoresist 21 by using a mask plate to remove the exposed part of the photoresist to form a positive photoresist opening 211;

[0043] S50. Performing a first sub-etching process based on an inductively coupled plasma etching process to remove the negative photoresist 20 at the positive photoresist opening 211 and a part of the epitaxial layer below this part of the negative photoresist 20. It should be noted that in this embodiment, the epitaxial layer below the negative photoresist 20 is a P-type GaN layer 113;

[0044] S60. Performing a second sub-etching process based on an inductively coupled plasma etching process to remove the remaining epitaxial layer below this part of the negative photoresist 20 and a part of the current blocking layer 13 in contact with the epitaxial layer to form a current blocking layer opening 132;

[0045] S70. Removing the remaining negative photoresist 20 and positive photoresist 21 to form an isolation groove 114;

[0046] In the first sub-etching process, the upper electrode power is 1000W - 1500W, the lower electrode power is 500W - 750W, and the ratio of the upper electrode power to the lower electrode power is (2 - 2.5):1;

[0047] In the second sub-etching process, the upper electrode power is 350W - 550W, the lower electrode power is 100W - 150W, and the ratio of the upper electrode power to the lower electrode power is (3.5 - 5):1.

[0048] It can be understood that in the present invention, a negative photoresist 20 is coated on the PSS pits, and a positive photoresist 21 is coated on the negative photoresist 20. Then, part of the positive photoresist 21 is subjected to exposure and development treatment using a mask plate, and the exposed part of the positive photoresist 21 is removed to form a positive photoresist opening 211. By doing so, a blocking layer for developing the positive photoresist 21 can be formed using the exposed negative photoresist 20, so that only the positive photoresist is developed during the development process to form an opening in the positive photoresist 21. Then, through a first sub-etching process, the negative photoresist 20 at the positive photoresist opening 211 and part of the epitaxial layer below this part of the negative photoresist 20 are first removed. And in the first sub-etching process, through specific etching parameters, the etching rate ratio between the negative photoresist 20 and the epitaxial layer is made to be between 0.95 - 1.05, thereby ensuring that the depth of the current blocking layer opening 132 is not greater than 1000 Å, and avoiding the failure of the light-emitting diode chip caused by most of the current blocking layer 13 being etched. Then, through a second sub-etching process, the remaining epitaxial layer below this part of the negative photoresist 20 and part of the current blocking layer 13 in contact with the epitaxial layer are removed to form a current blocking layer opening 132. Then, the remaining negative photoresist 20 and positive photoresist 21 are removed to form an isolation groove 114. After this step, an angle α is formed between the plane of the isolation groove 114 and the epitaxial layer. An angle β is formed between the plane of the current blocking layer opening 132 at the low end of the isolation groove 114 and the epitaxial layer. And in the second sub-etching process, through specific etching parameters, the angle β can be made smaller than the angle α, and the difference between the angle β and the angle α is made greater than 40°, thereby ensuring that the insulating protective layer does not fall off at the angle β in the subsequent process and improving the yield of the LED chip.

[0049] Specifically, in this embodiment, for the first sub-etching process, the upper electrode power is 1000 W, the lower electrode power is 500 W, and their ratio is 2:1. For the second sub-etching process, the upper electrode power is 350 W, the lower electrode power is 100 W, and their ratio is 3.5:1.

[0050] Specifically, step S10 specifically includes:

[0051] S11, first, a sapphire substrate is provided, and then an N-type GaN layer 111, an active light-emitting layer 112, and a P-type GaN layer 113 are sequentially prepared from bottom to top on the sapphire substrate using the MOCVD process. The N-type GaN layer 111, the active light-emitting layer 112, and the P-type GaN layer 113 together constitute an epitaxial wafer.

[0052] Further, step S20 specifically includes:

[0053] S21. Then, apply photoresist on the surface of the P-type GaN layer 113, and then use exposure and development to remove part of the photoresist, exposing the P-type GaN layer 113 under this part of the photoresist;

[0054] S22. Use inductively coupled plasma etching process to remove part of the P-type GaN layer 113 and the active light-emitting layer 112 under the P-type GaN layer 113 until the N-type GaN layer 111 is exposed, and then remove the photoresist to form an N-type GaN layer conductive step, and then remove the photoresist;

[0055] S23. Deposit indium tin oxide on the surfaces of the P-type semiconductor layer and the N-type semiconductor layer conductive step by magnetron sputtering process; then apply photoresist on the surface of the indium tin oxide, and then use exposure and development to remove part of the photoresist, exposing part of the indium tin oxide, and then use indium tin oxide etching solution to remove the exposed indium tin oxide, and then remove the photoresist to form the current spreading layer 12;

[0056] S24. Deposit SiO2 as the current blocking layer 13 on the surfaces of the P-type semiconductor layer and the N-type semiconductor conductive step by PECVD process, then apply photoresist on the surface of the current blocking layer 13, and then use exposure and development to remove part of the photoresist, exposing the current blocking layer 13 under this part of the photoresist, and then use BOE etching to also remove the exposed current blocking layer 13 to form a current blocking layer through hole 131, and then remove the photoresist;

[0057] S25. Apply negative photoresist 20 on the surfaces of the current blocking layer through hole 131 and the current blocking layer 13, and then use exposure and development to remove part of the photoresist, and then use electron beam evaporation process to evaporate Ag metal 1500 - 2000 Å, Ni metal 300 - 500 Å, Ti metal 300 - 500 Å in sequence; then use the lift-Off process to remove the metal located on the photoresist, and then remove the photoresist to form a P-type reflective metal layer 14; wherein, in this embodiment, the Ag metal evaporated in this step is 1500 Å, the Ni metal is 300 Å, and the Ti metal is 300 Å.

[0058] S26. Apply negative photoresist 20 on the surface of the P-type reflective metal layer 14 and the current blocking layer 13 not covered by the P-type reflective metal layer 14. Then, use exposure and development to remove part of the photoresist. Then, use the electron beam evaporation process to evaporate Ti metal 200 - 300 Å, Pt metal 1500 - 2000 Å, Au metal 4000 - 8000 Å, and Cr metal 200 - 500 Å in sequence. Then, use the Lift-Off process to remove the metal located above the photoresist, and then remove the photoresist to form the P-type conductive metal layer 15. Among them, in this embodiment, the Ti metal evaporated in this step is 200 Å, the Pt metal is 1500 Å, the Au metal is 4000 Å, and the Cr metal is 200 Å.

[0059] S27. First, use the atomic layer deposition process to deposit an Al2O3 thin film 600 - 1200 Å on the surface of the P-type conductive metal layer 15 and the current blocking layer 13 not covered by the P-type conductive metal layer 15. Then, use the PECVD process to deposit a SiO2 thin film 6000 - 8000 Å. The two thin films together form the first insulating protection layer 16. Apply photoresist on the surface of the SiO2 thin film. Then, use the exposure and development process to remove part of the photoresist, exposing the first insulating protection layer 16 under this part of the photoresist. Then, use the ICP etching process to remove the exposed part of the first insulating protection layer 16 and the current blocking layer 13 under this part of the first insulating protection layer 16 to form an N-type conductive through hole, and the N-type conductive through hole is located above the conductive step of the N-type GaN layer. Then, use the grinding process to thin the sapphire substrate. Among them, in this embodiment, the deposited Al2O3 thin film is 600 Å, the SiO2 thin film is 6000 Å, and the remaining thickness of the sapphire substrate after thinning is 200 μm.

[0060] S28. Using an electron beam evaporation process, deposit Cr metal with a thickness of 20 - 50 Å, Al metal with a thickness of 2000 - 5000 Å, Ti metal with a thickness of 1500 - 2000 Å, and Pt metal with a thickness of 1500 - 2000 Å in sequence on the first insulating protective layer 16 and the formed first insulating layer through holes. The above four layers of metal together constitute the N-type conductive metal layer 17. Provide a doped conductive silicon wafer 19, and then use an electron beam evaporation process to deposit a bonding layer 18 on the doped conductive silicon wafer 19 and the N-type conductive metal layer 17 of the light-emitting diode chip. The metal bonding layer 18 includes Ti metal with a thickness of 3000 - 4000 Å and 2 - 5 stacks of Sn metal and Ni metal. In each stack, the thickness of Sn metal is 5000 - 10000 Å, and the thickness of Ni metal is 2000 - 4000 Å. Then use a thermocompression bonding process to bond the conductive silicon wafer 19 to the light-emitting diode chip through the bonding layer 18. Among them, in this embodiment, the Cr metal deposited is 20 Å, the Al metal is 2000 Å, the Ti metal is 1500 Å, the Pt metal is 1500 Å, the Ti metal used in the metal bonding layer 18 is 3000 Å, the number of stacks is 3, the thickness of Sn metal in the stack is 5000 Å, and the thickness of Ni metal is 2000 Å.

[0061] S29. Using a laser lift-off process, remove the thinned sapphire substrate. The laser lift-off process is to irradiate from the sapphire surface with a 266 nm ultraviolet laser, so that the GaN at the bonding surface of part of the sapphire substrate and the N-type GaN layer 111 decomposes by using the energy of the laser, generating metallic gallium and nitrogen gas, thereby decomposing and removing the sapphire substrate. In the laser lift-off process, the spot radius of the laser is between 12 - 16 μm, the spot moving speed is between 2500 - 3000 mm / s, and the power of the laser is between 80 - 100 W. Among them, in this embodiment, the spot radius of the laser is 12 μm, the spot moving speed is 2500 mm / s, and the power of the laser is 80 W.

[0062] Preferably, in the step of coating a negative photoresist 20 on the pit and exposing the negative photoresist 20 completely, and then heating the exposed negative photoresist 20, the heating temperature is 115 - 120 °C, and the heating time is 90 - 120 s. In the first sub-etching process, the thickness of the epitaxial layer removed for the first time under part of the negative photoresist 20 is 90% - 95%. Among them, in this embodiment, the heating temperature of this step is 115 °C, the heating time is 90 s, and the thickness of the epitaxial layer removed for the first time is 90%.

[0063] Further, after the step S70, it further includes:

[0064] S80. Use an atomic layer deposition device to deposit Al2O3 on the opening 132 of the current blocking layer and the surface of the remaining epitaxial layer as the second insulating protective layer. Then, coat a negative photoresist 20 on the surface of the second insulating protective layer. Next, expose and develop to remove part of the negative photoresist 20, exposing part of the second insulating protective layer. Then, use a BOE etching solution to etch away this exposed part of the second insulating protective layer and the current blocking layer 13 below it until the P-type conductive metal layer 15 to form a via hole.

[0065] S90. Use an electron beam evaporation process to sequentially evaporate 500 Å of Ti metal, 1000 Å of Pt metal, 5000 Å of Au metal, 2000 Å of Ni metal, and 10000 Å of Au metal. Then, use a Lift-Off process to remove the metal above the photoresist, and then remove the photoresist, thus forming a P-type pad layer. In this way, the final high-yield vertical LED chip is fabricated.

[0066] For the high-yield vertical LED chip fabricated by the above method, the depth L of the opening 132 of the current blocking layer in the epitaxial layer is 400 Å, the angle α formed by the isolation groove 114 and the plane of the epitaxial layer is 72°, and the angle β formed by the opening 132 of the current blocking layer and the plane of the epitaxial layer at the lower end of the isolation groove 114 is 25°. The difference between the two is 47°. This structural form makes the depth of the opening 132 of the current blocking layer not greater than 1000 Å, thereby avoiding the failure of the light-emitting diode chip caused by most of the current blocking layer 13 being etched, so as to improve the yield of the LED chip. At the same time, the difference between the angle β and the angle α is greater than 40°, which can ensure that the insulating protective layer will not fall off at the angle β in the subsequent process, and can also improve the yield of the LED chip.

[0067] The following table shows multiple groups of experimental data in this application to verify the feasibility of the method in the first embodiment.

[0068]

[0069] It can be seen that in the above experimental data, the maximum depth of the opening of the current blocking layer is 900 Å, and the minimum difference between the angle β and the angle α is also 43°, both of which can meet the requirements that the depth of the opening of the current blocking layer is not greater than 1000 Å and the difference between the angle β and the angle α is greater than 40°, proving that the preparation method of the above high-yield vertical LED chip is feasible.

[0070] In summary, the method for preparing a high-yield vertical LED chip in the above embodiments of the present invention can reduce the depth of the opening of the current blocking layer, thereby retaining most of the current blocking layer; at the same time, the included angle β is made smaller than the included angle α, and the difference between the included angle β and the included angle α is greater than 40°. With such a setting, it is possible to prevent the subsequent second insulating protective layer from peeling off at the included angle β. Both of the above two forms can improve the yield of the vertical LED chip.

[0071] The second embodiment of the present invention further provides a high-yield vertical LED chip, which is prepared by the method for preparing a high-yield vertical LED chip in the first embodiment.

[0072] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0073] The above-described embodiments only represent several implementation manners of the present invention. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A method for preparing a vertical LED chip with a high yield rate, characterized in that, It includes the following steps: Provide a substrate and prepare an epitaxial wafer on the substrate; Process the epitaxial wafer until the substrate is removed by a laser lift-off process to form PSS pits; Coat a negative photoresist on the PSS pits and expose the negative photoresist completely, and then heat the exposed negative photoresist; Coat a positive photoresist on the surface of the heated negative photoresist, and then use a mask to perform exposure and development processing on part of the positive photoresist to remove the exposed part of the photoresist to form a positive photoresist opening; Based on an inductively coupled plasma etching process, perform a first sub-etching procedure to remove the negative photoresist at the positive photoresist opening and part of the epitaxial layer below this part of the negative photoresist; Based on an inductively coupled plasma etching process, perform a second sub-etching procedure to remove the remaining epitaxial layer below this part of the negative photoresist and part of the current blocking layer in contact with the epitaxial layer to form a current blocking layer opening; Remove the remaining negative photoresist and positive photoresist to form an isolation groove; In the first sub-etching procedure, the upper electrode power is 1000W - 1500W, the lower electrode power is 500W - 750W, and the ratio of the upper electrode power to the lower electrode power is (2 - 2.5):1; In the second sub-etching procedure, the upper electrode power is 350W - 550W, the lower electrode power is 100W - 150W, and the ratio of the upper electrode power to the lower electrode power is (3.5 - 5):

1.

2. The preparation method of the high-yield vertical LED chip according to claim 1, characterized in that, In the step of coating a negative photoresist on the pits, exposing the negative photoresist completely, and then heating the exposed negative photoresist, the heating temperature is 115 - 120°C, and the heating time is 90S - 120S.

3. The preparation method of the high-yield vertical LED chip according to claim 1, wherein In the first sub-etching procedure, the thickness of the epitaxial layer removed for the first time below part of the negative photoresist is 90% - 95%.

4. The method for preparing a vertical LED chip with a high yield rate according to claim 1, wherein, The removing the substrate by a laser lift-off process to form PSS pits specifically includes: By a laser lift-off process, irradiate the laser on the sapphire surface of the substrate so that the substrate and part of the epitaxial layer combined with the substrate are decomposed, and metal gallium and nitrogen are generated to remove the substrate.

5. The method for preparing a high-yield vertical LED chip according to claim 4, characterized in that, The laser spot radius of the laser lift-off process is 12um - 16um, the moving speed of the laser spot is 2500mm / S - 3000mm / S, and the power of the laser is 80W - 100W.

6. A vertical LED chip with a high yield rate, characterized in that, Prepared by the method for preparing a high-yield vertical LED chip according to any one of claims 1 - 3.

7. The high-yield vertical LED chip according to claim 6, characterized in that, An included angle α is formed between the isolation groove and the plane of the epitaxial layer, and an included angle β is formed between the current blocking layer opening and the plane of the epitaxial layer at the low end of the isolation groove.

8. The high-yield vertical LED chip according to claim 7, wherein, The included angle β is smaller than the included angle α, and the difference between the included angle β and the included angle α is greater than 40°.

9. The high-yield vertical LED chip according to claim 6, wherein The depth of the current blocking layer opening is less than or equal to 1000A.

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