Capacitor structure, storage structure and preparation method thereof
By setting a first subfunction layer with a thickness greater than a preset thickness in the capacitance structure and forming a superlattice structure, the problem of impurity generation in the capacitance dielectric layer is solved, the dielectric constant is improved and the leakage is reduced, and the performance of the capacitance structure is improved.
Patent Information
- Application Number
- CN202410043071.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-11
- Publication Date
- 2025-07-11
AI Technical Summary
During the formation of the capacitance structure, part of the surface layer of the first electrode oxidizes to form metal oxides, causing the precursor to absorb oxygen to form impurity-containing compounds, which affects the film quality and dielectric constant of the capacitance dielectric layer, especially after the device size is miniaturized, the interface layer has a particularly serious impact.
By forming a first sub-functional layer with a thickness greater than or equal to a preset thickness on the first electrode surface, the second sub-functional layer precursor is prevented from absorbing oxygen from the electrode oxide, and a capacitive dielectric layer is formed by thermal annealing treatment to form a superlattice structure to increase the dielectric constant and reduce leakage.
It effectively prevents the generation of impurities, improves the film quality and dielectric constant of the capacitance dielectric layer, reduces leakage, and improves the performance of the capacitance structure.
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Figure CN120302875A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit technology, and particularly to a capacitor structure, a memory structure and a manufacturing method thereof. Background Art
[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking day by day, and the types and quantities of devices included in a single chip are increasing accordingly. As a result, any minor difference in the process production may affect the device performance.
[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention
[0004] Based on this, a capacitor structure, a memory structure and a manufacturing method thereof are provided.
[0005] A manufacturing method of a capacitor structure includes the following steps:
[0006] Form a first electrode, and oxidize a part of the surface layer of the first electrode to form an electrode oxide;
[0007] Form a plurality of stacked dielectric functional layer groups on the oxidized surface side of the first electrode. The dielectric functional layer group includes a first sub-functional layer and a second sub-functional layer. Among them, the thickness of the first sub-functional layer at least on the surface of the first electrode is greater than or equal to a first preset thickness, and the first preset thickness is a threshold thickness for preventing the precursor of the second sub-functional layer from absorbing oxygen from the electrode oxide;
[0008] Form a second electrode on the surface of the dielectric functional layer group away from the first electrode, and perform a thermal annealing treatment to form a capacitor dielectric layer.
[0009] In the above manufacturing method of the capacitor structure, after forming the first electrode, a plurality of stacked dielectric functional layer groups including a first sub-functional layer and a second sub-functional layer are formed on the oxidized surface side of the first electrode, and the thickness of the first sub-functional layer at least on the surface of the first electrode is set to be greater than or equal to a first preset thickness (the first preset thickness is a threshold thickness capable of preventing the precursor of the second sub-functional layer from absorbing oxygen from the electrode oxide), and a thermal annealing treatment is performed to make the first sub-functional layer react with the second sub-functional layer to form a capacitor dielectric layer. At this time, during the formation of the capacitor dielectric layer, the precursor of the second sub-functional layer can be effectively prevented from absorbing oxygen from the electrode oxide of the first electrode by the first sub-functional layer on the surface of the first electrode, reducing the generation of impurities, thereby facilitating the increase of the k value of the capacitor dielectric layer.
[0010] In one embodiment, a second electrode is formed on a surface of the dielectric functional layer group facing away from the first electrode, and a thermal annealing treatment is performed to form a capacitive dielectric layer, including:
[0011] Forming a second electrode on a surface of a top-layer second sub-functional layer of the plurality of dielectric functional layer groups;
[0012] Performing the thermal annealing treatment on the structure after the second electrode is formed.
[0013] In one embodiment,
[0014] the first sub-functional layers in the plurality of dielectric functional layer groups have the same thickness, and the second sub-functional layers in the plurality of dielectric functional layer groups have the same thickness,
[0015] After performing the thermal annealing treatment to form the capacitive dielectric layer, each of the dielectric functional layer groups is transformed into a superlattice unit, the superlattice unit includes a main dielectric layer and the first sub-dielectric layer, the main dielectric layer is a film layer formed by reacting the first sub-functional layer and the second sub-functional layer through the thermal annealing treatment, and the first sub-dielectric layer is the remaining first sub-functional layer after the thermal annealing treatment.
[0016] In one embodiment, the superlattice unit further includes a second sub-dielectric layer, the main dielectric layer is located between the second sub-dielectric layer and the first sub-dielectric layer, and the second sub-dielectric layer is the remaining second sub-functional layer after the thermal annealing treatment.
[0017] In one embodiment, the thickness of the first sub-functional layer is 1.5 nm - 3 nm, and / or the thickness of the second sub-functional layer is 1.5 nm - 3 nm.
[0018] In one embodiment, the material of the first electrode is ruthenium, the material of the first sub-functional layer is titanium dioxide, the material of the second sub-functional layer is strontium oxide, and the material of the main dielectric layer is strontium titanate.
[0019] A method for preparing a storage structure,
[0020] Providing a substrate;
[0021] Forming the capacitive structure on the substrate according to the above method.
[0022] In one embodiment, the substrate includes a semiconductor pillar, and forming the capacitive structure on the substrate includes:
[0023] Forming the first electrode, the capacitive dielectric layer, and the second electrode of the capacitive structure around a circumferential sidewall of the semiconductor pillar.
[0024] A capacitive structure is fabricated by the preparation method of the above capacitive structure. The capacitive structure includes:
[0025] A first electrode, with a part of its surface oxidized into electrode oxide;
[0026] A capacitive dielectric layer, located on the oxidized side of the first electrode, including a main dielectric layer and a first sub-dielectric layer, and the first sub-dielectric layer is at least located on the surface of the first electrode;
[0027] A second electrode, located on the side of the capacitive dielectric layer away from the first electrode.
[0028] In one embodiment, the capacitive dielectric layer includes a plurality of superlattice units stacked, and the superlattice unit includes the main dielectric layer and the first sub-dielectric layer.
[0029] In one embodiment, the superlattice unit further includes a second sub-dielectric layer, and the main dielectric layer is located between the second sub-dielectric layer and the first sub-dielectric layer.
[0030] In one embodiment, the material of the first electrode is ruthenium, the material of the first sub-dielectric layer is titanium dioxide, the material of the second sub-dielectric layer is strontium oxide, and the material of the main dielectric layer is strontium titanate.
[0031] A storage structure includes:
[0032] A substrate;
[0033] The above capacitive structure, located on the substrate.
[0034] In one embodiment, the substrate includes a semiconductor pillar, and the capacitive structure surrounds the semiconductor pillar. Description of the Drawings
[0035] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.
[0036] Figure 1 It is a flowchart of the preparation method of the storage structure provided in one embodiment;
[0037] Figure 2 It is a three-dimensional structure schematic diagram of the storage structure provided in one embodiment;
[0038] Figure 3 It is a flowchart of the preparation method of the capacitive structure provided in one embodiment;
[0039] Figures 4 to 7 It is a schematic cross-sectional structure diagram obtained during the preparation process of the capacitive structure provided in an embodiment.
[0040] Explanation of reference numerals:
[0041] 100 - Substrate; 110 - Semiconductor column; 200 - Capacitive structure; 210 - First electrode; 220 - Capacitive dielectric layer; 220a - Dielectric functional layer group; 221a - First sub-functional layer; 221 - First sub-dielectric layer; 222a - Second sub-functional layer; 222 - Second sub-dielectric layer; 223 - Main dielectric layer; 230 - Second electrode; 220b - Superlattice unit; 300 - Word line; 400 - Bit line. Detailed implementation manners
[0042] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Preferred embodiments of the present application are shown in the accompanying drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.
[0043] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0044] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or parts, these elements, components, regions, layers, doping types, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or part from another element, component, region, layer, doping type, or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or part discussed below may be referred to as the second element, component, region, layer, or part.
[0045] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. can be used herein to describe the relationship of one element or feature shown in the figure with other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relationship terms also include different orientations of the device during use and operation. For example, if the device in the attached drawing is flipped, an element or feature described as "under other elements" or "beneath it" or "under it" will be oriented "above" other elements or features. Thus, the exemplary terms "under" and "beneath" can include both upper and lower orientations. In addition, the device can also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are accordingly interpreted.
[0046] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, the presence of the described features, integers, steps, operations, elements, and / or components can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups is not excluded. At the same time, as used herein, the term "and / or" includes any and all combinations of the related listed items.
[0047] The related structures of the embodiments of the present invention should not be limited to the specific shapes shown in the drawings of the specification, but include shape deviations caused by, for example, manufacturing techniques. The shapes shown in the figures are substantially schematic and do not limit the scope of the present invention.
[0048] As mentioned in the background art, since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet the needs of current products. For example, to meet product requirements, a capacitive dielectric layer with a high dielectric constant (k value) is developed.
[0049] However, during the actual research and development process of the capacitive dielectric layer, the inventors found that the following problems would occur:
[0050] During the formation of the capacitive structure, first, the first electrode is formed, and then the capacitive dielectric layer is formed. However, a part of the surface layer of the first electrode may be oxidized to form metal oxides. This causes some precursors to absorb oxygen from the metal oxides of the first electrode during the formation of the capacitive dielectric layer, resulting in an unsaturated reaction and generating compounds containing impurities. These impurity-containing compounds cause the film quality of the capacitive dielectric layer formed after annealing to be poor and the dielectric constant to be low, thereby affecting the performance of the capacitive structure. Especially after the device size is miniaturized, the influence of the interface layer is particularly serious.
[0051] For example, when developing a high dielectric constant material strontium titanate (STO), the related technical solution is to first form a ruthenium (Ru) electrode as the first electrode. However, the Ru metal electrode interface is easily oxidized to form RuO2. At this time, when forming the capacitance dielectric layer STO, some precursors may absorb oxygen from RuO2, resulting in an unsaturated reaction and generating compounds containing C impurities such as SrCO3. These C-containing compounds will deteriorate the film quality of STO, thereby affecting the performance of the capacitor.
[0052] Based on this, the embodiments of the present application provide a capacitance structure, a storage structure, and a preparation method thereof.
[0053] In one embodiment, please refer to Figure 1 , and a preparation method of a storage structure is provided, including the following steps:
[0054] Step S10, providing a substrate 100;
[0055] Step S20, forming a capacitance structure 200 on the substrate 100.
[0056] As an example, the substrate 100 may include a substrate. The substrate may be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate may also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate should not limit the protection scope of the present application.
[0057] In addition, the substrate 100 may further include other structures or film layers formed on the substrate.
[0058] As an example, please refer to Figure 2 , the substrate 100 may further include a semiconductor pillar 110 (such as a silicon pillar). At this time, the capacitance structure 200 may be formed around the circumferential sidewall of the semiconductor pillar 110. For example, a first electrode, a capacitance dielectric layer, and a second electrode may be sequentially formed around the circumferential sidewall of the semiconductor pillar 110.
[0059] The shape of the semiconductor pillar 110 may be square columnar or cylindrical, etc. The specific shape of the semiconductor pillar 110 is not limited here.
[0060] Meanwhile, as an example, multiple semiconductor pillars 110 may be formed on a substrate. Moreover, each layer of semiconductor pillars 110 may extend along a first direction and be arranged along a second direction. The plane determined by the first direction and the second direction may be parallel to the substrate.
[0061] One end of the semiconductor pillar 110 in its extending direction (the first direction) may be surrounded by a capacitor structure 200. Meanwhile, the middle part of the semiconductor pillar 110 may be surrounded by a word line 300, thereby forming a gate-all-around (GAA) transistor structure. The same word line 300 may also extend along a third direction and penetrate through multiple layers of semiconductor pillars 110. The third direction is, for example, perpendicular to the substrate. Meanwhile, the other end of the semiconductor pillar 110 in its extending direction (the first direction) may be connected to a bit line 400. The bit line 400 may extend along the second direction, thereby connecting multiple semiconductor pillars 110 arranged along the second direction in the same layer.
[0062] The transistor structure and / or the bit line 400 may be formed after the capacitor structure 200 is formed, or may be formed before the capacitor structure 200 is formed, and there is no limitation here.
[0063] Of course, in other examples, the substrate 100 is in other forms. For example, the substrate 100 may also have a flat upper surface, and the capacitor structure 200 may be formed on this upper surface of the substrate 100, thereby forming a planar capacitor.
[0064] In one embodiment, please refer to Figure 3 , a method for preparing a capacitor structure 200 is provided, including:
[0065] Step S100, forming a first electrode 210, and oxidizing a partial surface layer of the first electrode 210 to form an electrode oxide;
[0066] Step S200, forming a plurality of stacked dielectric functional layer groups 220a on the oxidized side surface of the first electrode 210. The dielectric functional layer group 220a includes a first sub-functional layer 221a and a second sub-functional layer 222a. Among them, the thickness of at least the first sub-functional layer 221a located on the surface of the first electrode 210 is greater than or equal to a first preset thickness, and the first preset thickness is a threshold thickness capable of preventing the precursor for forming the second sub-functional layer 222a from absorbing oxygen from the electrode oxide;
[0067] Step S300, forming a second electrode 230 on the surface of the dielectric functional layer group 220a facing away from the first electrode 210, and performing a thermal annealing treatment to form a capacitor dielectric layer.
[0068] In step S100, please refer to Figure 4, the material of the first electrode 210 may include, but is not limited to, ruthenium (Ru). For example, the material of the first electrode 210 may also include any one or several of Ti, Ta, and conductive metal compounds such as TiN and TaN.
[0069] After the first electrode 210 is formed, a part of its surface layer may be oxidized into an electrode oxide 211. As an example, the surface layer of the first electrode 210 may be oxidized when an oxygen source is introduced during the formation of the dielectric functional layer group 220a.
[0070] In step S200, please refer to Figure 5 , when forming the dielectric functional layer group 220a at the bottom layer, the precursor of the first sub-functional layer 221a may be introduced first. The precursor of the first sub-functional layer 221a is denoted as the first precursor. Then an oxygen source is introduced so that the first precursor is oxidized to form the first sub-functional layer 221a. At this time, a part of the surface layer of the first electrode 210 may also be oxidized.
[0071] After the first precursor is oxidized to form the first sub-functional layer 221a, a purge gas may be introduced to remove the volatile reaction by-products generated by the reaction.
[0072] After that, the precursor of the second sub-functional layer 222a is introduced. The precursor of the second sub-functional layer 222a is denoted as the second precursor. The oxidizing property of the precursor of the second sub-functional layer 222a (i.e., the second precursor) is greater than that of the electrode oxide 211. Therefore, there is a risk of it absorbing oxygen from the electrode oxide 211.
[0073] As an example, the material of the first electrode 210 is ruthenium (Ru), the material of the first sub-functional layer 221a is titanium dioxide (TiO2), and the material of the second sub-functional layer 222a is strontium oxide (SrO). At this time, the electrode oxide 211 of the first electrode 210 may be RuO2. The oxidizing property of the Sr precursor of SrO is greater than that of the Ru ion in RuO2. Therefore, there is a risk of absorbing oxygen from RuO 2 2.
[0074] At this time, the thickness of the first sub-functional layer 221a disposed on the surface of the first electrode 210 is set to be greater than or equal to the first preset thickness, so that the second precursor (such as the Sr precursor) can be effectively isolated from the electrode oxide 211 (such as RuO2) by the first sub-functional layer 221a. Furthermore, it can effectively prevent the second precursor (such as the Sr precursor) from absorbing oxygen from the electrode oxide 211 (such as RuO2) of the first electrode 210, thereby preventing the second precursor from undergoing an unsaturated reaction and generating a compound containing impurities. Thus, the film quality of the capacitor dielectric layer 220 formed after annealing can be improved, the dielectric constant can be increased, and the performance of the capacitor structure 200 can be further improved.
[0075] Among them, the first preset thickness can be set according to actual requirements. For example, the first preset thickness can be set to 1.5 nm.
[0076] After introducing the second precursor into the second sub-functional layer 222a, an oxygen source can be introduced to oxidize the second precursor (saturation reaction) to form the second sub-functional layer 222a.
[0077] The formation process of the other dielectric functional layer group 220a can be similar. First, the first precursor of the first sub-functional layer 221a can be introduced, and then an oxygen source can be introduced to oxidize the first precursor to form the first sub-functional layer 221a. Then, a purge gas is introduced to remove the volatile reaction by-products generated by the reaction. After that, the second precursor of the second sub-functional layer 222a is introduced, and then an oxygen source is introduced to oxidize the second precursor to form the second sub-functional layer 222a. Then, a purge gas is introduced to remove the volatile reaction by-products generated by the reaction.
[0078] When the preparation of multiple dielectric functional layer groups 220a is completed, the first sub-functional layer 221a and the second sub-functional layer 222a are alternately stacked.
[0079] In step S300, please refer to Figure 6 , the material of the second electrode 230 can include any one or several of Ru, Ti, Ta, and conductive metal compounds such as TiN and TaN.
[0080] Please refer to Figure 7 , after the thermal annealing treatment, the first sub-functional layer 221a and the second sub-functional layer 222a can crystallize and can react with each other by diffusion to form a crystalline (such as polycrystalline) main dielectric layer 223. When the material of the first sub-functional layer 221a is titanium dioxide (TiO2) and the material of the second sub-functional layer 222a is strontium oxide (SrO), the material of the main dielectric layer 223 can be strontium titanate (STO).
[0081] At the same time, since the thickness of the first sub-functional layer 221a at least on the surface of the first electrode 210 is greater than or equal to the first preset thickness, after the annealing reaction, there can still be a remaining part of the first sub-functional layer 221a at least on the surface of the first electrode 210, so that at least the first sub-dielectric layer 221 is formed on the surface of the first electrode 210. At this time, after the thermal annealing treatment, the formed capacitor dielectric layer 220 includes the main dielectric layer 223 and the first sub-dielectric layer 221.
[0082] Of course, by adjusting the process conditions, it is also possible to make all the first sub-functional layers 221a react completely with the second sub-functional layer 222a after annealing, so that the capacitor dielectric layer 220 is a film layer formed by stacking multiple main dielectric layers 223 of the same material.
[0083] In this embodiment, after the first electrode 210 is formed, a plurality of dielectric functional layer groups including a first sub-functional layer and a second sub-functional layer are formed in a stacked manner on the oxidized side surface of the first electrode 210, and the thickness of the first sub-functional layer 221a disposed at least on the surface of the first electrode 210 is greater than or equal to a first preset thickness (the first preset thickness is a threshold thickness capable of preventing the precursor for forming the second sub-functional layer 222a from absorbing oxygen from the electrode oxide), and through thermal annealing treatment, the first sub-functional layer and the second sub-functional layer react to form a capacitive dielectric layer. At this time, during the formation of the capacitive dielectric layer, the precursor for forming the second sub-functional layer 222a can be effectively prevented from absorbing oxygen from the electrode oxide 211 of the first electrode 210 by the first sub-functional layer located on the surface of the first electrode, reducing the generation of impurities, which is beneficial to improving the k value of the capacitive dielectric layer.
[0084] In one embodiment, step S300 includes:
[0085] Step S310, please refer to Figure 6 , a second electrode 230 is formed on the surface of the top-layer second sub-functional layer 222a of the plurality of dielectric functional layer groups 220a;
[0086] Step S320, please refer to Figure 7 , the structure after the second electrode 230 is formed is subjected to thermal annealing treatment.
[0087] As an example, when performing thermal annealing treatment, the annealing temperature can be set to 400°C - 700°C, the annealing atmosphere can be set to N2 atmosphere, the annealing time can be set to 30s - 150s, etc.
[0088] At this time, the second electrode 230 is formed first, and then thermal annealing treatment is performed, so that the second electrode 230 can provide stress during the thermal annealing process to promote crystallization.
[0089] Of course, in other embodiments, thermal annealing treatment can also be performed first, and then the second electrode 230 is formed, and this is not limited here.
[0090] In one embodiment, the thicknesses of the first sub-functional layers 221a in the plurality of dielectric functional layer groups 220a formed in step S200 are the same, and the thicknesses of the second sub-functional layers 222a in the plurality of dielectric functional layer groups 220a are the same. At this time, the plurality of dielectric functional layer groups 220a are periodically repeated, and the thickness of the first sub-functional layer 221a in each dielectric functional layer group 220a is greater than the first preset thickness.
[0091] Meanwhile, after annealing in step S300, each dielectric functional layer group 220a is transformed into a superlattice unit 220b, and the superlattice unit 220b includes a main dielectric layer 223 and a first sub-dielectric layer 221.
[0092] At this time, the capacitive dielectric layer 220 has a superlattice structure formed by stacking a plurality of superlattice units 220b, thereby effectively increasing the dielectric constant of the capacitive dielectric layer 220.
[0093] At the same time, compared with the conventional method of making the first sub-functional layer 221a and the second sub-functional layer 222a fully react to form a polycrystalline main dielectric layer 223 (such as STO) after rapid thermal annealing, the grain size in the capacitive dielectric layer 220 with a superlattice structure can be effectively increased. And the larger the grain size, the smaller the leakage current generated between the grain boundaries. Therefore, when the thickness of the capacitive dielectric layer 220 is the same, this embodiment can further reduce the leakage current path in the capacitive dielectric layer 220 and suppress leakage. Under the same leakage requirement, this embodiment can further reduce the thickness of the capacitive dielectric layer 220.
[0094] In one embodiment, the thickness of the second sub-functional layer 222a is greater than a second preset thickness.
[0095] At this time, since the thickness of the second sub-functional layer 222a is greater than the second preset thickness, there is a remaining portion after the annealing reaction of the second sub-functional layer 222a, thereby forming the second sub-dielectric layer 222.
[0096] The second preset thickness can be set according to actual requirements. For example, the second preset thickness can be set to 1.5 nm.
[0097] At this time, please refer to Figure 7 , each superlattice unit 220b formed after step S300 includes a first sub-dielectric layer 221, a main dielectric layer 223, and a second sub-dielectric layer 222. The main dielectric layer 223 is located between the second sub-dielectric layer 222 and the first sub-dielectric layer 221, thereby facilitating the adjustment of the proportion of each element in the superlattice unit 220b, and thus facilitating the increase of the dielectric constant.
[0098] For example, when the material of the first sub-functional layer 221a is titanium dioxide (TiO2) and the material of the second sub-functional layer 222a is strontium oxide (SrO), and the material of the main dielectric layer 223 can be strontium titanate (STO), when the thickness of the first sub-functional layer 221a is greater than a first preset thickness to make the superlattice unit 220b include the first sub-dielectric layer 221, and the thickness of the second sub-functional layer 222a is greater than the second preset thickness to make the superlattice unit 220b include the second sub-dielectric layer 222, the proportion of Sr elements in the superlattice unit 220b can be effectively increased, thus facilitating the increase of the dielectric constant.
[0099] As an example, the total thickness of the plurality of stacked medium functional layer groups 220a formed in step S200 can be, for example, 5 nm - 20 nm. Among them, the thickness of each first sub-functional layer 221a can be 1.5 nm - 3 nm, and at the same time, the thickness of each second sub-functional layer 222a can be 1.5 nm - 3 nm.
[0100] At this time, a single first sub-functional layer 221a and / or a single second sub-functional layer 222a can have at least three atomic layers, so that after thermal annealing, a superlattice unit 220b including a first sub-medium layer 221, a main medium layer 223, and a second sub-medium layer 222 can be formed.
[0101] It should be understood that although Figure 1 the steps in the flowchart of Figure 1 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover,
[0102] In one embodiment, please refer to Figure 7 , and a storage structure is further provided. The storage structure includes a substrate 100 and a capacitor structure 200.
[0103] The substrate 100 can include a substrate. The substrate can be composed of a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate can also include substrates such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate should not limit the protection scope of this application.
[0104] In addition, the substrate 100 can further include other structures or film layers formed on the substrate.
[0105] As an example, the substrate 100 may further include semiconductor pillars 110 (such as silicon pillars), and at this time, the capacitor structure 200 may be formed around the semiconductor pillars 110. In addition, the storage structure may further include a transistor structure and bit lines 400.
[0106] Multiple layers of semiconductor pillars 110 may be formed on the substrate. Moreover, each layer of semiconductor pillars 110 may extend along a first direction and be arranged along a second direction. The plane determined by the first direction and the second direction may be parallel to the substrate.
[0107] One end of the semiconductor pillar 110 in its extending direction (the first direction) may be surrounded by the capacitor structure 200. At the same time, the middle part of the semiconductor pillar 110 may be surrounded by a gate dielectric layer (not shown), and the gate dielectric layer may be surrounded by a word line 300, thereby forming a gate-all-around (GAA) transistor structure. And the same word line 300 may extend along a third direction and penetrate through multiple layers of semiconductor pillars 110. The third direction is perpendicular to the substrate, for example. At the same time, the other end of the semiconductor pillar 110 in its extending direction (the first direction) may be connected to the bit line 400. The bit line 400 may extend along the second direction so as to connect multiple semiconductor pillars 110 in the same layer.
[0108] Of course, in other examples, the substrate 100 may also have a flat upper surface, and the capacitor structure 200 may be formed on this upper surface of the substrate 100, thereby forming a planar capacitor.
[0109] In one embodiment, a capacitor structure 200 is further provided, which includes a first electrode 210, a capacitor dielectric layer 220, and a second electrode 230.
[0110] A partial surface layer of the first electrode 210 is oxidized into an electrode oxide 211.
[0111] The material of the first electrode 210 may include but is not limited to ruthenium (Ru). For example, the material of the first electrode 210 may further include any one or several of Ti, Ta, and conductive metal compounds such as TiN and TaN. When the material of the first electrode 210 is Ru, the material of the electrode oxide 211 may be RuO2.
[0112] The capacitor dielectric layer 220 is located on the oxidized side of the first electrode 210. The capacitor dielectric layer 220 includes a main dielectric layer 223 and a first sub-dielectric layer 221. The material of the main dielectric layer 223 may be strontium titanate (STO), for example. The material of the first sub-dielectric layer 221 may be titanium dioxide (TiO2), for example. The first sub-dielectric layer 221 is at least located on the surface of the first electrode 210.
[0113] The second electrode 230 is located on the side of the capacitor dielectric layer 220 away from the first electrode 210. That is, the second electrode 230 and the first electrode 210 are respectively located on both sides of the capacitor dielectric layer 220.
[0114] The material of the second electrode 230 may include any one or several of Ru, Ti, Ta, and conductive metal compounds such as TiN and TaN.
[0115] In one embodiment, the capacitive dielectric layer 220 includes a plurality of superlattice units 220b stacked. The superlattice unit 220b includes a main dielectric layer 223 and a first sub-dielectric layer 221.
[0116] At this time, in the capacitive dielectric layer 220, the superlattice units 220b may be stacked periodically to form a superlattice structure.
[0117] The dielectric constant of the capacitive dielectric layer 220 having a superlattice structure can be effectively increased. And when the thickness of the capacitive dielectric layer 220 is the same, the leakage current in the capacitive dielectric layer 220 having a superlattice structure can be effectively reduced.
[0118] In one embodiment, the superlattice unit 220b further includes a second sub-dielectric layer 222. The main dielectric layer 223 is located between the second sub-dielectric layer 222 and the first sub-dielectric layer 221.
[0119] At this time, it is convenient to adjust the proportion of each element in the superlattice unit 220b, so as to facilitate the increase of the dielectric constant. For example, when the material of the main dielectric layer 223 is strontium titanate (STO), the material of the first sub-dielectric layer 221 is titanium dioxide (TiO2), and the material of the second sub-dielectric layer 222 is strontium oxide (SrO), the superlattice unit 220b includes the second sub-dielectric layer 222, so that the proportion of Sr element in the superlattice unit 220b can be effectively increased, thus facilitating the increase of the dielectric constant.
[0120] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0121] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several deformations and improvements can be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.
Claims
1. A method for preparing a capacitive structure, characterized in that, It includes the following steps: Form a first electrode, and a part of the surface layer of the first electrode is oxidized to form an electrode oxide; Form a plurality of dielectric functional layer groups arranged in a stacked manner on the oxidized side surface of the first electrode. The dielectric functional layer group includes a first sub-functional layer and a second sub-functional layer. Among them, the thickness of the first sub-functional layer at least on the surface of the first electrode is greater than or equal to a first preset thickness, and the first preset thickness is a threshold thickness that can prevent the precursor for forming the second sub-functional layer from absorbing oxygen from the electrode oxide; Form a second electrode on the surface of the dielectric functional layer group facing away from the first electrode, and perform a thermal annealing treatment to form a capacitive dielectric layer.
2. The preparation method of the capacitor structure according to claim 1, characterized in that, The step of forming a second electrode on the surface of the dielectric functional layer group facing away from the first electrode and performing a thermal annealing treatment to form a capacitive dielectric layer includes: Form a second electrode on the surface of the top-layer second sub-functional layer of the plurality of dielectric functional layer groups; Perform the thermal annealing treatment on the structure after forming the second electrode.
3. The method for preparing a capacitive structure according to claim 1, wherein The thicknesses of the first sub-functional layers in the plurality of dielectric functional layer groups are the same, and the thicknesses of the second sub-functional layers in the plurality of dielectric functional layer groups are the same. After performing the thermal annealing treatment to form a capacitive dielectric layer, each of the dielectric functional layer groups is transformed into a superlattice unit. The superlattice unit includes a main dielectric layer and the first sub-dielectric layer. The main dielectric layer is a film layer formed by reacting the first sub-functional layer and the second sub-functional layer through the thermal annealing treatment, and the first sub-dielectric layer is the remaining first sub-functional layer after the thermal annealing treatment.
4. The method for preparing a capacitive structure according to claim 3, wherein The thickness of the second sub-functional layer is greater than a second preset thickness; The superlattice unit further includes a second sub-dielectric layer. The main dielectric layer is located between the second sub-dielectric layer and the first sub-dielectric layer, and the second sub-dielectric layer is the remaining second sub-functional layer after the thermal annealing treatment.
5. The manufacturing method of the capacitor structure according to claim 4, wherein, The thickness of the first sub-functional layer is 1.5 nm - 3 nm, and / or the thickness of the second sub-functional layer is 1.5 nm - 3 nm.
6. The preparation method of the capacitance structure according to claim 4, wherein, The material of the first electrode is ruthenium, the material of the first sub-functional layer is titanium dioxide, the material of the second sub-functional layer is strontium oxide, and the material of the main dielectric layer is strontium titanate.
7. A method for preparing a storage structure, wherein Provide a substrate; Form the capacitive structure on the substrate according to the method of any one of claims 1 - 6.
8. The preparation method of the storage structure according to claim 7, characterized in that, The substrate includes a semiconductor pillar. The step of forming the capacitive structure on the substrate includes: Around the circumferential sidewall of the semiconductor pillar, form the first electrode, the capacitive dielectric layer and the second electrode of the capacitive structure.
9. A capacitive structure, characterized in that, Prepared by using the method for preparing a capacitive structure according to any one of claims 1 - 6, the capacitive structure includes: A first electrode, a part of the surface layer of which is oxidized into an electrode oxide; A capacitive dielectric layer, located on the oxidized side of the first electrode, including a main dielectric layer and a first sub-dielectric layer, and the first sub-dielectric layer is at least located on the surface of the first electrode; The second electrode is located on a side of the capacitive dielectric layer away from the first electrode.
10. The capacitive structure according to claim 9, wherein, The capacitive dielectric layer includes a plurality of superlattice units stacked, and the superlattice unit includes the main dielectric layer and the first sub-dielectric layer.
11. The capacitive structure according to claim 10, wherein The superlattice unit further includes a second sub-dielectric layer, and the main dielectric layer is located between the second sub-dielectric layer and the first sub-dielectric layer.
12. The capacitive structure according to claim 11, wherein The material of the first electrode is ruthenium, the material of the first sub-dielectric layer is titanium dioxide, the material of the second sub-dielectric layer is strontium oxide, and the material of the main dielectric layer is strontium titanate.
13. A storage structure, characterized in that, Comprising: A substrate; The capacitive structure according to any one of claims 9-12, located on the substrate.
14. The storage structure according to claim 13, wherein The substrate includes a semiconductor column, and the capacitive structure surrounds the semiconductor column.