Method for monitoring and managing conduction losses of electronic circuit

Abstract

The invention relates to a method for monitoring and managing the conduction losses of an electronic circuit, the electronic circuit comprising at least a first transistor (T1) and a second transistor (T2), the first transistor (T1) and the second transistor (T2) being coupled in parallel, the method comprising: # a first step E1) in which the first transistor (T1) is operated such that it transitions into a closed state, and # a second step E2) in which the second transistor (T2) is operated such that it transitions into a closed state; the invention relates to a method for operating a first transistor (T1) in a closed state and measuring a first closing delay (DfT1) of said first transistor after the first transistor (T1) is operated in the closed state, # a second step E2) in that the second transistor (T2) is operated such that it transitions into the closed state in which the second transistor (T2) is operated after a first determined duration TM1, # a third step E3) in that the second transistor (T2) is operated such that it transitions into the closed state after a second determined duration TM1. A fourth step E4) of measuring a first turn-off delay (DoT1) of the first transistor (T1) after operation of the first transistor (T1) in the open state, a fourth step E4) of operating the second transistor (T2) in the open state, and a fifth step E5) of measuring a second turn-off delay (DoT1) of the first transistor (T1) after operation of the second transistor (T2) in the open state, operation of the second transistor (T2) in the open state occurs after a second determined duration TM2.

Description

Technical Field

[0001] The present invention relates to the field of electric vehicles and, more precisely, to a method for monitoring and managing the conduction losses of an electronic circuit. Background Art

[0002] An electric vehicle generally includes at least one electric motor, such as an asynchronous electric motor, which is adapted to rotate at least one wheel of the electric vehicle. It also includes at least one high-voltage battery, such as an 800-volt battery, which is adapted to provide electrical energy to supply the electric motor.

[0003] To allow the supply of electrical energy to the electric motor by the high-voltage battery, the electric vehicle also includes an on-board charger, which is better known by its English name OBC (for "On Board Charger"). The on-board charger is connected on the one hand to the high-voltage battery and on the other hand to the power supply network. The on-board charger allows the conversion of the alternating voltage provided by the power supply network into a direct current voltage for charging the battery.

[0004] The on-board charger mainly includes: a power factor corrector circuit, the power factor corrector being well known by its English name PFC (for "Power Factor Corrector"); a DC-DC voltage converter, which is commonly referred to as a "DC / DC converter"; and a microcontroller capable of operating the power factor corrector circuit.

[0005] In the case of charging the high-voltage battery, the power factor corrector circuit is an element of the on-board charger that implements the conversion of the alternating voltage provided by the power supply network into a direct current voltage. For example, in the case where the power supply network is a three-phase alternating voltage type network, the power factor corrector circuit includes three branches. Each branch is generally referred to as a unit and includes two transistors coupled in series, and each unit is coupled to one phase of the alternating voltage.

[0006] As mentioned in the above description, the role of the power factor corrector circuit is to transform the alternating voltage into a direct current voltage. To this end, the switches or transistors of the unit are operated so that the switching is carried out in a determined order; the units themselves are also operated in a determined order in order to rectify the input signal to create a direct current signal at the output of the PFC.

[0007] The power to be transmitted is relatively high, and thus each switch or transistor suffers from so-called "switching" losses when the state changes. When these switching losses are repeated and not controlled, these losses can cause high heating of the switches and significantly reduce the lifetime duration.

[0008] In order to reduce the power transmitted by a transistor, document FR2114069 first proposed positioning additional transistors in parallel. Thus, such an arrangement cleverly allows reducing the power through the transistor.

[0009] In order to limit switching losses, document FR2114069 also proposed an initial operating strategy for the parallel transistors of an operating unit. The aim of this method is to first switch the first of two transistors coupled in parallel and to wait for a determined duration before operating the second transistor. Thus, the switching losses when the second transistor switches can be reduced. In fact, the first transistor has already switched, so there are no switching losses for the second transistor.

[0010] With this solution, it is possible to control the conduction losses of a switching unit including two transistors coupled in parallel. However, a fixed switching duration, and more particularly the waiting time before the second transistor switches, is not optimal for the conduction losses of said transistors which may lead to a drift of the switching time representing a possible degradation of the first transistor. SUMMARY OF THE INVENTION

[0011] The present invention relates to a method for monitoring and managing the conduction loss of an electronic circuit, the electronic circuit comprising at least a first transistor and a second transistor, the first transistor and the second transistor being coupled in parallel; the method comprising: a first step E1), which consists in operating the first transistor so that it transitions to a closed-circuit state and measuring a first closing delay of the first transistor after the first transistor is operated in the closed-circuit state; a second step E2), which consists in operating the second transistor so that it transitions to a closed-circuit state, the operation of the second transistor in the closed-circuit state occurring after a first determined duration TM1; a third step E3), which consists in operating the first transistor so that it transitions to an open-circuit state and measuring a first opening delay of the first transistor after the first transistor is operated in the open-circuit state; a fourth step E4), which consists in operating the second transistor so that it transitions to an open-circuit state, the operation of the second transistor in the open-circuit state occurring after a second determined duration TM2; a fifth step E5), which consists in operating the second transistor so that it transitions to a closed-circuit state and measuring a first closing delay of the second transistor after the second transistor is operated in the closed-circuit state; a sixth step E6), which consists in operating the first transistor so that it transitions to a closed-circuit state, the operation of the first transistor in the closed-circuit state occurring after a third determined duration TM3; a seventh step E7), which consists in operating the second transistor so that it transitions to an open-circuit state and measuring a first opening delay of the second transistor after the second transistor is operated in the open-circuit state; an eighth step E8), which consists in operating the first transistor so that it transitions to an open-circuit state, the operation of the first transistor in the open-circuit state occurring after a fourth determined duration TM4; a ninth step E9), which consists in storing in a memory the value of the first closing delay of the first transistor, the value of the first opening delay of the first transistor, the value of the first closing delay of the second transistor, and the value of the first opening delay of the second transistor; a tenth step E10), which consists in executing steps E1) to E9) at least n times; and an eleventh step E11), which consists in performing an averaging of the n measured values of the first closing delay of the first transistor, an averaging of the n measured values of the first opening delay of the first transistor, an averaging of the n measured values of the first closing delay of the second transistor, and an averaging of the n measured values of the first opening delay of the second transistor; a twelfth step E12), which consists in executing steps E1) to E11) m times; and a thirteenth step E13), which consists in comparing m values obtained by averaging the n values accordingly.

[0012] Thanks to the present invention and its method, it is possible to detect the drift of the switching time of at least one transistor.

[0013] In an embodiment, when the result of at least one comparison of the m values drifts by p% from the average value, a software alarm is generated.

[0014] As a variant, when the result of comparing the values obtained by averaging n values of the m first closing delays of the first transistor, or the result of comparing the values obtained by averaging n values of the m first opening delays of the first transistor, or the result of comparing the values obtained by averaging n values of the m first closing delays of the second transistor, or the result of comparing the values obtained by averaging n values of the m first opening delays of the second transistor drifts by p%, then only the transistor corresponding to the drifted value is activated after the other transistor.

[0015] For example, if the observed drift of the values obtained by averaging n values of the m transistors that are activated second only continues to be similar to the drift of the observed drift, for example greater than p%, then the method proposes to activate a software alarm.

[0016] Advantageously, if the drift of the values obtained by averaging n values of the m transistors that are activated second only exhibits a drift of less than p%, then the method proposes to reactivate the corresponding transistor first.

[0017] For example, the value of p% is equal to 10%.

[0018] In an embodiment, if the drift of the values obtained by averaging n values of the m transistors that are activated only by it exhibits a drift greater than p%, then the method deactivates the transistor.

[0019] For example, the function uses the three-sigma mathematical method.

[0020] For example, at least one of the two transistors is an IGBT transistor.

[0021] For example, at least one of the two transistors is a SiC / GaN transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Other features and advantages of the present invention will become more apparent by reading the following description. The description is illustrative only and should be read with reference to the accompanying drawings, in which:

[0023] Figure 1 Figure 1 is a diagram of a charger according to the present invention,

[0024] Figure 2 Figure 2 presents an electrical schematic diagram of a power factor corrector circuit of a charger according to Figure 1 the charger,

[0025] Figure 3 Figure 3 presents a diagram of a method according to the present invention, ​​​​​

[0026] Figure 4 Figure 4 Presents the variation over time of the open or closed state of a set of switches of a power factor corrector circuit. DETAILED DESCRIPTION

[0027] The present invention will be presented in the context of its implementation in an electric vehicle, which includes at least one electric motor capable of converting electrical energy into mechanical energy in order to drive the rotation of at least one wheel of the electric vehicle.

[0028] With reference to Figure 1 , the electric vehicle includes a supply battery 10 and an electrical system, which includes an on-board charger 20 and a microcontroller 30.

[0029] The supply battery 10 is particularly capable of operating in a discharge mode, in which the supply battery 10 supplies electrical energy to the devices installed in the electric vehicle. The supply battery 10 is also capable of operating in a charging mode, in which the supply battery 10 can be charged from the electrical energy provided by the power grid. For example, the voltage of the supply battery 10 can be 400V or 800V. For example, the power grid can deliver an alternating voltage of 380 volts or 220 volts.

[0030] The on-board charger 20 - which is better known by its English name OBC (for "On Board Charger") - is connected via a connecting device to the supply battery 10, at least one device installed in the electric vehicle, and the power grid.

[0031] In an embodiment, the on-board charger 20 is called "bidirectional". Thus, when the on-board charger 20 is connected to the power grid and the supply battery 10 needs to be recharged, the on-board charger 20 can convert the alternating voltage provided by the power grid into a direct current voltage capable of charging the supply battery 10.

[0032] More precisely, the on-board charger 20 includes a power factor corrector circuit 21 and a DC-DC voltage converter 22, which is also called a DC-DC converter 22. The DC-DC converter 22 is electrically connected to the power factor corrector circuit 21 via an adapted wiring.

[0033] In addition, the DC-DC converter 22 is adapted to be electrically connected to the supply battery 10, and the power factor corrector circuit 21 is adapted to be electrically connected to a device inside or outside the vehicle or the power grid via a connecting device not shown.

[0034] Still referring to Figure 1 , the factor corrector circuit 21 is capable of converting an alternating voltage V AC into a direct current voltage V DC ​​, and vice versa. Thus, it is bidirectional.

[0035] The DC-DC voltage converter 22 is capable of converting a DC voltage V DC into another DC voltage V 10 . For example, when the supply battery 10 operates in the charging mode, the power factor correction circuit 21 is connected to the power grid, and thus the power factor correction circuit 21 converts the AC voltage V AC supplied by the power grid into a DC voltage V having a value of, for example, 650 volts DC . Finally, the DC-DC voltage converter 22 converts the DC voltage V DC into a DC voltage V adapted to recharge the supply battery 10 10 . For example, the DC voltage has a value of 400 volts or 800 volts.

[0036] Conversely, when the supply battery 10 operates in the discharging mode, which means that the power factor correction circuit 21 is connected to an electronic device to supply power to, for example, a game console installed in a vehicle, the DC-DC voltage converter 22 then converts the DC voltage V 10 supplied by the supply battery 10 into another DC voltage V DC . For example, the other DC voltage has a value of approximately 650 volts. Finally, the power factor correction circuit 21 converts the DC voltage V DC substantially limited to 650 volts into an AC voltage V capable of supplying electrical energy to the device connected to the power factor correction circuit 21 AC , in this case, as mentioned above, the device is a game console.

[0037] Referring to Figure 2 , in the case where the power grid is a three-phase network, the detailed electrical structure of the power factor correction circuit 21 will now be presented. The power grid thus includes three connection terminals, and an optional neutral terminal. In another embodiment of the present invention, in the case where the power grid is single-phase, i.e., 220V, the circuit then only presents two connection terminals.

[0038] In the present case, the power factor correction circuit 21 includes a first branch B1 or unit, a second branch B2, and a third branch B3. The first coil L1 is electrically connected to the first connection terminal BC1 of the power grid. The first connection terminal BC1 can be one of the three phases of a three-phase network.

[0039] The first branch B1 includes a first group of transistors and a second group of transistors. Each group of transistors includes at least two transistors connected in parallel. For simplicity of description, each of the first group of transistors and the second group of transistors includes two transistors connected in parallel. Thus, the first group of the first branch B1 includes a first transistor T1 and a second transistor T2 connected in parallel between a high point PH and a first midpoint PM1. The second group includes a third transistor T3 and a fourth transistor T4 connected in parallel between a low point PB and the first midpoint PM1. The first midpoint PM1 is electrically connected via a first coil L1 to a first connection terminal BC1 of an electrical device or a power grid connected to the charger 20.

[0040] The power factor correction circuit 21 further includes a second branch B2, whose structure is similar to that of the first branch B1. Thus, the second branch B2 includes a fifth transistor T5 and at least a sixth transistor T6 connected in parallel between the high point PH and a second midpoint PM2, and the second branch B2 includes a seventh transistor T7 and at least an eighth transistor T8 connected in parallel between the low point PB and the second midpoint PM2. The second midpoint PM2 is electrically connected via a second coil L2 to a second connection terminal BC2 of the power grid.

[0041] The power factor correction circuit 21 finally includes a third branch B3, whose structure is similar to that of the first branch B1. Thus, the third branch B3 includes a ninth transistor T9 and at least a tenth transistor T10 connected in parallel between the high point PH and a third midpoint PM3, and the third branch B3 includes an eleventh transistor T11 and at least a twelfth transistor T12 connected in parallel between the low point PB and the third midpoint PM3. The third midpoint PM3 is electrically connected via a third coil L3 to a third connection terminal BC3 of the power grid.

[0042] A first capacitor C1 and a second capacitor C2 are serially coupled between the high point PH and the low point PB. Optionally, a fourth terminal BC4 is connected to a fourth midpoint PM4 disposed between the first capacitor C1 and the second capacitor C2.

[0043] Advantageously, each of the branches B1, B2, B3 includes at least two transistors or a plurality of transistors coupled in parallel, thus allowing for loss distribution. The first branch B1, the second branch B2, and the third branch B3 respectively form an electrical half-bridge.

[0044] The microcontroller 30 is capable of operating the opening and closing of each of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12 of the power factor corrector circuit 21. To this end, the microcontroller 30 is capable of sending an operation signal for each transistor, and the operation signal can vary the duty cycle and the switching (i.e., opening and closing) frequency of each transistor. The microcontroller 30 is, for example, a processor capable of implementing a set of instructions that allows these functions to be achieved.

[0045] As mentioned above, the transistors exhibit a switching time necessary, for example, to transition from a high level (open circuit) to a low level (closed circuit). This switching time is different for different transistors, and furthermore, it may evolve according to temperature and also the aging of the transistors. Moreover, the switching time from a high level to a low level is not necessarily the same as the switching time from a low level to a high level.

[0046] Referring Figure 3 、 Figure 4 to FIGS. 4 and 5, an implementation form of the method implemented by the microcontroller 30 will now be presented.

[0047] The method is described herein in a case where it is necessary to operate the closing and opening of a first switch T1 and a second switch T2 mounted in parallel. However, the method described below can also be applied to any group of at least two switches mounted in parallel in the power factor corrector circuit 21. In addition, any other type of electronic circuit including at least two transistors mounted in parallel can also be operated by the method of the present invention. For the sake of simplicity of description, the method will be described for a group of two switches, such as the first transistor T1 and the second transistor T2 of the first unit B1.

[0048] The method includes a first closing step E1 ( Figure 3 ), which consists of operating the first switch T1. To this end, for example, the microcontroller 30 generates a first operation signal Vgs1 ( Figure 4 ) for closing the first switch T1 at a first moment t1. The first switch T1 then closes within a delay called the first closing delay Df1_T1 of the first switch, and the first closing delay is inherent to the first transistor T1 and corresponds to the switching time of the transistor, that is, the closing time of the switch (or the switching of the transistor) counted from the receipt of the closing command (see Figure 4 ). Thus, once the first transistor T1 is closed, the midpoint PM1 is coupled to the high point PH.

[0049] Advantageously, after a first duration TM1 (100 ns in this case) greater than the first closing delay Df1_T1 of the first switch, a second closing step E2 of the second switch T2 is achieved. As a reminder, the second switch T2 is mounted in parallel with the first switch T1; the first switch T1 is closed when the second closing step E2 is carried out.

[0050] In other words, according to this first embodiment, the second closing step E2 involves the closing of the second switch T2 mounted in parallel with the first switch T1, where the microcontroller 30 sends a second operating signal Vgs2 for closing the second switch T2 at a second moment t2. The second moment t2 occurs after the end of the first closing delay Df1_T1 of the first switch. Advantageously, since the first midpoint PM1 is already at the potential of the high point PH due to the closing of the first switch T1, the second switch T2 does not suffer from switching losses.

[0051] The method according to the invention then provides a third opening step E3 of the closed first switch T1 (see Figure 4 ). Thus, the microcontroller 30 sends a third operating signal for opening the first switch T1 at a third moment t3. The first switch T1 then opens within a delay called the first opening delay Do1_T1 of the first switch, which is inherent to the first transistor T1 and corresponds to the switching time, i.e., the switching-off time of the switch from the moment the opening command is received.

[0052] The second switch T2 remains closed when the first switch T1 opens, the voltage at the first midpoint PM1 is always equal to the voltage defined at the high point PH, and the first switch T1 does not suffer from switching losses.

[0053] After the first opening delay Do1_T1 of the first switch - the first opening delay Do1_T1 will be detailed later based on the sending of the first opening operation signal - a fourth opening step E4 of the second switch T2 is achieved. To this end, the microcontroller 30 sends a second operating signal for opening the second switch T2 at a fourth moment t4.

[0054] To optimize the time when only one of the two transistors is conducting, the method of the invention provides for measuring the actual switching time of the first transistor T1 in order to initiate the switching of the second transistor T2 within an optimal delay, so as to better distribute the transmitted electrical power between the two transistors T1 and T2.

[0055] To this end, in an embodiment, the invention provides a method: measuring the actual switching time of the first transistor T1 at each operating change or state change of the first transistor T1. In an embodiment, the connectivity for measuring the actual switching time of the transistor is the connectivity already present in the microcontroller 30.

[0056] As illustrated in Figure 4 , the method for measuring the actual switching time of a first transistor T1 includes a first step M1, which consists in waiting for the end of the state change of the first transistor T1 after a state change operation signal. To this end, for example, it is proposed to detect the signal on the source of the first transistor T1 and detect its transition to a low threshold level (for the transition from the off state to the on state) or detect its transition to a high threshold level (for the reverse switching). The low threshold and the high threshold are fixed and are determined according to the voltage levels of the electrical arrangement in which these two transistors are deployed.

[0057] Once the actual state change is detected, the method consists in a second step M2: measuring the actual switching time of the first transistor T1 during the second step M2. To this end, during the second step M2, the delay between the change in the state of the first closing operation signal of the first switch T1 corresponding to the first moment t1 and the value corresponding to the first closing delay of the first switch T1 (i.e., Df1_T1) is measured. For example, during the second step M2, the subtraction between the value corresponding to Df1_T1 and the value corresponding to the first moment t1 is performed. The value thus calculated is stored in the storage area of the microcomputer at the third step M3.

[0058] Advantageously, the method for measuring the actual switching time of the first transistor T1 as discussed above is also used when the first transistor T1 switches from the on state to the off state.

[0059] To this end, the method according to the invention proposes to measure the actual switching time of the first transistor T1 during a fourth step M4, which consists in waiting for the end of the state change of the first transistor T1 after a state change operation signal. To this end, for example, it is proposed to detect the signal on the source of the first transistor T1 and detect its transition to a high threshold level (for the transition from the on state to the off state).

[0060] Once the actual state change is detected, the method implements the measurement of the actual switching time of the first transistor T1 at the fifth step M5. To this end, during the fifth step M5, the delay between the change in the state of the first opening operation signal of the first switch T1 corresponding to the third moment t3 and the value corresponding to the first opening delay Do1_T1 of the first switch T1 is measured. For example, during the fifth step M5, the subtraction between the value corresponding to Do1_T1 and the value corresponding to the third moment t3 is performed. The value thus calculated is stored in a dedicated storage area of the microcomputer at the sixth step M6.

[0061] Therefore, with the present invention, it is possible to accurately know the duration of the actual switching time of the first transistor T1 when transitioning from the off state to the on state and vice versa after receiving the state change signal.

[0062] Advantageously, in order to optimally control the time during which only the first transistor T1 is switched, the method of the present invention proposes to determine the actual switching time of the first transistor T1 from the off state to the on state and also from the on state to the off state by performing such measurements in n switchings. For example, in an embodiment, the method of the present invention proposes to perform one hundred measurements for the actual switching time from the high state to the low state and one hundred measurements for the actual switching time from the low state to the high state.

[0063] The methods and techniques for performing such measurements are easy for those skilled in the art.

[0064] The method of the present invention proposes to use the average value of the actual switching time from the high state to the low state and the average value from the low state to the high state as corresponding values to generate the state change signal for the second transistor T2 corresponding to t2. Therefore, advantageously, the second transistor T2 will be switched optimally.

[0065] Advantageously, in an embodiment, the present invention also proposes to perform one hundred measurements every M minutes. For example, M is equal to one minute. Therefore, the method of the present invention will achieve one hundred measurements of the actual switching time when the first transistor T1 transitions from its high state to its low state, and will achieve one hundred measurements of the actual switching time when the first transistor T1 transitions from its low state to its high state. The values thus obtained will be used for the values of t2 and t4 for subsequent switching sequences.

[0066] Therefore, it is possible to manipulate the switching of the transistor and thus the conduction loss of the first transistor T1.

[0067] In the case where the actual switching time of the first transistor T1 is greater than the average value calculated in the previous cycle, the method as described above results in conduction losses related to the switching of the second transistor T2 while the first transistor T1 has not been fully switched.

[0068] In order to reduce the conduction loss in the situation pointed out above, in another embodiment of the present invention, it is proposed to use a method step consisting of applying the three - sigma statistical technique to n samples instead of the step of taking the average of n recorded values. This technique is well - known to those skilled in the art and will not be described in detail here.

[0069] Advantageously, using this method, the switching commands t2 (and t4) on the second transistor T2 will only occur at times corresponding to the statistically longest value among the actual switching times of the first transistor T1 measured during n switchings in the previous cycle. Thus, using this method, it is advantageously avoided to initiate the switching command of the second transistor T2 before the first transistor T1 is actually switched.

[0070] Advantageously, with this variant of the method according to the invention, the switching losses only occur on the first transistor T1, allowing the second transistor T2 to be switched without switching losses, since the midpoint PM1 is already at the PH potential due to the switching of the first transistor T1.

[0071] As a variant, the method according to the invention is only carried out on the second transistor T2, and when transitioning from the high state to the low state and when transitioning from the low state to the high state, the second transistor T2 is always switched first.

[0072] In another embodiment, the invention proposes to switch the first transistor T1 and the second transistor T2 in the following order: the first transistor T1 is switched first when transitioning from the off state to the on state, and the second transistor T2 is switched first when transitioning from the on state to the off state. Thus, by virtue of the invention, the two transistors alternately suffer from switching losses, allowing for uniform aging of the transistors on the same cell.

[0073] In another variant of the implementation of the method according to the invention, instead of the first closing step E1, the second closing step E2, the third opening step E3, and the fourth opening step E4, when transitioning from the high state to the low state, first a first series of n_1 measurements of the actual switching time of the first transistor T1 is carried out during a fifth step E5. The first transistor T1 is the first transistor to be switched among the two transistors. The value n_1 is, for example, 100 samples. The measurement strategy is the same as discussed previously.

[0074] The invention then proposes that during a sixth step E6, when transitioning from the low state to the high state, a second series of n_2 measurements of the actual switching time of the first transistor T1 is carried out, and the second transistor T2 is in the closed state during each measurement of the actual switching time of the first transistor T1.

[0075] The method according to the invention then proposes that during a seventh step E7, when transitioning from the high state to the low state, a first series of p_1 measurements of the actual switching time of the second transistor T2 is carried out. The second transistor T2 is the first transistor to be switched among the two transistors. The value p_1 is, for example, 100 samples. The measurement strategy is the same as discussed previously.

[0076] The invention then proposes that during an eighth step E8, when transitioning from a low state to a high state, a second series of p_2 measurements of the actual switching time of a second transistor T2 are carried out, with a first transistor T1 being in a closed state during each measurement of the actual switching time of the second transistor T2.

[0077] During a ninth step E9), the method consists in saving in a memory the value of a first closing delay (Df_T1) of the first transistor, the value of a first opening delay (Do_T1) of the first transistor, the value of a first closing delay (Df_T2) of the second transistor, and the value of a first opening delay (Do_T2) of the second transistor. As a variant, n values are saved. As a variant, only the average value is saved.

[0078] At a tenth step E10), all steps E1) to E9) are carried out a determined number of times, for example 100 times. The method then proposes that at an eleventh step E11) and a twelfth step E12), all steps E1) to E10) are carried out a determined number of times, for example 100 times, allowing a relatively reliable representation of a possible drift of one of the transistors (T1) or (T2) to be obtained.

[0079] Thanks to the invention, it is cleverly proposed and possible to track the drift of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12 of a power factor correction circuit 21 in order to monitor the aging of said transistors. To this end, the invention proposes implementing the method, for example, each time the vehicle is started, allowing the evolution of the transistors to be tracked during the life of the vehicle.

[0080] The invention cleverly proposes saving the average value of the actual switching time for a transistor and tracking and processing the values thus calculated. The method for processing these values can be, for example, obtaining the drift of the average value of the actual switching time for said transistor when indicating a transition from an open state to a closed state that assumes the aging of at least one transistor (for example transistor T1).

[0081] In this case, the invention proposes generating an alarm signal for the driver, allowing a fault to be anticipated.

[0082] As a variant, the invention proposes, for example, no longer switching the first transistor T1 first in the case where a drift of the actual switching time of, for example, the first transistor T1 is observed, in order to protect it from switching losses. Thus, for example, in such a case, the second transistor T2 is switched first, and the first transistor T1 is switched second, allowing the conduction losses during the switching of the first transistor T1 to be limited to the greatest extent according to the strategy proposed above.

[0083] Advantageously, the switching time test can be performed only once per start of the electric vehicle 10, or once every M minutes, for example every 10 minutes.

[0084] Advantageously, in a case where the switching sequence of the transistors is modified but the first transistor continues to drift, the method then provides for deactivating the transistor, generating and executing an alarm signal to inform the vehicle user of an apparent fault.

Claims

1. A method for monitoring and managing the conduction loss of an electronic circuit, the electronic circuit comprising at least a first transistor (T1) and a second transistor (T2), the first transistor (T1) and the second transistor (T2) being coupled in parallel, the method comprising: · A first step E1), which consists in operating the first transistor (T1) so that it transitions to a closed-circuit state, and measuring a first closing delay (Df_T1) of the first transistor after the first transistor (T1) is operated in the closed-circuit state, · A second step E2), which consists in operating the second transistor (T2) so that it transitions to a closed-circuit state, the operation of the second transistor (T2) in the closed-circuit state occurring after a first determined duration TM1, · A third step E3), which consists in operating the first transistor (T1) so that it transitions to an open-circuit state, and measuring a first turn-off delay (Do_T1) of the first transistor after the first transistor (T1) is operated in the open-circuit state, · A fourth step E4), which consists in operating the second transistor (T2) so that it transitions to an open-circuit state, the operation of the second transistor (T2) in the open-circuit state occurring after a second determined duration TM2, · A fifth step E5), which consists in operating the second transistor (T2) so that it transitions to a closed-circuit state, and measuring a first closing delay (Df_T2) of the second transistor after the second transistor (T2) is operated in the closed-circuit state, · A sixth step E6), which consists in operating the first transistor (T1) so that it transitions to a closed-circuit state, the operation of the first transistor (T1) in the closed-circuit state occurring after a third determined duration TM3, · A seventh step E7), which consists in operating the second transistor (T2) so that it transitions to an open-circuit state, and measuring a first turn-off delay (Do_T2) of the second transistor after the second transistor (T2) is operated in the open-circuit state, · An eighth step E8), which consists in operating the first transistor (T1) so that it transitions to an open-circuit state, the operation of the first transistor (T1) in the open-circuit state occurring after a fourth determined duration TM4, · A ninth step E9), which consists in storing in a memory the value of the first closing delay (Df_T1) of the first transistor, the value of the first turn-off delay (Do_T1) of the first transistor, the value of the first closing delay (Df_T2) of the second transistor, and the value of the first turn-off delay (Do_T2) of the second transistor, · A tenth step E10), which consists in executing steps E1) to E9) at least n times, and · An eleventh step E11), which consists in performing an averaging of the n measured values of the first closing delay (Df_T1) of the first transistor, an averaging of the n measured values of the first turn-off delay (Do_T1) of the first transistor, an averaging of the n measured values of the first closing delay (Df_T2) of the second transistor, and an averaging of the n measured values of the first turn-off delay (Do_T2) of the second transistor, · The twelfth step E12) consists of performing steps E1) to E11) m times, and · The thirteenth step E13) consists of comparing m values obtained by averaging n values respectively, wherein when the result of at least one comparison of the m values drifts by p% from the average value, a software alarm is generated, and wherein when the result of the comparison of the m values obtained by averaging n values of the first closing delay (Df_T1) of the first transistor, or the result of the comparison of the m values obtained by averaging n values of the first opening delay (Do_T1) of the first transistor, or the result of the comparison of the m values obtained by averaging n values of the first closing delay (Df_T2) of the second transistor, or the result of the comparison of the m values obtained by averaging n values of the first opening delay (Do_T2) of the second transistor drifts by p%, then the transistor corresponding to the drifted value is activated only after the other transistor.

2. The method for monitoring and managing the conduction loss of an electronic circuit according to claim 1, wherein if the observed drift of the m values obtained by averaging n values of the transistor that is activated second only continues to drift similarly to the observed drift, for example, greater than p%, a software alarm is activated.

3. The method for monitoring and managing the conduction loss of an electronic circuit according to claim 2, wherein if the drift of the m values obtained by averaging n values of the transistor that is activated second only shows a drift less than p%, the corresponding transistor is reactivated first.

4. The method for monitoring and managing the conduction loss of an electronic circuit according to any one of claims 1 to 3, wherein the value of p% is equal to 10%.

5. The method for monitoring and managing the conduction loss of an electronic circuit according to claim 4, wherein if the drift of the m values obtained by averaging n values of the transistor that is activated second only shows a drift greater than p%, the transistor is deactivated.

6. The method for monitoring and managing the conduction loss of an electronic circuit according to any one of claims 1 to 5, wherein the processing function used is the three-sigma mathematical method.

7. The method for monitoring and managing the conduction loss of an electronic circuit according to any one of claims 1 to 6, wherein at least one of the two transistors is an IGBT transistor.

8. The method for monitoring and managing the conduction loss of an electronic circuit according to any one of claims 1 to 7, wherein at least one of the two transistors is a SiC / GaN transistor.

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