Three-dimensional memory device including isolated trench fill structures

Abstract

A three-dimensional memory device includes: a pair of alternating stacks of insulating layers and conductive layers laterally spaced apart from each other by lateral isolation trenches extending substantially along a first horizontal direction; a memory opening extending vertically through a respective one of the pair of alternating stacks; a memory opening filling structure in a corresponding one of the memory openings; and a lateral isolation trench fill structure including a peripheral spacer and a conductive fill structure wherein a first vertical cross-sectional view of the lateral isolation trench fill structure in a first vertical plane includes: an outer periphery of the peripheral spacer; the outer periphery comprises a horizontal top surface section located in a first horizontal plane; and an inner periphery of the peripheral spacer, the inner periphery being vertically spaced from and completely below the first horizontal plane.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of U.S. Non - provisional Application No. 18 / 471,896, entitled "THREE - DIMENSIONAL MEMORY DEVICE WITH ISOLATION TRENCH FILL STRUCTURE HAVING LATERALLY - UNDULATING SIDEWALLS AND METHOD OF MAKING THE SAME", filed on September 21, 2023, with the United States Patent and Trademark Office, the entire content of which is hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and more particularly to three - dimensional memory devices including isolation trench fill structures having laterally - undulating sidewalls and methods of making the same. Background Art

[0004] A three - dimensional vertical NAND string having one bit per cell is disclosed in the article by T. Endoh et al., entitled "Novel Ultra High Density Memory With A Stacked - Surrounding Gate Transistor (S - SGT) Structured Cell", Proceedings of the IEDM (2001), pages 33 - 36. Summary of the Invention

[0005] According to one aspect of the present disclosure, there is provided a three - dimensional memory device including: a pair of alternating stacks of insulating layers and conductive layers, the pair of alternating stacks being laterally spaced apart from each other by laterally - extending isolation trenches extending generally along a first horizontal direction; memory openings extending vertically through corresponding ones of the pair of alternating stacks; memory opening fill structures located in corresponding ones of the memory openings and including corresponding vertical semiconductor channels and corresponding vertical stacks of memory elements at levels of the conductive layers; and a laterally - extending isolation trench fill structure located in the laterally - extending isolation trenches and including peripheral spacers and a conductive fill structure. The laterally - extending isolation trench fill structure has a width modulation along a second horizontal direction perpendicular to the first horizontal direction at levels of both the insulating layer and the conductive layer, the width modulation varying with a lateral distance along the first horizontal direction.

[0006] According to another aspect of the present disclosure, a method of forming a three-dimensional memory device is provided. The method includes: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer over a substrate; forming a memory opening through the vertical alternating sequence; forming a memory opening filling structure in the memory opening, wherein each memory opening filling structure in the memory opening filling structure includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; forming a lateral isolation trench through the vertical alternating sequence, wherein the lateral isolation trench has a width modulation in a second horizontal direction perpendicular to a first horizontal direction at levels of both the insulating layer and the sacrificial material layer, and the width modulation varies with a lateral distance along the first horizontal direction; replacing a remaining portion of the continuous sacrificial material layer with a conductive layer to form a pair of alternating stacks of the insulating layer and the conductive layer on opposite sides of the lateral isolation trench; and forming a lateral isolation trench filling structure in the lateral isolation trench, wherein the lateral isolation trench filling structure includes a peripheral spacer and a conductive filling structure formed in the peripheral spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 FIG. 8 is a schematic vertical cross-sectional view of a first exemplary structure for forming a memory die after forming an alternating stack of an insulating layer and a sacrificial material layer over a carrier substrate according to a first embodiment of the present disclosure.

[0008] Figure 2 FIG. 12 is a schematic vertical cross-sectional view of a first exemplary structure after forming a stepped surface and a stepped dielectric material portion according to a first embodiment of the present disclosure.

[0009] Figure 3A FIG. 16 is a schematic vertical cross-sectional view of a first exemplary structure after forming a memory opening and a support opening according to a first embodiment of the present disclosure. Figure 3B FIG. 18 is Figure 3A a top view of the first exemplary structure of FIG. 18. The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of FIG. 18. Figure 3A FIG. 22 is

[0010] Figure 4 FIG. 26 is a vertical cross-sectional view of a first exemplary structure after forming a sacrificial opening filling structure according to a first embodiment of the present disclosure.

[0011] Figure 5 FIG. 30 is a vertical cross-sectional view of a first exemplary structure after replacing a sacrificial support opening filling structure with a support pillar structure according to a first embodiment of the present disclosure.

[0012] Figure 6A vertical cross-sectional view of a first exemplary structure after removing a sacrificial memory opening filling structure from a memory opening according to a first embodiment of the present disclosure.

[0013] Figures 7A to 7D A sequential vertical cross-sectional view of a memory opening during the formation of a memory opening filling structure according to a first embodiment of the present disclosure.

[0014] Figure 8A A vertical cross-sectional view of a first exemplary structure after forming a memory opening filling structure according to a first embodiment of the present disclosure. Figure 8B Is Figure 8A A top view of the first exemplary structure. The vertical plane A-A' is Figure 8A The cutting plane of the vertical cross-sectional view.

[0015] Figure 9A A vertical cross-sectional view of a first exemplary structure after forming a lateral isolation trench according to a first embodiment of the present disclosure. Figure 9B Is Figure 9A A top view of the first exemplary structure.

[0016] Figure 10A A vertical cross-sectional view of a first exemplary structure after forming a laterally extending cavity according to a first embodiment of the present disclosure.

[0017] Figure 10B Is around Figure 10A A vertical cross-sectional view of a region of a memory opening of the first exemplary structure.

[0018] Figure 11 , Figure 12 And Figure 13 Sequential vertical cross-sectional views of a region around a memory opening during the formation of a conductive layer according to a first embodiment of the present disclosure.

[0019] Figure 14 A vertical cross-sectional view of a first exemplary structure after forming a conductive layer according to a first embodiment of the present disclosure.

[0020] Figure 15A A vertical cross-sectional view of a first exemplary structure after forming peripheral spacers in a lateral isolation trench according to a first embodiment of the present disclosure. Figure 15B Is Figure 15A A top view of the first exemplary structure. The vertical plane A-A' is Figure 15A The cutting plane of the vertical cross-sectional view. Figure 15C Is along Figure 15B A vertical cross-sectional view of a first exemplary structure along the vertical plane C-C' of Figure 15D Is along Figure 15BVertical cross-sectional view of a first exemplary structure of the vertical plane D-D'.

[0021] Figure 16A Is a vertical cross-sectional view of a first exemplary structure after forming a conductive filling structure in a lateral isolation trench according to a first embodiment of the present disclosure. Figure 16B Is Figure 16A Top view of the first exemplary structure. The vertical plane A-A' is Figure 16A The cutting plane of the vertical cross-sectional view. Figure 16C Is along Figure 16B Vertical cross-sectional view of a first exemplary structure of the vertical plane C-C'. Figure 16D Is along Figure 16B Vertical cross-sectional view of a first exemplary structure of the vertical plane D-D'.

[0022] Figure 17A Is a vertical cross-sectional view of a first exemplary structure after forming a contact via structure according to a first embodiment of the present disclosure. Figure 17B Is Figure 17A Top view of the first exemplary structure. The vertical plane A-A' is Figure 17A The cutting plane of the vertical cross-sectional view.

[0023] Figure 18A Is a vertical cross-sectional view of a first exemplary structure after forming a bit line and a bit line level metal line according to a first embodiment of the present disclosure. Figure 18B Is Figure 18A Top view of the first exemplary structure. The vertical plane A-A' is Figure 18A The cutting plane of the vertical cross-sectional view.

[0024] Figure 19 Is a vertical cross-sectional view of a first exemplary structure after forming a memory die according to a first embodiment of the present disclosure.

[0025] Figure 20 Is a vertical cross-sectional view of a logic die according to a first embodiment of the present disclosure.

[0026] Figure 21 Is a vertical cross-sectional view of a first exemplary structure after forming a bonding assembly of a memory die and a logic die according to a first embodiment of the present disclosure.

[0027] Figure 22 Is a vertical cross-sectional view of a first exemplary structure after removing a carrier substrate from a memory die according to a first embodiment of the present disclosure.

[0028] Figure 23 Is a vertical cross-sectional view of a first exemplary structure after removing the bottommost insulating layer according to a first embodiment of the present disclosure.

[0029] Figure 24 is a vertical cross-sectional view of a first exemplary structure after removing a bottom portion of a memory film according to a first embodiment of the present disclosure.

[0030] Figure 25 is a vertical cross-sectional view of a first exemplary structure after forming a source layer, a back dielectric layer, and a back contact pad according to a first embodiment of the present disclosure.

[0031] Figure 26 is a vertical cross-sectional view of an alternative configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0032] Figure 27 is a schematic vertical cross-sectional view of a second exemplary structure for forming a memory die after forming an alternating stack of an insulating layer and a sacrificial material layer over a substrate according to a second embodiment of the present disclosure.

[0033] Figure 28 is a schematic vertical cross-sectional view of a second exemplary structure after forming a stepped surface and a stepped dielectric material portion according to a second embodiment of the present disclosure.

[0034] Figure 29A is a schematic vertical cross-sectional view of a second exemplary structure after forming a memory opening and a support opening according to a second embodiment of the present disclosure. Figure 29B is Figure 29A a top view of a second exemplary structure. The vertical plane A-A’ is Figure 29A the cutting plane of the vertical cross-sectional view of

[0035] Figure 30 is a vertical cross-sectional view of a second exemplary structure after forming a sacrificial opening filling structure according to a second embodiment of the present disclosure.

[0036] Figure 31A is a vertical cross-sectional view of a second exemplary structure after forming a lateral isolation trench according to a second embodiment of the present disclosure. Figure 31B is Figure 31A a top view of a second exemplary structure. The vertical plane A-A’ is Figure 31A the cutting plane of the vertical cross-sectional view of

[0037] Figure 32 is a vertical cross-sectional view of an exemplary structure after forming a laterally extending cavity according to a second embodiment of the present disclosure.

[0038] Figure 33 is a vertical cross-sectional view of a second exemplary structure after forming a conductive layer according to a second embodiment of the present disclosure.

[0039] Figure 34A is a vertical cross-sectional view of a second exemplary structure after removal of a sacrificial opening fill structure according to a second embodiment of the present disclosure. Figure 34B is Figure 34A a top view of the second exemplary structure of Figure 34A The vertical plane A-A' is the cutting plane of the vertical cross-sectional view of Figure 34C is along Figure 34B the vertical cross-sectional view of the second exemplary structure along the vertical plane C-C' of Figure 34D is along Figure 34B the vertical cross-sectional view of the second exemplary structure along the vertical plane D-D' of

[0040] Figure 35A is a vertical cross-sectional view of the region around the memory opening and the lateral isolation trench of the second exemplary structure after depositing a barrier dielectric layer, a memory material layer, a dielectric liner, a semiconductor channel material layer, and a dielectric core layer in the memory opening, the support opening, and the lateral isolation trench according to a second embodiment of the present disclosure. Figure 15B is Figure 15B another vertical cross-sectional view of the second exemplary structure of

[0041] Figure 36A is a vertical cross-sectional view of the region around the memory opening and the lateral isolation trench of the second exemplary structure after depositing a conductive fill material layer in the lateral isolation trench according to a second embodiment of the present disclosure. Figure 36B is Figure 36B another vertical cross-sectional view of the second exemplary structure of

[0042] Figure 37A is a vertical cross-sectional view of the region around the memory opening and the lateral isolation trench of the second exemplary structure after performing a planarization process according to a second embodiment of the present disclosure. Figure 37B is Figure 37B another vertical cross-sectional view of the second exemplary structure of

[0043] Figure 38A is a vertical cross-sectional view of the region around the memory opening and the lateral isolation trench of the second exemplary structure after performing a recess etching process according to a second embodiment of the present disclosure. Figure 38B is Figure 38B another vertical cross-sectional view of the second exemplary structure of

[0044] Figure 39A is a vertical cross-sectional view of the second exemplary structure after forming a drain structure according to a second embodiment of the present disclosure. Figure 39B is Figure 39A a top view of the second exemplary structure of Figure 39AThe cutting plane of the vertical sectional view. Figure 39C is the vertical sectional view of the second exemplary structure along the Figure 39B vertical plane C-C' of. Figure 39D is the vertical sectional view of the second exemplary structure along the Figure 39B vertical plane D-D' of.

[0045] Figure 40A is the vertical sectional view of the second exemplary structure after forming the contact via structure according to the second embodiment of the present disclosure. Figure 40B is Figure 40A the top view of the second exemplary structure of. The vertical plane A-A' is Figure 40A the cutting plane of the vertical sectional view of.

[0046] Figure 41 is the vertical sectional view of the second exemplary structure after forming the memory die according to the second embodiment of the present disclosure.

[0047] Figure 42 is the vertical sectional view of the second exemplary structure after forming the bonding assembly of the memory die and the logic die according to the second embodiment of the present disclosure.

[0048] Figure 43 is the vertical sectional view of the second exemplary structure after removing the carrier substrate from the memory die according to the second embodiment of the present disclosure.

[0049] Figure 44 is the vertical sectional view of the second exemplary structure after forming the source layer, the back dielectric layer, and the back contact pad according to the second embodiment of the present disclosure.

[0050] Figure 45 is the vertical sectional view of an alternative configuration of the second exemplary structure according to the second embodiment of the present disclosure. Detailed Description

[0051] As discussed above, the present disclosure relates to a three-dimensional memory device including an isolation trench fill structure having laterally undulating sidewalls and a method of manufacturing the same, and various aspects thereof are described below.

[0052] The drawings are not drawn to scale. Multiple instances of an element may be replicated in the case of illustrating a single instance of the element, unless otherwise explicitly described or clearly indicated that there is no replication of the element. Ordinal numbers such as "first", "second", and "third" are only used to identify similar elements, and different ordinal numbers may be used in the specification and claims of the present disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0053] Like reference numerals designate like or similar elements. Unless otherwise specified, elements having the same reference numeral are considered to have the same composition and the same function. Unless otherwise specified, "contact" between elements means direct contact providing an edge or surface shared by the elements. If two or more elements do not contact each other directly or do not contact each other directly, the two elements are "separated" from each other or are "separated" from each other. As used herein, an element located "on" a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, an element is "directly" located "on" a second element if there is physical contact between the surface of the element and the surface of the second element. As used herein, an element is "electrically connected to" a second element if there is an electrical conduction path composed of at least one conductive material between the element and the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in shape or composition of at least one of its components.

[0054] As used herein, a "layer" refers to a portion of a material including a region having a thickness. The layer may extend over the entire underlying or overlying structure, or its extent may be less than the extent of the underlying or overlying structure. Further, a layer may be a region of a uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top surface and the bottom surface of a continuous structure or at the top surface and the bottom surface. The layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above it, and / or below it.

[0055] Generally, a semiconductor die or a semiconductor package may include memory chips. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (usually one or two). Although there are some limitations, the same, concurrent operations can be performed on each plane. Each plane contains a plurality of blocks, which are the smallest units that can be erased in a single erase operation. Each block contains a plurality of pages, which are the smallest units that are programmable, i.e., the smallest units on which a read operation can be performed.

[0056] As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 5 S / m. As used herein, a "semiconductor material" refers to a material having a conductivity in the range of 1.0×10 -5Materials in the range of 1.0 S / m to 1.0 S / m and capable of producing a doped material with a conductivity in the range of 1.0 S / m to 1.0×10 7 S / m when appropriately doped with an electrical dopant. As used herein, an "electrical dopant" is a p-type dopant that adds holes to the valence band within the band structure or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, a "conductive material" is a material having a conductivity greater than 1.0×10 5 S / m. As used herein, an "insulating material" or "dielectric material" is a material having a conductivity less than 1.0×10 -5 S / m. As used herein, a "heavily doped semiconductor material" is a semiconductor material doped with an electrical dopant at a high enough atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a conductivity greater than 1.0×10 5 S / m. A "doped semiconductor material" can be a heavily doped semiconductor material or can be a semiconductor material including an electrical dopant (i.e., a p-type dopant and / or an n-type dopant), the concentration of these electrical dopants providing a conductivity in the range of 1.0×10 -5 S / m to 1.0×10 7 S / m. An "intrinsic semiconductor material" is a semiconductor material not doped with an electrical dopant. Thus, a semiconductor material can be semiconducting or conductive and can be an intrinsic semiconductor material or a doped semiconductor material. A doped semiconductor material can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, a "metallic material" is a conductive material containing at least one metallic element. All conductivity measurements are made under standard conditions.

[0057] Reference Figure 1 , illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which can be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 can include a commercially available silicon wafer. Alternatively, the carrier substrate 9 can include any material that can be selectively removed relative to the material of the insulating layer 32 and the subsequent dielectric material portion to be formed.

[0058] The alternating stack of the first material layer and the second material layer may be formed above the carrier substrate 9. In the alternating stack, the first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, the alternating stack (32, 42) of the insulating layer 32 and the sacrificial material layer 42 may be formed above the substrate 9. The insulating layer 32 includes an insulating material such as undoped silicate glass or doped silicate glass, and the sacrificial material layer 42 includes a sacrificial material such as silicon nitride or silicon-germanium alloy. In one embodiment, the insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and the sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer. The alternating stack (32, 42) may include multiple repetitions of a unit layer stack including the insulating layer 32 and the sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger numbers of repetitions may also be employed. Hereinafter, the topmost insulating layer in the insulating layer 32 is referred to as the topmost insulating layer 32T. The bottommost insulating layer in the insulating layer 32 is the insulating layer 32 closest to the carrier substrate 9, which is referred to herein as the bottommost insulating layer 32B. Each insulating layer in the insulating layer 32 other than the topmost insulating layer 32 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses may also be employed. Each sacrificial material layer in the sacrificial material layer 42 may have a thickness in the range of 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses may also be employed. In one embodiment, the topmost insulating layer 32 may have a thickness approximately half that of the other insulating layers 32.

[0059] The first exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will be subsequently formed in the memory array region, and in which a layer contact via structure for contacting a contact word line will be subsequently formed in the contact region. The insulating layer 32 extends continuously across the memory array region 100 and the contact region 300 without being patterned, and may be referred to as the continuous insulating layer 32. The sacrificial material layer 42 extends continuously across the memory array region 100 and the contact region 300 without being patterned, and may be referred to as the continuous sacrificial material layer 42. Thus, a vertical alternating sequence of the continuous insulating layer 32 and the continuous sacrificial material layer 42 can be formed.

[0060] Reference Figure 2, a stepped surface is formed in the contact region 300. As used herein, a "stepped surface" refers to a set of surfaces that includes at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and portions of the alternating stacks (32, 42) are removed from the stepped cavity by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface.

[0061] The stepped cavity can have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise with the vertical distance from the top surface of the substrate. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. The set of processing steps can include, for example, a first type of etching process and a second type of etching process, where the first type of etching process vertically increases the depth of the cavity by one or more levels, and the second type of etching process laterally expands the region vertically etched in the subsequent first type of etching process. As used herein, a "level" of a structure including a plurality of alternating ones is defined as the relative position of a pair of a first material layer and a second material layer within the structure.

[0062] Each sacrificial material layer 42 within the alternating stacks (32, 42) except for the topmost sacrificial material layer 42 extends further laterally than any overlying sacrificial material layer 42 within the alternating stacks (32, 42) in the mesa region. The stepped surface of the alternating stacks (32, 42) continuously extends from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stacks (32, 42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stacks (32, 42).

[0063] A stepped dielectric material portion 65 (i.e., an insulating fill material portion) can be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. The excess portion of the deposited dielectric material can be removed, for example, by chemical mechanical planarization (CMP) above the top surface of the topmost insulating layer 32T. The remaining portion of the deposited dielectric material that fills the stepped cavity constitutes the stepped dielectric material portion 65, which can be an inverse stepped dielectric material portion. As used herein, an "inverse stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with the vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the stepped dielectric material portion 65, the silicon oxide of the stepped dielectric material portion 65 can or can not be doped with dopants such as B, P, and / or F.

[0064] Optionally, a drain select level isolation structure (not shown) may be formed through the topmost insulating layer 32T and a subset of the sacrificial material layer 42 at the drain select level. For example, the drain select level isolation structure may be formed by forming a drain select level lateral isolation trench and filling the drain select level lateral isolation trench with a dielectric material such as silicon oxide. The excess portion of the dielectric material may be removed from above the top surface of the topmost insulating layer 32T.

[0065] Reference Figure 3A and Figure 3B , an etch mask layer (not shown) may be formed over the alternating stack (32, 42) and may be lithographically patterned to form openings therein. An anisotropic etch process may be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42) to form memory openings 49 and support openings 19. The memory openings 49 may be formed through the alternating stack (32, 42) in the memory array region 100. Each memory opening in the memory openings 49 may vertically extend through the alternating stack (32, 42). The support openings 19 may be formed through the alternating stack (32, 42) and a stepped dielectric material portion 65 in the contact region 300. In one embodiment, the support openings 19 may have the same depth as the memory openings 49.

[0066] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1. The memory openings 49 may include rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. A plurality of clusters of memory openings 49 may be formed in the memory array region 100, each cluster including a corresponding two-dimensional periodic array of memory openings 49. The clusters of memory openings 49 may be laterally spaced apart along the second horizontal direction hd2 by a strip region that does not contain any openings (49, 19). Similarly, a plurality of clusters of support openings 19 may be formed in the contact region such that the clusters of support openings 19 may be laterally spaced apart along the second horizontal direction hd2 by a strip region that does not contain any openings (49, 19).

[0067] Reference Figure 4 , a sacrificial fill material such as amorphous carbon or diamond-like carbon may be deposited in the memory openings 49 and the support openings 19 by a conformal deposition process. The excess portion of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T by a planarization process such as a recess etch process or a chemical mechanical polishing process. The remaining portion of the sacrificial fill material that fills the memory openings 49 constitutes a sacrificial memory opening fill structure 47. The remaining portion of the sacrificial fill material that fills the support openings 19 constitutes a sacrificial support opening fill structure 17.

[0068] ReferenceFigure 5 , a mask layer (not shown) may be applied over the first exemplary structure and may be lithographically patterned to cover the memory array region 100 without covering the contact region 300. The mask layer may include a dielectric material such as silicon oxide or silicon nitride and may have a thickness in the range of 5 nm to 50 nm, although smaller and larger thicknesses may also be employed. The sacrificial support opening fill structure 17 may be selectively removed relative to the materials of the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)) and the substrate 9 by performing a selective removal process such as an ashing process. A cavity is formed in the volume of the support opening 19. A dielectric fill material such as silicon nitride may be deposited in the cavity. The excess of the dielectric fill material above the horizontal plane covering the top surface of the stepped dielectric material layer 65 may be removed by a planarization process such as a recess etch process or a chemical mechanical polishing process. The remaining portion of the dielectric fill material filling the support opening 19 constitutes the support pillar structure 20. Subsequently, the mask layer may be removed, for example, by a selective etching process.

[0069] Reference Figure 6 , the sacrificial memory opening fill structure 47 may be selectively removed relative to the materials of the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)) and the substrate 9 by performing a selective removal process such as an ashing process. A cavity is formed in the volume of the memory opening 49.

[0070] Figures 7A to 7D is a sequential vertical cross-sectional view of the memory opening 49 during the formation of the memory opening fill structure 58 according to an embodiment of the present disclosure. The memory opening fill structure 58 may include NAND strings.

[0071] In an alternative embodiment, instead of forming the dielectric support pillar structure 20 described above, dummy memory opening fill structures may be formed in the support openings 19 simultaneously and during the same process step as the memory opening fill structure 58 is formed in the memory openings. In an alternative embodiment, the dummy memory opening fill structures serve as the support pillar structure 20.

[0072] Reference Figure 7A , illustrates the memory opening 49 after the processing steps of Figure 6 . Reference Figure 7B, a layer stack including a memory material layer 54 can be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. The memory material layer 54 includes a memory material, that is, a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride), a ferroelectric material, a phase change memory material, or any other memory material that can store data bits by inducing a change in resistivity, ferroelectric polarization, or any other measurable physical property. In the case where the memory material layer 54 includes a charge storage material, the optional dielectric liner 56 may include a tunneling dielectric layer.

[0073] The semiconductor channel material layer 60L can be deposited on the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, the semiconductor channel material layer 60L can have a doping of a first conductivity type, which can be p-type or n-type. In one embodiment, the first semiconductor material includes a first doped silicon material having a doping of a first conductivity type. In an exemplary example, the atomic concentration of the dopant of the first conductivity type in the semiconductor channel material layer 60L can be in the range of 1.0×10 13 / cm 3 to 3.0×10 17 / cm 3 such as 1.0×10 14 / cm 3 to 3.0×10 16 / cm 3 , but smaller and larger atomic concentrations can also be employed. A dielectric core layer 62L including a dielectric fill material can be deposited in the remaining volume of the memory opening 49 and above the alternating stack (32, 42).

[0074] Refer to Figure 7C , the dielectric core layer 62L can be vertically recessed such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0075] Refer to Figure 7D , a doped semiconductor material having a doping of a second conductivity type can be deposited in each recessed area above the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3within a range, but smaller or larger dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0076] Excess portions of the deposited semiconductor material doped with the second conductivity type and horizontal portions of the semiconductor channel material layer 60L may be removed, for example, by chemical mechanical planarization (CMP) or recess etching processes above a horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the doped semiconductor material with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which is doped with the first conductivity type) constitutes a vertical semiconductor channel 60.

[0077] Each portion of the layer stack including the memory material layer 54 retained in the respective memory opening 49 constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric liner 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, and the respective vertical stack of memory elements may include a portion of the respective memory material layer 54 of the memory film 50 at the level of the sacrificial material layer 42, or generally at the level of a spacer material layer that can subsequently be at least partially replaced with a conductive layer.

[0078] Reference Figure 8A and Figure 8B , illustrates a first exemplary structure after forming the memory opening fill structure 58 within the memory opening 49. Each memory opening fill structure within the memory opening fill structure 58 may include a memory film 50 and a vertical semiconductor channel 60. Each memory opening fill structure within the memory opening fill structure 58 includes a respective vertical stack of memory elements, and the respective vertical stack of memory elements may include a portion of the respective memory material layer 54 of the memory film 50 at the level of the sacrificial material layer 42.

[0079] Reference Figure 9A and Figure 9B , a dielectric material such as undoped silicate glass or doped silicate glass may be deposited over the alternating stack (32, 42) to form a contact level dielectric layer 80. The thickness of the contact level dielectric layer 80 may be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses may also be employed.

[0080] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be lithographically patterned to form various discrete openings therein. The openings in the photoresist layer overlie regions between proximate clusters of the memory opening fill structures 58 (e.g., between adjacent memory block regions).

[0081] An anisotropic etching process may be performed to transfer the pattern of the discrete openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stack (32, 42) (i.e., the vertical alternating sequence (32, 42)), and the stepped dielectric material portion 65, and optionally into the substrate 9.

[0082] Then, by performing at least one isotropic etch, the discrete openings extending through the contact-level dielectric layer 80, the alternating stack (32, 42), and the stepped dielectric material portion 65 expand at the levels of the insulating layer 32 and the sacrificial material layer 42. In one embodiment, a sequence of two isotropic etches may be performed to expand the discrete openings. During the first isotropic etch, hydrofluoric acid is provided into the discrete openings to recess the silicon oxide insulating layer 32. During the second isotropic etch, hot phosphoric acid is provided into the discrete openings to recess the silicon nitride sacrificial material layer 42. In an alternative embodiment, the order of the steps of the first isotropic etch and the second isotropic etch may be reversed.

[0083] Each of the expanded discrete openings in the expanded discrete openings merges with at least one adjacent discrete opening at the levels of the insulating layer 32 and the sacrificial material layer 42 to form a continuous lateral isolation trench 79. The continuous lateral isolation trench 79 extends through the alternating stack (32, 42) and the stepped dielectric material portion 65. The lateral isolation trench 79 extends vertically through each layer within the alternating stack (32, 42) and optionally into an upper portion of the top portion of the substrate 9. The lateral isolation trench 79 extends laterally along a first horizontal direction hd1 (e.g., the word line direction). Each of the lateral isolation trenches 79 in the lateral isolation trench 79 may include a respective pair of laterally undulating longitudinal sidewalls that generally extend along the first horizontal direction hd1, have a respective width modulation along a second horizontal direction hd2, and extend vertically from at least the bottom sacrificial material layer 42 to the top surface of the contact layer dielectric layer 80. In one embodiment, the substrate 9 may be physically exposed beneath each of the lateral isolation trenches 79.

[0084] In one embodiment, the lateral isolation trench 79 may have a corresponding vertical cross-sectional profile including a kink line 79I at which a tapered surface section of a continuously extending sidewall abuts an inversely tapered surface section of a continuously extending sidewall. As used herein, a tapered surface section refers to a surface section where the lateral dimension of the volume of an element increases with the vertical distance from the underlying substrate, and an inversely tapered surface section refers to a surface section where the lateral dimension of the volume of an element decreases with the vertical distance from the underlying substrate. Generally, the sidewalls of the lateral isolation trench 79 may optionally have a gradually changing slope and may optionally have a curved vertical cross-sectional profile, with the maximum width located at the kink line 79I. The lateral isolation trench 79 may have a maximum lateral width at the kink line 79I in the range of 120 nm to 500 nm, such as 200 nm to 300 nm, along the second horizontal direction hd2, although smaller and larger lateral dimensions may be employed. Each kink line may extend generally laterally along the first horizontal direction hd1 and may have a corresponding periodic lateral undulation along the second horizontal direction hd2.

[0085] Generally speaking, each lateral isolation trench 79 may include a pair of longitudinal sidewalls extending generally along the first horizontal direction hd1. The vertical cross-sectional profile of the lateral isolation trench 79 in a vertical plane perpendicular to the first horizontal direction hd1 has a variable width that increases with the vertical distance from a horizontal plane including the bottommost surface of the vertical alternating sequence (32, 42) in the lower portion of the vertical alternating sequence (32, 42) and decreases with the vertical distance from the horizontal plane in the upper portion of the vertical alternating sequence (32, 42). In one embodiment, each lateral isolation trench 79 has a width modulation along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1 that varies with the lateral distance along the first horizontal direction hd1.

[0086] In Figure 9B In one embodiment shown, each lateral isolation trench 79 includes a periodic lateral alternating sequence of a neck region 79N having a minimum width along the second horizontal direction hd2 and a bulge region 79B having a maximum width along the second horizontal direction hd2. The distance along the first horizontal direction hd1 between adjacent neck regions 79N or between adjacent bulge regions 79B includes a pitch p. In one embodiment, each lateral isolation trench 79 includes a pair of laterally undulating longitudinal sidewalls, and each laterally undulating longitudinal sidewall of the pair of laterally undulating longitudinal sidewalls includes a set of horizontally protruding and vertically tapered surface sections that abut each other at the edges.

[0087] Reference Figure 10A and Figure 10B, an isotropic etching process can be performed to selectively remove the sacrificial material layer 42 relative to the insulating layer 32, the memory opening filling structure 58, and optionally the substrate 9. A laterally extending cavity 43 can be formed in the volume where the sacrificial material layer 42 is removed. Sidewall surface segments of the memory opening filling structure 58 can be physically exposed to the laterally extending cavity 43. In an illustrative example, if the sacrificial material layer 42 includes silicon nitride, the isotropic etching process can include a wet etching process using hot phosphoric acid.

[0088] Reference Figure 11 , an external barrier dielectric layer 44 can optionally be formed in the laterally extending cavity 43 by a conformal deposition process. The external barrier dielectric layer 44 can include a metal oxide layer, such as aluminum oxide.

[0089] Reference Figure 12 , a metal barrier material can be conformally deposited in the laterally extending cavity 43. The metal barrier material can include, for example, TiN, TaN, WN, MoN, TiC, TaC, WC, or a combination thereof.

[0090] Reference Figure 13 and Figure 14 , a metal filling material can be conformally deposited in the remaining volume of the laterally extending cavity 43. The metal filling material can include, for example, Ti, Ta, Mo, Co, Ru, W, Cu, other transition metals, and / or their alloys or layer stacks. The excess portion of the deposition of at least one conductive material in the lateral isolation trench 79 or above the topmost insulating layer 32T can be removed by performing an etch-back process, which can include an isotropic etching process and / or an anisotropic etching process. Each remaining portion of the corresponding laterally extending cavity in the laterally extending cavity 43 filled with at least one conductive material constitutes a conductive layer 46. An alternating stack of the insulating layer 32 and the conductive layer 46 can be formed between each pair of adjacent lateral isolation trenches 79 above the carrier substrate 9. A plurality of alternating stacks of the insulating layer 32 and the conductive layer 46 can be laterally spaced apart from each other by the lateral isolation trenches 79. The conductive layer 46 includes word lines and select gate electrodes.

[0091] In one embodiment, at least one of the lateral isolation trenches 79 can include a corresponding pair of laterally undulating longitudinal sidewalls formed by both the insulating layer 32 and the conductive layer 46. In one embodiment, each of the laterally undulating longitudinal sidewalls of the pair of laterally undulating longitudinal sidewalls includes a set of horizontal protrusions and vertically tapered surface segments that are adjacent to each other at the edges.

[0092] Multiple alternating stacks (32, 46) of an insulating layer 32 and a conductive layer 46 are laterally spaced apart from each other by lateral isolation trenches 79. Memory openings 49 extend vertically through corresponding stacks in the alternating stacks (32, 46). A memory opening fill structure 58 may be located in a corresponding one of the memory openings 49. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical semiconductor channel 60 and a corresponding vertical stack (e.g., a portion of the memory film 50) of memory elements at a level of the conductive layer 46.

[0093] Reference Figures 15A to 15D , an insulating material may be conformally deposited in the lateral isolation trenches 79 to form an insulating spacer material layer 74L. The insulating spacer material layer 74L includes an insulating material such as undoped silicate glass (e.g., silicon oxide) or doped silicate glass. The insulating spacer material layer 74L may be deposited by a conformal deposition process such as a low-pressure chemical vapor deposition process. In one embodiment, at least one of the lateral isolation trenches 79 may include N neck regions 79N and (N + 1) protruding regions 79B that are laterally staggered with each other along a first horizontal direction hd1. For example, N may be an integer in the range of 2 3 to 2 14 such as 2 6 to 2 10 but smaller and larger numbers may also be employed.

[0094] In one embodiment, the thickness of the insulating spacer material layer 74L may be greater than half of the width of each neck region 79N in a horizontal plane including the top surface of the contact-level dielectric layer 80, less than half of the width of each neck region 79N at the height of the turning line 79I, and less than half of the width of each protruding region 79B in a horizontal plane including the top surface of the contact-level dielectric layer 80. In this case, each portion of the insulating spacer material layer 74L located within a corresponding lateral isolation trench 79 may include N laterally extending tunnels 77T that extend laterally along the first horizontal direction hd1, as Figure 15D shown. The tunnels 77T include portions of the remaining unfilled voids 77 of the corresponding lateral isolation trench 79 that are embedded in portions of the filled neck regions 79N of the insulating spacer material layer 74L. Vertical seams 74S are insulating spacer material layers 74L that may be located above each corresponding tunnel 77T in the neck region 79N, as Figure 15D shown. In addition, each portion of the insulating spacer material layer 74L located within a corresponding lateral isolation trench 79 may include (N + 1) vertically extending portions that are adjacent to and staggered with N horizontally extending portions of the corresponding portion of the insulating spacer material layer 74L.

[0095] Reference Figures 16A to 16D, a conductive filler material can be conformally deposited in the remaining volume of the void 77 located in the lateral isolation trench 79. In one embodiment, the conductive filler material can include a conductive metal nitride material or a conductive metal material that counteracts the stress applied by the conductive layer 46 on the substrate 9 and / or can consist essentially of the conductive metal nitride material or the conductive metal material. This reduces the warping of the substrate 9 and thus improves the properties of the memory device located above the substrate 9. In one embodiment, the conductive metal can include titanium, and the conductive metal nitride material can include titanium nitride. The conductive filler material can be formed with an edge seal filler in the cutout region above the substrate 9.

[0096] Portions of the conductive filler material and the insulating spacer material layer 74L can be removed from above a horizontal plane including the top surface of the contact dielectric layer 80 by performing a planarization process such as a chemical mechanical polishing process. Each remaining portion of the conductive filler material retained in the respective lateral isolation trench 79 constitutes a conductive fill structure 76. Each remaining portion of the insulating spacer material layer 74L constitutes an insulating spacer, which is referred to herein as a peripheral spacer 74. Each adjacent combination of the conductive fill structure 76 and the peripheral spacer 74 constitutes a fill structure that fills the respective lateral isolation trench 79, and is referred to herein as a lateral isolation trench fill structure (74, 76). Each lateral isolation trench fill structure (74, 76) can be located in the lateral isolation trench 79 and can include a peripheral spacer 74 and a conductive fill structure 76.

[0097] In Figure 16A and Figure 16C In one embodiment shown, the conductive fill structure 76 can partially fill the void 77 that extends through the peripheral spacer 74 in the protruding region 79B. Thus, the embedded air gap 75 can be located in the conductive fill structure 76 in the protruding region 79B. Each air gap 75 is surrounded by the conductive fill structure 76 on all sides. In Figure 16D In one embodiment shown, the conductive fill structure 76 fills the tunnel 77T that extends through the peripheral spacer 74 in the neck region 79N.

[0098] A first vertical cross-sectional view of the lateral isolation trench fill structure (74, 76) located in the neck region 79N (e.g., in a first vertical plane perpendicular to the first horizontal direction hd1) such as Figure 16DThe view of ) may include: an outer perimeter OP of the peripheral spacer 74, the outer perimeter OP including a horizontal top surface section located in a first horizontal plane HP1; and an inner perimeter IP of the peripheral spacer 74, the inner perimeter IP being vertically spaced from the first horizontal plane HP1 and being entirely located below the first horizontal plane. In one embodiment, the horizontal top surface section of the outer perimeter OP of the peripheral spacer 74 is connected to the inner perimeter IP of the peripheral spacer 74 by a vertically extending seam 74S, at which two vertical surfaces of the peripheral spacer 74 are in direct contact with each other.

[0099] In Figure 16D In one embodiment as shown, the outer perimeter OP of the peripheral spacer 74 includes a pair of tapered upper sidewall sections that abut respective ends of the horizontal top surface section of the peripheral spacer 74. The lateral spacing between the pair of tapered upper sidewall sections decreases with the vertical distance from a second horizontal plane HP2 corresponding to the transition line 79I. In one embodiment, the outer perimeter OP of the peripheral spacer 74 includes a pair of tapered lower sidewall sections underlying the pair of tapered upper sidewall sections of the peripheral spacer 74, and the lateral spacing between the pair of tapered lower sidewall sections increases with the vertical distance from the second horizontal plane HP2. In one embodiment, in a first vertical cross-sectional view, the conductive fill structure 76 fills the entire area within the inner perimeter IP of the peripheral spacer 74 in the neck region 79N.

[0100] In one embodiment, at least one of the lateral isolation trench fill structures (74, 76) has a width modulation along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1, the width modulation varying with the lateral distance along the first horizontal direction hd1. In one embodiment, the lateral isolation trench fill structure (74, 76) includes a periodic lateral alternating sequence of a neck region 78N located in the neck region 79N of the trench 79 and having a minimum width along the second horizontal direction hd2 and a protruding region 78B located in the neck region protruding region 79B of the trench 79 and having a maximum width along the second horizontal direction hd2.

[0101] In Figure 16A and Figure 16B In one embodiment as shown, at least one of the lateral isolation trench fill structures (74, 76) has a height variation of the top surface of the conductive fill structure 76 along the first horizontal direction hd1. The top surface of the lateral isolation trench fill structure (74, 76) includes a plurality of discrete top surface sections of the conductive fill structure 76 that are laterally spaced from each other by an intermediate portion of the top surface of the peripheral spacer 74.

[0102] In Figure 16DIn one embodiment shown, the peripheral spacer 74 includes N laterally extending tunnels 77T that extend laterally along a first horizontal direction hd1 inside the inner perimeter IP, where N is an integer greater than 2. 3 The conductive fill structure 76 includes N vertically extending portions 76T in N of the laterally extending tunnels 77 in the neck region 78N. In one embodiment, the conductive fill structure 76 is a single continuous structure and includes (N + 1) vertically extending portions 76T in the neck region 78N that are staggered along the first horizontal direction hd1 with N laterally extending portions 76B in the protruding region 78B. The embedded air gap 75 can be located in the N laterally extending portions 76B positioned in the protruding region 79B. In one embodiment, the conductive fill structure 76 is composed of at least one metal nitride material.

[0103] Reference Figure 17A and Figure 17B A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be lithographically patterned to form openings over each of the memory opening fill structures in the memory opening fill structure 58 and over the horizontal extending surfaces of the stepped surfaces in the contact regions. An anisotropic etching process can be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the stepped dielectric material portion 65. A drain contact via cavity can be formed through the contact-level dielectric layer 80 over the memory opening fill structure 58. A layer contact via cavity can be formed through the contact-level dielectric layer 80 and the stepped dielectric material portion 65 on the top surface of the corresponding conductive layer in the conductive layer 46. Subsequently, the photoresist layer can be removed, for example, by ashing.

[0104] At least one conductive material (such as a combination of a metal barrier material and a metal fill material) can be deposited in the drain contact via cavity and the layer contact via cavity. The excess portion of at least one conductive material can be removed from above the horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process that can employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the drain contact via cavity filled with at least one conductive material constitutes the drain contact via structure 88 on the top surface of the corresponding drain region in the contact drain region 63. The remaining portion of the layer contact via cavity filled with at least one conductive material constitutes the layer contact via structure 86 on the top surface of the corresponding conductive layer of the contact conductive layer 46.

[0105] Reference Figure 18A and Figure 18B, A connection-level dielectric layer 90 may be formed over the contact-level dielectric layer 80. A connection via cavity may be formed through the connection-level dielectric layer 90 and filled with at least one conductive material (which may include at least one metal material) to form a connection-level via structure (98, 96). The connection-level via structure (98, 96) includes a drain connection via structure 98 of a corresponding drain contact via structure in the contact drain contact via structure 88 and a layer connection via structure 96 of a corresponding layer contact via structure in the contact layer contact via structure 86.

[0106] A bitline-level dielectric layer 120 may be formed over the connection-level dielectric layer 90. A bitline-level line cavity may be formed through the bitline-level dielectric layer 120 and filled with at least one conductive material (which may include at least one metal material) to form a bitline-level metal line (128, 126). The bitline-level metal line may include a bitline 128 extending laterally along a second horizontal direction hd2 and a bitline-level interconnect metal line 126 (not shown separately) that may be used to provide an electrical connection to the layer connection via structure 96.

[0107] Reference Figure 19 , An additional dielectric material layer and additional metal interconnect structures may be formed over the contact-level dielectric layer 80. The additional dielectric material layer may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as a memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bitline-level dielectric material layer embedding the bitlines, which are a subset of the memory-side metal interconnect structure 980.

[0108] A metal bonding pad (referred to herein as a memory-side bonding pad 988) may be formed at the topmost level of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structure 980 and various nodes of a three-dimensional memory array including an alternating stack of an insulating layer 32 and a conductive layer 46 and a memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0109] A memory - side dielectric material layer 960 is formed over the alternating stack (32, 46). A memory - side metal interconnect structure 980 is embedded in the memory - side dielectric material layer 960. A memory - side bonding pad 988 may be embedded within the memory - side dielectric material layer 960, and specifically within the top - most layer of the memory - side dielectric material layer 960. The memory - side bonding pad 988 may be electrically connected to the memory - side metal interconnect structure 980.

[0110] In one embodiment, the memory die 900 may include: a three - dimensional memory array including an alternating stack (32, 46) of insulating layers 32 and conductive layers 46; a two - dimensional array of memory openings 49 that vertically extend through the alternating stack (32, 46); and a two - dimensional array of memory - opening fill structures 58 that are located within the two - dimensional array of memory openings 49 and include corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two - dimensional array of drain - contact via structures 88 that are electrically connected to the corresponding vertical semiconductor channels in the vertical semiconductor channels 60; and a two - dimensional array of layer - contact via structures 86 that are electrically connected to the corresponding conductive layers in the conductive layers 46, with a subset of the conductive layers serving as word lines of the three - dimensional memory array.

[0111] Generally speaking, the memory die 900 includes a memory device, a memory - side metal interconnect structure 980, and a memory - side bonding pad 988 embedded within the memory - side dielectric material layer 960. The memory device includes a three - dimensional memory array comprising an alternating stack of insulating layer 32 and conductive layer 46, and a two - dimensional array of NAND strings (e.g., memory - opening fill structures 58) that vertically extend through the alternating stack (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two - dimensional array of NAND strings. In one embodiment, the memory - side metal interconnect structure 980 includes bit lines 128 of the two - dimensional array of NAND strings.

[0112] Reference Figure 20 Referring, a logic die 700 is provided. The logic die 700 includes a peripheral circuit 720 formed on a logic - side substrate 709. According to one aspect of the present disclosure, the peripheral circuit 720 may be configured to control the operation of a memory array within the memory die 900. For example, the peripheral circuit 720 may include a word - line driver region, a bit - line driver region, a sense - amplifier region, an input / output buffer, etc. A logic - side metal interconnect structure 780 embedded within the logic - side dielectric material layer 760 may be formed over the peripheral circuit 720. The logic die 700 includes a logic - side bonding pad 788 embedded within the logic - side dielectric material layer 760.

[0113] Reference Figure 21, a bonded component can be formed by bonding the logic die 700 to the memory die 900. The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0114] The logic die 700 can be attached to the memory die 900, for example, by bonding the logic-side bonding pads 788 to the memory-side bonding pads 988. The bonding between the memory die 900 and the logic die 700 can be performed using a wafer-to-wafer bonding process (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by a die-to-bonding process, or by a die-to-die bonding process. The logic-side bonding pads 788 within each logic die 700 can be bonded to the memory-side bonding pads 988 within the corresponding memory die 900.

[0115] Reference Figure 22 , the carrier substrate 9 can be removed, for example, by grinding, polishing, cleaving, an isotropic etching process, and / or an anisotropic etching process. If a polishing process such as a chemical mechanical polishing process is used to remove the carrier substrate 9.

[0116] Reference Figure 23 , during or after the substrate 9 removal process, the bottommost insulating layer 32B is also removed. For example, the bottommost insulating layer 32B can be removed by selective etching.

[0117] Reference Figure 24 , the bottom portion of the memory film 50 can be removed from each memory opening fill structure 58 by performing sequential selective etching with respect to the material of the vertical semiconductor channel 60. The bottom surface of each vertical semiconductor channel 60 in the memory opening fill structure 58 can be physically exposed.

[0118] Reference Figure 25 , the source layer 3 can be formed on the physically exposed bottom surface of the vertical semiconductor channel 60. The source layer 3 includes a doped semiconductor material doped with a second conductivity type. The backside dielectric layer 4 can be formed above the source layer 3. At least one backside contact pad 6 can be formed through the backside dielectric layer 4. For example, at least one backside contact pad 6 can include a source contact pad formed on the backside of the source layer 3. In one embodiment, each backside contact pad 6 can include a metal barrier liner 6A and a metal plate portion 6B.

[0119] Reference Figure 26 , illustrates an alternative configuration of the first exemplary structure. The first alternative configuration of the first exemplary structure can be derived from the first exemplary structure illustrated by employing multiple vertical alternating sequences of a continuous insulating layer 32 and a continuous sacrificial material layer 42 with at least one intervening insulating layer (which is referred to herein as at least one interlayer insulating layer 32I) from Figure 25 The maximum lateral extent of each lateral isolation trench 79 can be at the level of the interlayer insulating layer 32I, which is one of the insulating layers 32 within the alternating stack (32, 46).

[0120] Reference Figure 27 , illustrates a second exemplary structure according to a second embodiment of the present disclosure. The second exemplary structure includes the alternating stack (32, 42) described above located above a substrate 9 Figure 1 as described with respect to

[0121] Reference Figure 28 , the processing steps of Figure 2 can be performed to form a stepped surface and a stepped dielectric material portion 65.

[0122] Reference Figure 29A and Figure 29B , reference Figure 3A and Figure 3B The processing steps described with respect to and reference Figure 9A and Figure 9B can be performed simultaneously using the same photoresist mask to form a memory opening 49, a support opening 19, and a discrete opening 179. The discrete opening 179 is formed between adjacent memory blocks.

[0123] Reference Figure 30 , the processing steps described with reference to Figure 4 can be performed to form a sacrificial memory opening fill structure 47 and a sacrificial support opening fill structure 17 in the corresponding memory opening 49 and support opening 19. The sacrificial material is removed from the discrete opening 179 to reopen the discrete opening 179.

[0124] Reference Figure 31A and Figure 31B , the second set of processing steps described with reference to Figure 9A and Figure 9B can be performed to expand the discrete opening 179 to form a lateral isolation trench 79. Generally, the lateral isolation trench 79 in the second exemplary structure can be the same as the lateral isolation trench 79 in the first exemplary structure.

[0125] Reference Figure 32 , the processing steps described with reference to Figure 12The described processing steps remove the sacrificial material layer 42 and form a laterally extending cavity 43. The isotropic etching process selectively removes the material of the sacrificial material layer 42 relative to the materials of the insulating layer 32, the carrier substrate 9, and the sacrificial opening fill structures (47, 17).

[0126] Reference Figure 33 , an executable reference Figure 11 , Figure 12 , Figure 13 and Figure 14 The described processing steps form an optional external barrier dielectric layer 44 and form a conductive layer 46.

[0127] Reference Figures 34A to 34D , an executable selective removal process such as an ashing process removes the sacrificial opening fill structures (47, 17) from the memory opening 49 and from the support opening 19.

[0128] Reference Figure 35A and Figure 35B , an optional continuous barrier dielectric layer 52L, a continuous memory material layer 54L, an optional continuous dielectric pad 56L, a semiconductor channel material layer 60L, and a dielectric core layer 62L may be sequentially deposited in the memory opening 49, the support opening 19, and the lateral isolation trench 79. The continuous barrier dielectric layer 52L may have the same material composition and the same thickness as the barrier dielectric layer 52 in the first exemplary structure. The continuous memory material layer 54L may have the same material composition and the same thickness as the memory material layer 54 in the first exemplary structure. The continuous dielectric pad 56L may have the same material composition and the same thickness as the dielectric pad 56 in the first exemplary structure.

[0129] According to one aspect of the present disclosure, the dielectric core layer 62L may be deposited by a conformal deposition process such as a low-pressure chemical vapor deposition process. In one embodiment, at least one of the lateral isolation trenches 79 may include N neck regions 79N and (N + 1) protrusion regions 79B that are laterally staggered with each other along a first horizontal direction hd1. For example, N may be an integer in the range of 2 3 to 2 14 such as 2 6 to 2 10 but smaller and larger numbers may also be employed.

[0130] The thickness of the dielectric core layer 62L can be greater than half of the width of the unfilled volume of each neck region 79N after the formation of the semiconductor channel material layer 60L in a horizontal plane including the top surface of the contact-level dielectric layer 80, less than half of the width of the unfilled volume of each neck region 79N at the height of the turning line 79I after the formation of the semiconductor channel material layer 60L, and less than half of the width of the unfilled volume of each protruding region 79B after the formation of the semiconductor channel material layer 60L in a horizontal plane including the top surface of the contact-level dielectric layer 80. In this case, each portion of the dielectric core layer 62L located within the corresponding lateral isolation trench 79 can include N laterally extending tunnels 77T (as shown in FIG. 35D) extending laterally along a first horizontal direction hd1 and N + 1 voids 77 (as shown in FIG. 35C). Additionally, each portion of the dielectric core layer 62L located within the corresponding lateral isolation trench 79 can include (N + 1) vertically extending portions that are adjacent to and interleaved with N horizontally extending portions of the corresponding portion of the dielectric core layer 62L.

[0131] Reference Figure 36A and Figure 36B , the conductive filling material can be conformally deposited in the remaining volume of the voids 77 located within the lateral isolation trench 79 to form a conductive filling material layer 76L. According to one aspect of the present disclosure, the conductive filling material can include and / or can be substantially composed of a conductive metal nitride material. In one embodiment, the conductive metal nitride material can include TiN, TaN, WN, or MoN, and / or can be substantially composed of them.

[0132] Reference Figure 37A and Figure 37B , portions of the conductive filling material, the dielectric core layer 62L, the semiconductor channel material layer 60L, the continuous dielectric liner 56L, the continuous memory material layer 54L, and the continuous barrier dielectric layer 52L can be removed from above a horizontal plane including the top surface of the topmost insulating layer 32T by performing a planarization process such as a chemical mechanical polishing process.

[0133] Each remaining portion of the conductive fill material retained in the respective lateral isolation trench 79 constitutes a conductive fill structure 76. Each remaining portion of the dielectric core layer 62L retained in the respective lateral isolation trench 79 constitutes a trench dielectric spacer 162. Each remaining portion of the semiconductor channel material layer 60L retained in the respective lateral isolation trench 79 constitutes a trench semiconductor spacer 160. Each remaining portion of the continuous dielectric liner 56L retained in the respective lateral isolation trench 79 constitutes a third trench spacer liner 156. Each remaining portion of the continuous memory material layer 54L retained in the respective lateral isolation trench 79 constitutes a second trench spacer liner 154. Each remaining portion of the continuous barrier dielectric layer 52L retained in the respective lateral isolation trench 79 constitutes a first trench spacer liner 152. Each adjacent combination of the first trench spacer liner 152, the second trench spacer liner 154, and the third trench spacer liner 156 constitutes a composite trench spacer liner 150. Each continuous combination of the composite trench spacer liner 150, the trench semiconductor spacer 160, and the trench dielectric spacer 162 includes a peripheral spacer 174. The embedded air gap 75 may be located in the conductive fill structure 76 in the protruding region 79B of the trench 79.

[0134] Each remaining portion of the continuous dielectric liner 56L retained in the respective memory opening 49 or the respective support opening 19 constitutes a dielectric liner (e.g., tunneling dielectric) 56. Each remaining portion of the continuous memory material layer 54L retained in the respective memory opening 49 or the respective support opening 19 constitutes a memory material layer 54. Each remaining portion of the continuous barrier dielectric layer 52L retained in the respective memory opening 49 or the respective support opening 19 constitutes a barrier dielectric layer 52. Each adjacent combination of the barrier dielectric layer 52, the memory material layer 54, and the dielectric liner 56 constitutes a memory film 50. Each remaining portion of the semiconductor channel material layer 60L retained in the respective memory opening 49 or the respective support opening 19 constitutes a vertical semiconductor channel 60. Each remaining portion of the dielectric core layer 62L retained in the respective memory opening 49 or the respective support opening 19 constitutes a dielectric core 62. Each adjacent combination of the vertical semiconductor channel 60 and the memory film 50 constitutes a memory stack structure 55.

[0135] The set of all material portions filling the memory openings 49 constitutes a memory opening fill structure 58. The set of all material portions filling the support openings 19 constitutes a support pillar structure 20. Each adjacent combination of the conductive fill structure 76 and the peripheral spacer 174 constitutes a fill structure filling the corresponding lateral isolation trench 79 and is referred to herein as a lateral isolation trench fill structure (174, 76). Each lateral isolation trench fill structure (174, 76) may be located in the lateral isolation trench 79 and may include the peripheral spacer 174 and the conductive fill structure 76. In a second embodiment, the peripheral spacer 174 includes the same set of materials as the combination of the memory film 50, the vertical semiconductor channel, and the dielectric core 62 in the memory opening 49.

[0136] Reference Figure 38A and Figure 38B , a photoresist layer (not shown) may be applied over the second exemplary structure and may be lithographically patterned to form an opening over the region of the dielectric core 62 that overlies the memory opening fill structure 58. A recess etching process may be performed to vertically recess the dielectric core 62.

[0137] Reference Figures 39A to 39D , a doped semiconductor material having a second conductivity type may be deposited in each recessed region over the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material may be in the range of 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 , but smaller or larger dopant concentrations may also be employed. The doped semiconductor material may be, for example, doped polysilicon.

[0138] The excess portions of the deposited semiconductor material doped with the second conductivity type and the horizontal portions of the semiconductor channel material layer 60L may be removed, for example, by chemical mechanical planarization (CMP) or a recess etching process from above the horizontal plane of the top surface including the topmost insulating layer 32T. Each remaining portion of the doped semiconductor material having the second conductivity type constitutes a drain region 63. The memory opening fill structure 58 is formed within each memory opening 49. In one embodiment, the drain region 63 may be omitted from the lateral isolation trench fill structure (174, 76). In another embodiment, while the drain region 63 is formed in the memory opening fill structure, a dummy drain region is formed in the lateral isolation trench fill structure (174, 76).

[0139] Reference Figure 40A and Figure 40B, a contact-level dielectric layer 80 may be formed over the alternating stack (32, 46) and the stepped dielectric material portion 65. Processing steps described with reference to Figure 17A and Figure 17B may be performed to form a drain contact via structure 88 and a layer contact via structure 86.

[0140] Referring to Figure 41 , processing steps described with reference to Figure 18A , Figure 18B and Figure 19 may be performed to form a connection-level dielectric layer 90, a bit-line-level dielectric layer 120, an additional dielectric material layer, and additional metal interconnect structures embedded therein. The additional dielectric material layer formed over the contact-level dielectric layer 80 is referred to herein as a memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as the memory-side dielectric material layer 960. The memory-side dielectric material layer 960 includes a bit-line-level dielectric material layer embedding bit lines 128, which are a subset of the memory-side metal interconnect structures 980.

[0141] A metal bonding pad (which is referred to herein as a memory-side bonding pad 988) may be formed at the topmost level of the memory-side dielectric material layer 960. The memory-side bonding pad 988 may be electrically connected to the memory-side metal interconnect structures 980 and various nodes of a three-dimensional memory array including an alternating stack of an insulating layer 32 and a conductive layer 46 and a memory opening fill structure 58. Thus, a memory die 900 may be provided.

[0142] The memory-side dielectric material layer 960 is formed over the alternating stack (32, 46). The memory-side metal interconnect structures 980 are embedded in the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be embedded within the memory-side dielectric material layer 960, and specifically within the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structures 980.

[0143] Referring to Figure 42 , processing steps described with reference to Figure 20 and Figure 21 may be performed to bond a logic die 700 to the memory die 900.

[0144] Referring to Figure 43, the carrier substrate 9 can be removed, for example, by grinding, polishing, splitting, isotropic etching processes, and / or anisotropic etching processes. If a polishing process such as chemical mechanical polishing is used to remove the carrier substrate 9. If an etching process such as wet etching is used to remove the carrier substrate 9, the bottom portion of the memory film 50 can be removed from each memory opening fill structure 58. The bottom surface of each vertical semiconductor channel 60 in the memory opening fill structure 58 can be physically exposed.

[0145] Reference Figure 44 , the source layer 3 can be formed on the physically exposed bottom surface of the vertical semiconductor channel 60. The source layer 3 includes a doped semiconductor material doped with a second conductivity type. The backside dielectric layer 4 can be formed over the source layer 3. At least one backside contact pad 6 can be formed through the backside dielectric layer 4. For example, at least one backside contact pad 6 can include a source contact pad formed on the backside of the source layer 3. In one embodiment, each backside contact pad 6 can include a metal barrier liner 6A and a metal plate portion 6B.

[0146] Reference Figure 45 , an alternative configuration of the second exemplary structure is illustrated. The alternative configuration of the second exemplary structure can be derived from the second exemplary structure by employing a plurality of vertical alternating sequences of a continuous insulating layer 32 and a continuous sacrificial material layer 42 with at least one intervening insulating layer (which is referred to herein as at least one interlayer insulating layer 32I). In this case, the maximum lateral extent of each lateral isolation trench 79 can be at the level of the interlayer insulating layer 32I, which is one of the insulating layers 32 in the alternating stack (32, 46).

[0147] Referring to all the accompanying drawings and in accordance with various embodiments of the present disclosure, a three-dimensional memory device is provided, which includes: a pair of alternating stacks (32, 46) of an insulating layer 32 and a conductive layer 46, the pair of alternating stacks (32, 46) being laterally spaced apart from each other by a lateral isolation trench 79 extending generally along a first horizontal direction hd1; memory openings 49 that vertically extend through corresponding stacks in the pair of alternating stacks (32, 46); a memory opening filling structure 58 that is located in a corresponding one of the memory openings 49 and includes a corresponding vertical stack of memory elements at a level of the conductive layer 46; and a lateral isolation trench filling structure {(74, 174), 76} that is located in the lateral isolation trench 79 and includes peripheral spacers (74, 174) and a conductive filling structure 76. The lateral isolation trench filling structure has a width modulation along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 at levels of both the insulating layer 32 and the conductive layer 42, and the width modulation varies with a lateral distance along the first horizontal direction.

[0148] In one embodiment, a first vertical cross-sectional view of the lateral isolation trench filling structure {(74, 174), 76} in a first vertical plane perpendicular to the first horizontal direction hd1 includes: an outer perimeter OP of the peripheral spacers (74, 174), the outer perimeter OP including a horizontal top surface section located in a first horizontal plane HP1; and an inner perimeter IP of the peripheral spacers (74, 174), the inner perimeter IP being vertically spaced apart from the first horizontal plane HP1 and being entirely located below the first horizontal plane.

[0149] In one embodiment, the horizontal top surface section of the outer perimeter OP of the peripheral spacers (74, 174) is connected to the inner perimeter IP of the peripheral spacers (74, 174) by a vertically extending seam 74S, at which two vertical surfaces of the peripheral spacers (74, 174) are in direct contact with each other. In one embodiment, the outer perimeter OP of the peripheral spacers (74, 174) includes a pair of tapered upper sidewall sections that adjoin corresponding ends of the horizontal top surface section of the peripheral spacers (74, 174); and a lateral spacing between the pair of tapered upper sidewall sections decreases with a vertical distance from a second horizontal plane HP2 located below the first horizontal plane HP1. In one embodiment, the outer perimeter OP of the peripheral spacers (74, 174) further includes a pair of tapered lower sidewall sections underlying the pair of tapered upper sidewall sections of the peripheral spacers (74, 174); and a lateral spacing between the pair of tapered lower sidewall sections decreases with a vertical distance from the second horizontal plane HP2.

[0150] In one embodiment, the inner perimeter IP of the peripheral spacer (74, 174) has a maximum width at a second horizontal plane HP2 that is below the top surface of the topmost layer within the pair of alternating stacks and above the bottommost surface of the bottommost layer within the pair of alternating stacks. In one embodiment, in a first vertical cross-sectional view, the conductive fill structure 76 fills the entire region within the inner perimeter IP of the peripheral spacer (74, 174).

[0151] In one embodiment, the lateral isolation trench fill structure {(74, 174), 76} includes a periodic lateral alternating sequence of a neck region 78N having a minimum width along a second horizontal direction and a bulge region 78B having a maximum width along the second horizontal direction. In one embodiment, the lateral isolation trench fill structure {(74, 174), 76} includes a pair of laterally undulating longitudinal sidewalls; and each of the pair of laterally undulating longitudinal sidewalls includes a set of horizontally protruding and vertically tapered surface segments that are adjacent to each other at the edges. In one embodiment, the top surface of the conductive fill structure 76 has a height variation along a first horizontal direction hd1; and the top surface of the lateral isolation trench fill structure {(74, 174), 76} includes a plurality of discrete top surface segments of the conductive fill structure 76 that are laterally spaced apart from each other by an intervening portion of the top surface of the peripheral spacer (74, 174).

[0152] In one embodiment, the peripheral spacer (74, 174) includes N laterally extending tunnels that extend laterally along a first horizontal direction hd1; N is an integer greater than 2 3 ; and the conductive fill structure 76 includes N vertically extending portions that are located within the N laterally extending tunnels. In one embodiment, the conductive fill structure 76 is a single continuous structure and further includes (N + 1) vertically extending portions that are interleaved with the N laterally extending portions along the first horizontal direction hd1.

[0153] In one embodiment, the conductive fill structure 76 includes titanium or titanium nitride. In one embodiment, the peripheral spacer (74, 174) is composed of at least one dielectric material. In one embodiment, the peripheral spacer (74, 174) includes at least one dielectric material and at least one semiconductor material that is electrically isolated from the conductive fill structure 76.

[0154] In one embodiment, the memory device includes a memory die 900 that includes bond pads 988 located above the pair of alternating stacks (32, 46); a logic die 700 that includes a peripheral circuit 720 is bonded to the bond pads 988; and a semiconductor source layer 3 is located below the pair of alternating stacks in contact with an end of a vertical semiconductor channel 60.

[0155] Various embodiments of the present disclosure can be used to provide a laterally isolated trench fill structure {(74, 174), 76} including a conductive fill structure 76. The conductive fill structure 76 can include a dummy structure that is not used as a source contact or an interconnect and is not electrically connected to the source layer of the memory device. In one embodiment, the conductive fill structure 76 includes a low-stress material such as titanium or titanium nitride, which provides high flexural strength, low substrate warpage, and no fluorine outgassing. The air gaps (i.e., voids) 75 (if any) in the conductive fill structure 76 are formed as discrete voids, and the conductive fill structure 76 is formed as a single continuous structure without voids at each neck region 78N of the laterally isolated trench fill structure {(74, 174), 76}. Thus, the conductive fill structure 76 can provide enhanced mechanical strength to the three-dimensional memory device.

[0156] Although the foregoing relates to specific preferred embodiments, it should be understood that the present disclosure is not limited thereto. Those of ordinary skill in the art can envision that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or "consisting of" replace the words "comprising" or "including". Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group including the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the execution of a processing step, embodiments in which such element or such processing step is not performed are also clearly contemplated, provided that the resulting device or apparatus can provide an equivalent result. Thus, whenever the formation of such element or such processing step can be omitted to provide the same result or an equivalent result, the auxiliary verb "can" as applied to the formation or execution of the element or processing step should also be interpreted as "may" or "may, or may not", and these equivalent results include slightly superior results and slightly inferior results. In cases where embodiments employing a specific structure and / or configuration are illustrated in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structure and / or configuration that is functionally equivalent, provided that such substitution is not expressly prohibited or otherwise known to be impossible to those of ordinary skill in the art. If publications, patent applications, and / or patents are cited herein, each such document is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: A pair of alternating stacks of insulating layers and conductive layers, the pair of alternating stacks being laterally spaced apart from each other by a lateral isolation trench extending generally along a first horizontal direction; Memory openings extending vertically through corresponding stacks of the pair of alternating stacks; Memory opening filling structures located in corresponding ones of the memory openings and including corresponding vertical semiconductor channels and corresponding vertical stacks of memory elements at levels of the conductive layers; And A lateral isolation trench filling structure located in the lateral isolation trench and including a peripheral spacer and a conductive filling structure, wherein the lateral isolation trench filling structure has a width modulation in a second horizontal direction perpendicular to the first horizontal direction at levels of both the insulating layer and the conductive layer, the width modulation varying with a lateral distance along the first horizontal direction.

2. The three-dimensional memory device according to claim 1, wherein a first vertical cross-sectional view of the lateral isolation trench filling structure in a first vertical plane perpendicular to the first horizontal direction includes: An outer perimeter of the peripheral spacer, the outer perimeter of the peripheral spacer including a horizontal top surface section in a first horizontal plane; And An inner perimeter of the peripheral spacer, the inner perimeter of the peripheral spacer being vertically spaced from the first horizontal plane and being entirely located below the first horizontal plane.

3. The three-dimensional memory device according to claim 2, wherein: The outer perimeter of the peripheral spacer includes a pair of tapered upper sidewall sections adjacent to respective ends of the horizontal top surface section of the peripheral spacer; and A lateral spacing between the pair of tapered upper sidewall sections decreases with a vertical distance from a second horizontal plane located below the first horizontal plane.

4. The three-dimensional memory device according to claim 3, wherein: The outer perimeter of the peripheral spacer further includes a pair of tapered lower sidewall sections underlying the pair of tapered upper sidewall sections of the peripheral spacer; and A lateral spacing between the pair of tapered lower sidewall sections decreases with the vertical distance from the second horizontal plane.

5. The three-dimensional memory device according to claim 3, wherein: The inner perimeter of the peripheral spacer has a maximum width at the second horizontal plane, the second horizontal plane being located below a top surface of a topmost layer within the pair of alternating stacks and above a bottommost surface of a bottommost layer within the pair of alternating stacks; And In the first vertical cross-sectional view, the conductive filling structure fills an entire area within the inner perimeter of the peripheral spacer.

6. The three-dimensional memory device according to claim 2, wherein a horizontal top surface section of the outer periphery of the peripheral spacer is connected to the inner periphery of the peripheral spacer by a vertically extending seam, at which vertically extending seam, two vertical surfaces of the peripheral spacer are in direct contact with each other.

7. The three-dimensional memory device according to claim 1, the three-dimensional memory device further comprising: bonding pads located above the pair of alternating stacks; a logic die including peripheral circuitry bonded to the bonding pads; and a semiconductor source layer located below the pair of alternating stacks in contact with an end of the vertical semiconductor channel.

8. The three-dimensional memory device according to claim 1, wherein the laterally isolated trench fill structure comprises a periodic lateral alternating sequence of a neck region having a minimum width along the second horizontal direction and a protruding region having a maximum width along the second horizontal direction.

9. The three-dimensional memory device according to claim 1, wherein: the laterally isolated trench fill structure comprises a pair of laterally undulating longitudinal sidewalls; and each laterally undulating longitudinal sidewall of the pair of laterally undulating longitudinal sidewalls comprises a set of horizontally protruding and vertically tapered surface sections adjacent to each other at an edge.

10. The three-dimensional memory device according to claim 1, wherein: a top surface of the conductive fill structure has a height variation along the first horizontal direction; and a top surface of the laterally isolated trench fill structure comprises a plurality of discrete top surface sections of the conductive fill structure, the plurality of discrete top surface sections being laterally spaced apart from each other by an intermediate portion of the top surface of the peripheral spacer.

11. The three-dimensional memory device according to claim 1, wherein: the peripheral spacer comprises N laterally extending tunnels extending laterally along the first horizontal direction; N is an integer greater than 2 3 ; and the conductive fill structure comprises N vertically extending portions located in the N laterally extending tunnels.

12. The three-dimensional memory device according to claim 11, wherein the conductive fill structure is a single continuous structure, the single continuous structure further comprising (N + 1) vertically extending portions staggered along the first horizontal direction with the N laterally extending portions.

13. The three-dimensional memory device according to claim 1, wherein the conductive fill structure consists essentially of titanium or titanium nitride.

14. The three-dimensional memory device according to claim 1, wherein the peripheral spacer comprises at least one dielectric material.

15. The three-dimensional memory device according to claim 1, wherein the peripheral spacer comprises at least one dielectric material and at least one semiconductor material electrically isolated from the conductive fill structure.

16. A method of forming a three-dimensional memory device, the method comprising: forming a vertical alternating sequence of a continuous insulating layer and a continuous sacrificial material layer above a substrate; forming a memory opening through the vertical alternating sequence; A memory opening fill structure is formed in the memory opening, wherein each memory opening fill structure in the memory opening fill structure includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; A lateral isolation trench is formed through the vertical alternating sequence, wherein the lateral isolation trench has a width modulation along a second horizontal direction perpendicular to the first horizontal direction at levels of both the insulating layer and the sacrificial material layer, and the width modulation varies with a lateral distance along the first horizontal direction; The remaining portion of the continuous sacrificial material layer is replaced with a conductive layer to form a pair of alternating stacks of an insulating layer and a conductive layer on opposite sides of the lateral isolation trench; And A lateral isolation trench fill structure is formed in the lateral isolation trench, wherein the lateral isolation trench fill structure includes a peripheral spacer and a conductive fill structure formed in the peripheral spacer.

17. The method according to claim 16, wherein: The peripheral spacer includes N laterally extending tunnels extending transversely along the first horizontal direction, where N is an integer greater than 2 3 ; and The conductive fill structure includes N horizontally extending portions located in the N laterally extending tunnels, and (N + 1) vertically extending portions adjacent to and interleaved with the N horizontally extending portions.

18. The method according to claim 16, the method further comprising: Removing the substrate and exposing ends of the vertical semiconductor channels; And Forming a source layer on the exposed ends of the vertical semiconductor channels.

19. The method according to claim 16, wherein forming the lateral isolation trench through the vertical alternating sequence includes: Forming discrete openings through the vertical alternating sequence; And Expanding the discrete openings at levels of the insulating layer and the sacrificial material layer to form the lateral isolation trench.

20. The method according to claim 16, wherein the memory opening fill structure and the peripheral spacer are formed by: Depositing in sequence a set of material layers including a semiconductor channel material layer, a dielectric core material layer, and a plurality of dielectric material layers; And Removing horizontally extending portions of the set of material layers from above the vertical alternating sequence, wherein: The memory opening fill structure includes the portions of the set of material layers retained in the memory opening; and The peripheral spacer includes the portions of the set of material layers retained in the lateral isolation trench.

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