Cavity shaping and selective metal silicide formation for CMOS devices

Abstract

A method of forming an electrical contact in a semiconductor structure includes performing a cavity forming process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region and a p-type MOS (p-MOS) region, the cavity forming process including forming an n-MOS cavity in an exposed surface of the n-MOS region and forming a p-MOS cavity in an exposed surface of the p-MOS region; and performing a first selective deposition process to selectively form a p-MOS cavity contact in the p-MOS cavity.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of U.S. Provisional Application Serial No. 63 / 433,154, filed on December 16, 2022, the entire disclosure of which is incorporated herein by reference. Background of the Invention

[0003] Field

[0004] Embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming electrical contacts within a semiconductor structure.

[0005] Description of Related Art

[0006] Multi - gate metal - oxide - semiconductor field - effect transistors (MOSFETs), such as complementary metal - oxide semiconductor (CMOS) devices, pose challenges in manufacturability due to their three - dimensional (3D) design and small size. In advanced CMOS devices, metal silicides (e.g., molybdenum silicide (MoSi2), ruthenium silicide (Ru x Si y )) selectively formed at the bottom of trench contacts are often used to reduce contact resistivity, and process improvements for exposing the surface of pre - cleaned trench contacts have been driven to optimize the selectivity of metal silicide formation. However, the pre - cleaning process itself does not provide sufficient selectivity in the formation of metal silicides.

[0007] Accordingly, there is a need for methods and systems capable of selectively forming metal silicide contacts in trench contacts for CMOS devices. Summary of the Invention

[0008] Embodiments of the present disclosure provide a method for forming an electrical contact in a semiconductor structure. The method includes performing a cavity - forming process on a semiconductor structure having an n - type metal - oxide - semiconductor (n - MOS) region and a p - type MOS (p - MOS) region, the cavity - forming process including forming an n - MOS cavity in an exposed surface of the n - MOS region and forming a p - MOS cavity in an exposed surface of the p - MOS region, and performing a first selective deposition process to selectively form a p - MOS cavity contact in the p - MOS cavity.

[0009] Embodiments of the present disclosure also provide a method of forming electrical contacts in a semiconductor structure. The method includes performing a pre-clean process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region, a p-type metal oxide semiconductor (p-MOS) region, and a dielectric layer having a first trench over the n-MOS region and a second trench over the p-MOS region; performing a cavity forming process to form an n-MOS cavity in an exposed surface of the n-MOS region within the first trench and a p-MOS cavity in an exposed surface of the p-MOS region within the second trench; performing a first selective deposition process to selectively form a p-MOS cavity contact in the p-MOS cavity; performing a second selective deposition process to selectively form an n-MOS cavity contact in the n-MOS cavity; performing a blanket deposition process to form a barrier layer on exposed inner surfaces of the first trench and the second trench and on an exposed surface of the dielectric layer; and performing a metal filling process to form a first contact plug in the first trench and a second contact plug in the second trench.

[0010] Embodiments of the present disclosure also provide a processing system. The processing system includes a first processing chamber, a second processing chamber, and a system controller configured to cause the processing system to perform a cavity forming process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region and a p-type metal oxide semiconductor (p-MOS) region in the first processing chamber, the cavity forming process including forming an n-MOS cavity in an exposed surface of the n-MOS region and a p-MOS cavity in an exposed surface of the p-MOS region, and performing a first selective deposition process in the second processing chamber to selectively form a p-MOS cavity contact in the p-MOS cavity. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To enable a manner of understanding the above-described features of the present disclosure in detail, a more particular description of the present disclosure as briefly summarized above may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the disclosed subject matter and are thus not to be considered limiting of its scope, as the present disclosure may admit to other equally effective embodiments.

[0012] Figure 1 is a schematic top view of a multi-chamber processing system in accordance with one or more embodiments of the present disclosure.

[0013] Figure 2A is a cross-sectional view of a processing chamber in accordance with one or more embodiments.

[0014] Figure 2B is Figure 2A an enlarged view of a portion of the processing chamber.

[0015] Figure 3 A process flow diagram showing a method of forming a contact layer in a semiconductor structure in accordance with one or more embodiments of the present disclosure.

[0016] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E and Figure 4F are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of Figure 3 .

[0017] For ease of understanding, wherever possible, the same element symbols are used to denote the same elements common to the drawings. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0018] The embodiments described herein provide methods and systems for forming an electrical contact comprising a metal silicide (e.g., molybdenum silicide (MoSi2), ruthenium silicide (Ru x Si y )) on a selected portion of a structure for forming a CMOS device (e.g., on an exposed surface of a silicon germanium layer). The method and system can be particularly useful for forming, in a semiconductor structure having regions containing silicon: regions containing silicon germanium, a dielectric layer formed thereon, and metal silicide contacts (e.g., molybdenum silicide (MoSi2), ruthenium silicide (Ru x Si y )) on the exposed surface of the silicon germanium material selectively formed within openings or features (e.g., contact trenches) in the dielectric layer. The processes described herein are configured to form a cavity in the opening or feature (e.g., contact trench) whose surface is optimized for selective deposition of the metal silicide.

[0019] Figure 1FIG. 0 is a schematic top view of a multi-chamber processing system 100 in accordance with one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and process chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 may be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment external to the processing system 100 (e.g., the ambient atmospheric environment such as may exist in a wafer fab). For example, in the various processes performed on substrates in the processing system 100, the substrates may be processed in various chambers maintained at a low pressure (e.g., less than or equal to about 300 Torr) or in a vacuum environment and transferred between various chambers without breaking the low pressure or vacuum environment. Accordingly, the processing system 100 may provide an integrated solution for some processing of substrates.

[0020] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include or integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems (including processing systems from other manufacturers) may be adapted to benefit from the aspects described herein.

[0021] In Figure 1 the illustrated example, the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate transfer of substrates. The docking station 132 is adapted to receive one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of the respective factory interface robot 134, the blade 138 being adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0022] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 148, 150 coupled to the hold chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the hold chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings having slit valves that are used to pass substrates therethrough by the transfer robots 112, 114 and that are used to provide a seal between the respective chambers to prevent gases from passing between the respective chambers. Generally, any port is open for transferring substrates therethrough. Otherwise, the port is closed.

[0023] The load lock chambers 104, 106, the transfer chambers 108, 110, the hold chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not shown in detail). The gas and pressure control system can include one or more gas pumps (e.g., turbopumps, cryopumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 to the load lock chamber 104 or 106 via the port 140 or 142. Then, the gas and pressure control system evacuates the load lock chamber 104 or 106. The gas and pressure control system also maintains the transfer chambers 108, 110 and the hold chambers 116, 118 in an internal low pressure or vacuum environment (which can include an inert gas). Thus, evacuation of the load lock chamber 104 or 106 facilitates the delivery of substrates between the atmospheric environment of, for example, the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0024] When the substrate is in the already evacuated load lock chamber 104 or 106, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 via the port 144 or 146. The transfer robot 112 can then transfer the substrate to any processing chamber 120, 122 and / or transfer the substrate between any processing chambers 120, 122 for processing via the corresponding ports 152, 154, and transfer the substrate to the holding chambers 116, 118 via the corresponding ports 148, 150 for holding awaiting further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chambers 116 or 118 via the ports 156 or 158, and can transfer the substrate to the processing chambers 124, 126, 128, 130 and / or transfer the substrate between any processing chambers 124, 126, 128, 130 for processing via the corresponding ports 160, 162, 164, 166, and transfer the substrate to the holding chambers 116, 118 via the corresponding ports 156, 158 for holding awaiting further transfer. The transfer and holding of the substrate within and between different chambers can be performed in a low pressure or vacuum environment provided by the gas and pressure control system.

[0025] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing the substrate. In some instances, the processing chamber 120 can perform an etching process, the processing chamber 122 can perform a cleaning process, the processing chamber 124 can perform a selective removal process, and the processing chambers 126, 128, 130 can perform corresponding epitaxial growth processes. The processing chamber 120 can be a Selectra TM etching chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chamber 122 can be a SiCoNi TM pre-cleaning chamber available from Applied Materials, Inc. of Santa Clara, California. The processing chambers 126, 128 or 130 can be Centura TM epitaxial chambers available from Applied Materials, Inc. of Santa Clara, California.

[0026] The system controller 168 is coupled to the processing system 100 and is configured to control the processing system 100 or its components. For example, the system controller 168 may control the operation of the processing system 100 by directly controlling the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100, or by controlling the controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 126, 128, 130. In operation, the system controller 168 is capable of collecting data and feedback from the individual chambers to coordinate the execution of the processing system 100.

[0027] The system controller 168 generally includes a central processing unit (CPU) 170, a memory 172, and support circuitry 174. The CPU 170 may be one of any form of general-purpose processor that can be used in an industrial environment. The memory 172 or non-transitory computer-readable medium is accessible by the CPU 170 and may be one or more of memories such as random-access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital memory. The support circuitry 174 is coupled to the CPU 170 and may include a cache, a clock circuit, an input / output subsystem, a power supply, etc. The various methods disclosed herein can generally be implemented under the control of the CPU 170 by the CPU 170 executing computer instruction codes stored in the memory 172 (or the memory of a specific processing chamber) as, for example, software routines. When the computer instruction codes are executed by the CPU 170, the CPU 170 controls the chambers to perform processing according to the various methods.

[0028] Other processing systems may adopt other configurations. For example, more or fewer processing chambers may be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer device in the processing system.

[0029] Figure 2A is a cross-sectional view of a processing chamber 200 according to one or more embodiments, which is adapted to perform the pre-cleaning process detailed below. The processing chamber 200 may be Figure 1 the illustrated processing chamber 122. Figure 2B is Figure 2A an enlarged view of a portion of the processing chamber 200.

[0030] The processing chamber 200 can be specifically used to perform thermal or plasma-based cleaning processes and / or plasma-assisted dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed at the upper end of the chamber body 202, and the support assembly 206 is at least partially disposed within the chamber body 202. A vacuum system can be used to remove gas from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 further includes a controller 212 for controlling the processes within the processing chamber 200.

[0031] The lid assembly 204 includes a stacked member adapted to provide precursor gas and / or plasma to a processing region 214 within the processing chamber 200. A first plate 216 is coupled to a second plate 218. A third plate 220 is coupled to the second plate 218. The lid assembly 204 can be connected to a power source (not shown) for supplying plasma to a tapered chamber 222 formed in the lid assembly 204. The lid assembly 204 can also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma chamber (e.g., Figures 2A to 2B the processing region 214, the first plate 216, and the second plate 218 therein) is coupled to a gas source 226 via the remote plasma source 224 (or, in the absence of the remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 can include a gas source adapted to provide helium, argon, or other inert gas. In some configurations, the gas provided by the gas source 226 can be excited into plasma, and these plasmas are provided to the lid assembly 204 by using the remote plasma source 224. In an alternative embodiment, the gas source 226 can provide a process gas that can be activated by the remote plasma source 224 before being introduced onto the surface of a substrate disposed within the processing chamber 200. Referring to Figure 2B , the tapered chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 to a volume 230 formed in a fourth plate 232 of the lid assembly 204.

[0032] In some configurations of the lid assembly 204, plasma is generated within the tapered chamber 222 by applying energy delivered from a plasma source. In one example, energy can be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas located within the tapered chamber 222. In this configuration of the lid assembly 204, the remote plasma source 224 can be not used, or the remote plasma source 224 is not installed within the lid assembly 204.

[0033] The central conduit 234 formed in the fourth plate 232 is adapted to supply plasma generating species provided from the volume 230 to a mixing chamber 238 formed in a sixth plate 240 of the lid assembly 204 via a fifth plate 236. The central conduit 234 is in communication with the mixing chamber 238 via an opening 242 in the fifth plate 236. The diameter of the opening 242 may be less than, greater than, or equal to the diameter of the central conduit 234. In Figure 2B an embodiment, the opening 242 has the same diameter as the central conduit 234.

[0034] The fourth plate 232 further includes inlets 244 and 246 adapted to supply gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may include processing gases as well as inert gases, such as inert gases used as carrier gases, such as argon and / or helium. The first gas source 248 may include ammonia (NH3) as well as argon (Ar). The second gas source 250 may contain fluorine-containing gases, hydrogen-containing gases, or combinations thereof. In one example, the second gas source 250 may contain hydrogen fluoride (HF) as well as argon (Ar).

[0035] As Figure 2B shown, in some configurations, the inlet 244 is coupled to the mixing chamber 238 via a cylindrical channel 252 (shown in dashed lines) and a hole 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 via a cylindrical channel 256 (shown in dashed lines) and a hole 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are sized such that they enable the gases provided from their respective gas sources 248, 250 to flow uniformly into the mixing chamber 238. In one configuration, the diameter of the hole 258 is less than the width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The hole 258 is typically circumferentially distributed around the centerline of the cylindrical channel 256 to provide uniform fluid flow into the mixing chamber 238. In one configuration, the diameter of the hole 254 is less than the width of the opening defined by the opposing sidewalls of the cylindrical channel 252 forming the fourth plate 232. The hole 254 is typically circumferentially distributed around the centerline of the cylindrical channel 252 to provide uniform fluid flow into the mixing chamber 238.

[0036] Inlets 244 and 246 provide respective fluid flow paths that traverse horizontally through the fourth plate 232, turn, and penetrate the fifth plate 236 to reach the mixing chamber 238. The cover assembly 204 further includes a seventh plate or a first gas distributor 260, which may be a gas distribution plate, such as a showerhead, through which the various gases mixed in the cover assembly 204 flow through the perforations 262 formed therein. The perforations 262 are in fluid communication with the mixing chamber 238 to provide a flow path from the mixing chamber 238 through the first gas distributor 260. Return reference Figure 2A , a baffle plate 264 and a gas distribution plate, such as a second gas distribution plate 266, which may be a gas distribution plate, such as a showerhead, are disposed below the cover assembly 204.

[0037] Alternatively, different cleaning processes may be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH3) may be introduced into the processing chamber 200 via the cover assembly 204, while ammonia (NH3) may be directly injected into the processing chamber 200 via a separate gas inlet 268 disposed on one side of the chamber body 202 and coupled to a gas source (not shown).

[0038] The support assembly 206 may include a substrate support 270 to support the substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 via a shaft 276 that extends through a central opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 via a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 allows the substrate support 270 to move vertically between a processing position and a loading position within the chamber body 202. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0039] The substrate support 270 has a flat or substantially flat substrate support surface for supporting the substrate 272 being processed thereon. The substrate support 270 may be vertically moved within the chamber body 202 by the actuator 274, which is coupled to the substrate support 270 via the shaft 276. For some process operations, the substrate support 270 may be lifted to a position close to the cover assembly 204 to control the temperature of the processed substrate 272. In this way, the substrate 272 may be heated via radiation emitted from the second gas distributor 266 or another radiation source, or via convection or conduction of an intermediate gas from the second gas distributor 266. In some process steps, the substrate may be disposed on a lift rod 278 to perform additional heat treatment operations, such as performing an annealing step.

[0040] Figure 3FIG. 300 is a process flow diagram of a method of forming a contact layer in a semiconductor structure 400 in accordance with some embodiments of the present disclosure. Figure 4A and Figure 4B and Figure 4C and Figure 4D and Figure 4E and Figure 4F are cross-sectional views of a portion of the semiconductor structure 400 corresponding to various states of the method 300. It should be understood that Figure 4A and Figure 4B and Figure 4C and Figure 4D and Figure 4E and Figure 4F only show partial schematic views of the semiconductor structure 400, and the semiconductor structure 400 may contain any number of transistor portions and additional materials having aspects as shown. It should also be noted that although Figure 3 the methods shown are described in sequence, other process sequences including one or more operations that have been omitted and / or added and / or have been rearranged in another desired order are within the scope of the disclosed embodiments provided herein.

[0041] Referring to Figure 4A and Figure 4B and Figure 4C and Figure 4D and Figure 4E and Figure 4F the semiconductor structure 400 may include an n-type MOS device 402 and a p-type MOS device 404 formed on a substrate (not shown).

[0042] As used herein, the term "substrate" refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. As needed, the substrate may be a silicon-based material or any suitable insulating or conductive material. The substrate may include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0043] As shown in Figure 4AAs shown, a portion of the n-type MOS device 402 among multiple n-type transistor devices formed on a substrate includes an n-type metal oxide semiconductor (n-MOS) region 406 formed of a first material such as silicon (Si). A portion of the p-type MOS device 404 among multiple p-type transistor devices formed on the substrate includes a p-type MOS (p-MOS) region 408 formed of a second material such as silicon germanium (SiGe). The first material and the second material include materials with different compositions such that the second material can be selectively etched relative to the first material (i.e., the etching rate of the second material is higher than that of the first material). The etching selectivity of the second material (i.e., the ratio of the etching rate of the second material to the etching rate of the first material) is between about 10:1 and 500:1. Other example combinations of the first material and the second material respectively include silicon (Si) / silicon germanium (SiGe), germanium (Ge) / silicon germanium (SiGe), or silicon (Si) / germanium tin (GeSn).

[0044] Depending on the desired conductive characteristics of the n-type MOS device 402, the n-MOS region 406 can be doped with an n-type dopant having a concentration between about 10 20 cm -3 and 5x10 21 cm -3 such as phosphorus (P), antimony (Sb). Depending on the desired conductive characteristics of the p-type MOS device 404, the p-MOS region 408 can be doped with a p-type dopant having a concentration between about 10 20 em -3 and about 5x10 21 cm 3 such as boron (B) or gallium (Ga).

[0045] The semiconductor structure 400 further includes a dielectric layer 410 having a first trench 412 formed on the n-MOS region 406 and a second trench 414 formed on the p-MOS region 408. The dielectric layer 410 can be formed of a dielectric material such as silicon dioxide (SiO2) or silicon nitride (Si3N4).

[0046] The n-MOS region 406 and the p-MOS region 408 can be formed using any suitable deposition technique such as epitaxial (Epi) deposition, chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the first and second trenches 412 and 414 are formed by patterning techniques such as lithography and etching processes.

[0047] Method 300 begins with a pre-clean process in block 310. The pre-clean process can be performed in a processing chamber, such as the processing chamber 122 shown in Figure 1 or the processing chamber 200 shown in FIG. 2. The pre-clean process in block 310 can be performed without breaking the vacuum environment in a multi-chamber processing system, such as the multi-chamber processing system 100 shown in Figure 1 .

[0048] The pre-clean process is configured to remove contaminants formed on the exposed surfaces of the n-MOS region 406 in the first trench 412 and the p-MOS region 408 in the second trench 414, such as carbon-containing contaminants (e.g., patterned residues) or oxide-containing contaminants (e.g., native oxide layers).

[0049] The pre-clean process for removing carbon-containing contaminants can include an anisotropic remote plasma-assisted dry etching process using a plasma formed from a gas including hydrogen (H), argon (Ar), helium (He), or a combination thereof, such as a reactive ion etching (RIE) process. The plasma effluent is directed to bombard and remove the remaining dielectric layer within the first trench 412 and the second trench 414.

[0050] The pre-clean process for removing oxide-containing contaminants can include an isotropic plasma etching process, such as a dry chemical etching process using amorphous hydrofluoric acid (HF) and ammonia (NH3), or a SiCoNi TM dry etching process using a plasma formed from a gas including ammonia (NH3), nitrogen trifluoride (NF3). The dry etching process is selective to the oxide layer and thus does not easily etch silicon, germanium, or nitride layers, whether these layers are amorphous, crystalline, or polycrystalline. The selectivity of the dry etching process to the oxide relative to silicon or germanium is at least about 3:1, and typically 5:1 or better, and sometimes 10:1. The selectivity of the dry etching process to the oxide relative to nitride is also high. The selectivity of the dry etching process relative to nitride is at least about 3:1, typically 5:1 or better, and sometimes 10:1.

[0051] In block 320, as shown in Figure 4B , a cavity forming process is performed to form an n-MOS cavity 406C in the exposed surface of the n-MOS region 406 within the first trench 412 and a p-MOS cavity 408C in the exposed surface of the p-MOS region 408 within the second trench 414. The cavity forming process can be performed in an etching chamber, such as the processing chamber 120 shown in Figure 1 . The cavity forming process in block 320 can be performed without breaking the vacuum environment in a multi-chamber processing system, such as Figure 1It is performed in a vacuum environment in the multi-chamber processing system 100 shown.

[0052] The cavity forming process in block 320 includes an etching process using an etching gas that includes a halogen-containing gas such as chlorine (Cl2), hydrogen chloride (HCl), or hydrogen fluoride (HF), and a carrier gas such as argon (Ar) or helium (He). The etching process using chlorine (Cl2) and hydrogen (H2) is sensitive to the amount of germanium (Ge), and thus the cavity forming process reacts differently on the n-MOS region 406 (e.g., silicon (Si)) and the p-MOS region 408 (e.g., silicon germanium (SiGe)). This difference may result in a difference in the deposition rate of the metal material on the exposed surfaces of the n-MOS cavity 406C (e.g., silicon (Si)) and the p-MOS cavity 408C (e.g., silicon germanium (SiGe)) in a subsequent selective deposition process.

[0053] The n-MOS and p-MOS cavities 406C and 408C can have a V shape, a U shape, or any other shape, with a width between about 5 nm and about 15 nm and a depth between about 5 nm and about 15 nm, and the contact area between the p-MOS region 408 and the contact plug to be formed in the second trench 414 is enlarged to minimize the parasitic resistance, resulting in improved device performance.

[0054] The cavity forming process is used to refresh (e.g., etch a surface of about a few nanometers that may be contaminated by remaining oxygen, nitrogen, or carbon) and prepare a pure and pollution-free exposed surface of the n-MOS and p-MOS cavities 406C and 408C, on which contacts (e.g., metal silicides) can be selectively formed in the p-MOS cavity 408C in a subsequent deposition process. The cavity forming process is also used to optimize device stress.

[0055] In block 330, a first selective deposition process is performed to selectively form a p-MOS cavity contact 416 in the p-MOS cavity 408C, as Figure 4C shown. The first selective deposition process can be performed in a processing chamber such as Figure 1 the processing chambers 126, 128, or 130 shown. The first selective deposition process in block 330 can be performed without breaking the vacuum environment in the multi-chamber processing system (such as Figure 1 the multi-chamber processing system 100 shown).

[0056] The p-MOS cavity contact 416 can be formed of a first metal material such as molybdenum (Mo), ruthenium (Ru), or their silicides. The p-MOS cavity contact 416 is connected to the p-MOS region 408 and the contact plug to be formed in the second trench 414 and provides an electrical connection between the two.

[0057] In some embodiments, the first selective deposition process includes a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or a similar process. The selectivity in the first selective deposition process can be caused by the difference in the reaction of the deposition precursor of the first metal material (e.g., molybdenum (Mo), ruthenium (Ru)) with the exposed surfaces of the n-MOS cavity 406C (e.g., silicon (Si), passivated silicon (Si) surface) and the p-MOS cavity 408C (e.g., silicon germanium (SiGe)). During the deposition process, the deposition precursor preferentially reacts with the exposed surface of the p-MOS cavity 408C (e.g., silicon germanium (SiGe)) compared to the exposed surface of the n-MOS cavity 406C (e.g., silicon (Si), passivated silicon (Si) surface). Thus, the growth rate of the first metal material on the exposed surface of the p-MOS cavity 408C can be faster than that on the exposed surface of the n-MOS cavity 406C.

[0058] In some embodiments, the deposition gas used in the deposition process includes a metal source such as a molybdenum (Mo)-containing halide precursor or a ruthenium (Ru)-containing organometal containing ruthenium (Ru). The first selective deposition process can be performed at a temperature between about 240 °C and about 450 °C and a pressure between 3 Torr and 300 Torr. During the deposition process, for example, argon (Ar) gas can be supplied at a flow rate between about 0 sccm and about 1000 sccm, and hydrogen (H2) gas can be supplied at a flow rate between about 500 sccm and about 15000 sccm.

[0059] The cycle of the first selective deposition process can be repeated as needed to obtain a desired thickness of the p-MOS cavity contact 416, for example, between about 5 times and about 1000 times.

[0060] In block 340, a second selective deposition process is optionally performed to selectively form an n-MOS cavity contact 418 in the n-MOS cavity 406C, as Figure 4D shown. The second selective deposition process can be performed in a processing chamber such as Figure 1 the processing chambers 126, 128, or 130 shown. The second selective deposition process in block 340 can be performed without breaking the vacuum environment in the multi-chamber processing system (such as Figure 1 the multi-chamber processing system 100 shown).

[0061] The n-MOS cavity contact 418 can be formed of a second metal material such as titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), lanthanum (La), yttrium (Y), hafnium (Hf), zirconium (Zr), or a silicide thereof. The n-MOS cavity contact 418 interfaces with the n-MOS region 406 and the contact plug to be formed within the first trench 412 and provides an electrical connection therebetween.

[0062] In some embodiments, the second selective deposition process includes deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and similar processes. The selectivity in the second selective deposition process can be caused by the difference in the reaction of the deposition precursor of the second metal material (e.g., titanium (Ti)) with the exposed surface of the n-MOS cavity 406C (e.g., silicon (Si)) and the exposed surface of the p-MOS cavity contact 416 (e.g., molybdenum (Mo), ruthenium (Ru)). During the deposition process, the deposition precursor reacts preferentially with the exposed surface of the n-MOS cavity 406C (e.g., silicon (Si)) compared to the exposed surface of the p-MOS cavity contact 416 (e.g., molybdenum (Mo), ruthenium (Ru)), and the growth of the second metal material on the exposed surface of the n-MOS cavity 406C can be faster than the growth rate on the exposed surface of the p-MOS cavity contact 416 (e.g., molybdenum (Mo), ruthenium (Ru)).

[0063] In some embodiments, the deposition gas used in the deposition process includes metal sources such as precursors containing titanium (Ti), tantalum (Ta), cobalt (Co), nickel (Ni), and combinations thereof. The second selective deposition process can be performed at a temperature between about 300 °C and about 800 °C and a pressure between 1 torr and 50 torr.

[0064] In block 350, as Figure 4E shown, a conformal deposition process is performed to form a barrier metal layer 420 on the exposed inner surfaces of the first trench 412 and the second trench 414 and on the exposed surface of the dielectric layer 410. The barrier metal layer 420 protects the p-MOS cavity contact 416 and the n-MOS cavity contact 418 and allows the contact plug to nucleate and grow within the first trench 412 and the second trench 414. The barrier metal layer 420 can be formed of a barrier metal material that is titanium nitride (TiN) or tantalum nitride (TaN). In some embodiments, the n-MOS cavity contact 418 is a silicide layer formed from a portion of the barrier metal layer 420 by using a spike annealing process. The conformal deposition process in block 350 can be performed without breaking the vacuum environment in a multi-chamber processing system such as Figure 1 the multi-chamber processing system 100 shown.

[0065] In block 360, as Figure 4FAs shown, a metal filling process is performed to form a first contact plug 422 in the first trench 412 and a second contact plug 424 in the second trench 414. The first contact plug 422 and the second contact plug 424 may be formed of a contact plug metal material such as tungsten (W), cobalt (Co), ruthenium (Ru), or molybdenum (Mo). The first contact plug 422 and the second contact plug 424 may include a metal having a desired work function. The metal filling process in block 360 may include using a chemical vapor deposition (CVD) process with a tungsten precursor such as WF6 or a cobalt precursor in a processing chamber such as Figure 1 processing chambers 126, 128, or 130 as shown.

[0066] After the metal filling process, the semiconductor structure 400 may be planarized by using a chemical mechanical planarization (CMP) process.

[0067] The embodiments described herein provide methods and systems for forming electrical contacts comprising metal silicides (e.g., molybdenum silicide (MoSi2), ruthenium silicide (Ru x Si y )) within trenches on selected portions of a transistor structure. The contact trench structure includes metal contact plugs formed within trenches between adjacent device modules, and electrical contacts that mediate between the contact plugs and silicon-based channels in the device modules, thereby reducing parasitic resistance. The electrical contacts are formed by selective deposition. The electrical contacts may be metal silicides (e.g., molybdenum silicide (MoSi2), ruthenium silicide (Ru x Si y )) selectively formed in trenches of p-type MOS devices (e.g., silicon germanium), or metal silicides (e.g., titanium silicide (TiSi2)) selectively formed in trenches of n-type MOS devices. Due to the cavity forming process according to the embodiments described herein, in order to form a cavity within the trench, the contact interface area is increased, and the exposed surface of the cavity is optimized for selective deposition of metal silicide within the cavity.

[0068] Although the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be designed without departing from its basic scope, and its scope is determined by the claims that follow.

Claims

1. A method of forming electrical contacts in a semiconductor structure, the method comprising: Performing a cavity forming process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region and a p-type MOS (p-MOS) region, the cavity forming process comprising: forming an n-MOS cavity in an exposed surface of the n-MOS region and forming a p-MOS cavity in an exposed surface of the p-MOS region; and Performing a first selective deposition process to selectively form a p-MOS cavity contact in the p-MOS cavity.

2. The method according to claim 1, wherein The n-MOS region comprises silicon doped with an n-type dopant, and The p-MOS region comprises silicon germanium doped with a p-type dopant.

3. The method according to claim 2, wherein The cavity forming process comprises: An etching process using chlorine (Cl2) and hydrogen (H2).

4. The method according to claim 1, wherein The p-MOS cavity contact comprises a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru).

5. The method according to claim 1, the method further comprising: Before the cavity forming process, performing a pre-cleaning process, comprising: Removing carbon-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process using hydrogen (H) plasma; and Removing oxide-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process.

6. The method according to claim 1, the method further comprising: After the first selective deposition process, performing a second selective deposition process to selectively form an n-MOS cavity contact in the n-MOS cavity.

7. The method according to claim 6, wherein The n-MOS cavity contact comprises titanium silicide (Ti).

8. The method according to claim 1, wherein The first selective deposition process is performed without breaking the vacuum environment.

9. A method of forming electrical contacts in a semiconductor structure, the method comprising: Performing a pre-cleaning process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region, a p-type metal oxide semiconductor (p-MOS) region and a dielectric layer having a first trench above the n-MOS region and a second trench above the p-MOS region; Performing a cavity forming process to form an n-MOS cavity in an exposed surface of the n-MOS region within the first trench and a p-MOS cavity in an exposed surface of the p-MOS region within the second trench; Performing a first selective deposition process to selectively form a p-MOS cavity contact in the p-MOS cavity; Performing a second selective deposition process to selectively form an n-MOS cavity contact in the n-MOS cavity; Performing a conformal deposition process to form a barrier layer on the exposed inner surfaces of the first trench and the second trench and on the exposed surface of the dielectric layer; And A metal filling process is performed to form a first contact plug in the first trench and a second contact plug in the second trench.

10. The method according to claim 9, wherein the pre-cleaning process, the cavity forming process, the first selective deposition process, the second selective deposition process, and the conformal deposition process are performed without breaking the vacuum environment.

11. The method according to claim 9, wherein the n-MOS region comprises silicon doped with an n-type dopant, and the p-MOS region comprises silicon germanium doped with a p-type dopant.

12. The method according to claim 11, wherein the cavity forming process comprises: an etching process using chlorine (Cl2) and hydrogen (H2).

13. The method according to claim 9, wherein the p-MOS cavity contact comprises a material selected from molybdenum silicide (Mo) and ruthenium silicide (Ru), and the n-MOS cavity contact comprises titanium silicide (Ti).

14. The method according to claim 9, wherein the pre-cleaning process comprises: removing carbon-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process using hydrogen (H) plasma; and removing oxide-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process.

15. The method according to claim 9, wherein the barrier layer comprises titanium nitride (TiN) or tantalum nitride (TaN).

16. The method according to claim 9, wherein the first contact plug and the second contact plug comprise tungsten (W).

17. A processing system, the processing system comprising: a first processing chamber; a second processing chamber; and a system controller configured to cause the processing system to: in the first processing chamber, perform a cavity forming process on a semiconductor structure having an n-type metal oxide semiconductor (n-MOS) region and a p-type metal oxide semiconductor (p-MOS) region, the cavity forming process comprising forming an n-MOS cavity in the exposed surface of the n-MOS region and forming a p-MOS cavity in the exposed surface of the p-MOS region; and in the second processing chamber, perform a first selective deposition process to selectively form p-MOS cavity contacts in the p-MOS cavities.

18. The processing system according to claim 17, the processing system further comprising: a third processing chamber, wherein the system controller is further configured to: before the cavity forming process, perform a pre-cleaning process in the third processing chamber, the pre-cleaning process comprising: removing carbon-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process using hydrogen (H) plasma; and removing oxide-containing contaminants from the exposed surfaces of the n-MOS region and the p-MOS region by a dry etching process.

19. The processing system according to claim 17, the processing system further comprising: a fourth processing chamber, wherein the system controller is further configured to: After the first selective deposition process, a second selective deposition process is performed in the fourth processing chamber to selectively form n-MOS cavity contacts in the n-MOS cavity.

20. The processing system according to claim 17, wherein the system controller is further configured to cause the processing system to perform the cavity forming process and the first selective deposition process without breaking the vacuum environment.

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