Self-assembly substrate and display device

Abstract

The self-assembly substrate includes: a substrate; a first assembly wiring on the substrate; a second assembly wiring on the substrate; a partition wall located on the first assembly wiring and the second assembly wiring and having an assembly hole; a first uneven layer located on the partition wall and having a first uneven structure; and a dielectric coating layer on the partition wall and having a second uneven structure. The second concavo-convex structure has a shape corresponding to the shape of the first concavo-convex structure.

Description

Technical Field

[0001] The embodiments relate to a self-assembly substrate and a display device. Background Art

[0002] Large-area displays include liquid crystal displays (LCDs), organic light-emitting diode displays (OLEDs), and micro light-emitting diode displays (Micro-LED displays), etc.

[0003] A micro-LED display is a display that uses a semiconductor light-emitting element, i.e., a micro-LED with a diameter or cross-sectional area of 100 μm or less, as a display element.

[0004] Since the micro-LED display uses a semiconductor light-emitting element, i.e., a micro-LED, as a display element, it has excellent performance in many characteristics such as contrast ratio, response speed, color reproduction rate, viewing angle, brightness, resolution, lifespan, luminous efficiency, or luminance.

[0005] In particular, the micro-LED display can separate and combine the screen in a modular manner, so it has the advantages of freely adjusting the size or resolution and the advantage of enabling a flexible display.

[0006] However, a large-sized micro-LED display requires more than millions of micro-LEDs, so there is a technical problem that it is difficult to transfer the micro-LEDs to the display panel quickly and accurately.

[0007] Transfer technologies developed in recent years include a pick and place process, a Laser Lift-off method, or a self-assembly method, etc.

[0008] Among them, the self-assembly method is a method in which semiconductor light-emitting elements automatically find assembly positions in a fluid 1200, and it is a method that is beneficial for realizing a large-screen display device.

[0009] In order to realize a large-screen display device using the self-assembly method, the following two methods have been developed currently.

[0010] The first method is as follows: After assembling semiconductor light-emitting elements on an interposer substrate using the self-assembly method, the semiconductor light-emitting elements on the interposer substrate are transferred to a backplane substrate.

[0011] The second method is as follows: In the case of no interposer substrate, semiconductor light-emitting elements are directly self-assembled onto a backplane substrate using the self-assembly method.

[0012] Both the first method and the second method have the problem that the semiconductor light-emitting element is adsorbed onto the self-assembly substrate, i.e., the interposer substrate or the backplane substrate, during the self-assembly process. Due to composite factors such as van der Waals forces or surface tension acting between the semiconductor light-emitting element and the self-assembly substrate, the semiconductor light-emitting element cannot be assembled into the target area, such as the assembly hole, and is adsorbed onto an area other than the assembly hole.

[0013] In this way, when the semiconductor light-emitting element adsorbed on the self-assembly substrate is electrically connected through subsequent processes, problems such as disconnection or short-circuit of the electrode wiring occur, resulting in lighting defects or display defects. Summary of the Invention

[0014] Technical Problem

[0015] The object of the embodiment is to solve the above problems and other problems.

[0016] Another object of the embodiment is to provide a self-assembly substrate capable of preventing the adsorption defect that the semiconductor light-emitting element is adsorbed onto an area other than the assembly hole.

[0017] In addition, another object of the embodiment is to provide a self-assembly substrate capable of preventing lighting defects or display defects caused by the adsorption defect of the semiconductor light-emitting element.

[0018] The technical problem of the embodiment is not limited to the content described herein, but includes problems that can be grasped through the description of the invention.

[0019] Means for Solving the Technical Problem

[0020] To achieve the above or other objects, according to one aspect of the embodiment, the self-assembly substrate includes: a substrate; a first assembly wiring located on the substrate; a second assembly wiring located on the substrate; a partition wall located on the first assembly wiring and the second assembly wiring and having an assembly hole; a first uneven layer located on the partition wall and having a first uneven structure; and a dielectric covering layer located on the partition wall and having a second uneven structure, and the second uneven structure may have a shape corresponding to the shape of the first uneven structure.

[0021] The dielectric covering layer may be a superhydrophilic surface modification layer. The dielectric covering layer may be a protective layer. The dielectric covering layer may be an external light scattering layer.

[0022] The first uneven layer includes a plurality of bumps, and the plurality of bumps may be arranged on the upper surface of the partition wall.

[0023] The size of the bumps may be smaller than the size of the semiconductor light-emitting element. The interval between the bumps may be smaller than the size of the semiconductor light-emitting element.

[0024] Based on the separation distance from the above-mentioned assembly holes, the sizes of the above-mentioned plurality of bumps or the intervals between the above-mentioned plurality of bumps can be different. The size of the bumps located closer to the above-mentioned assembly holes can be larger than the size of the bumps located farther from the above-mentioned assembly holes. The interval between the bumps located closer to the above-mentioned assembly holes can be smaller than the interval between the bumps located farther from the above-mentioned assembly holes.

[0025] The above-mentioned dielectric covering layer can be disposed on the upper surface of the above-mentioned partition wall except for the above-mentioned assembly holes. The above-mentioned dielectric covering layer can be disposed on the inner side surface of the above-mentioned assembly holes.

[0026] The above-mentioned self-assembly substrate may include: a second uneven layer, which is located on the upper surface of each of the above-mentioned plurality of bumps and has a third uneven structure.

[0027] The above-mentioned second uneven layer can be disposed on the upper surface of the above-mentioned partition wall between the above-mentioned plurality of bumps. The above-mentioned third uneven structure can be a nano-texture.

[0028] The above-mentioned self-assembly substrate can be an interposer substrate or a backplane substrate.

[0029] According to another aspect of the embodiment, the display device can be manufactured using the above-mentioned self-assembly substrate.

[0030] Advantages of the Invention

[0031] According to the embodiment, as Figures 6 to 12 shown, the self-assembly substrate 401 can be an interposer substrate 200 or a backplane substrate 300A-300C. The interposer substrate 200 can be a substrate on which a plurality of semiconductor light-emitting elements 150R, 150G, 150B are aligned and arranged in units of pixels before being transferred onto the backplane substrate 300A-300C. The backplane substrates 300A-300C can be substrates on which electrical connections are formed after transferring a plurality of semiconductor light-emitting elements 150R, 150G, 150B in units of pixels, so that a display device can be manufactured.

[0032] As Figure 11 and Figure 12 shown, the self-assembly substrate 401 disposes a first uneven layer 450 having a first uneven structure 451 on the partition wall 440, and can dispose a dielectric covering layer 455 having a second uneven structure 456.

[0033] The dielectric covering layer 455 can be a super-hydrophilic surface modification layer, a protective layer, or an external light scattering layer.

[0034] As Figure 13As shown, when the dielectric coating layer 455 is used as a super-hydrophilic surface modification layer, during self-assembly, the plurality of semiconductor light-emitting elements 150R, 150G, and 150B that are being moved by the magnet 1100 do not adsorb to the partition wall 440 through the dielectric coating layer 455. Thus, it is possible to prevent defects caused by adsorption, such as disconnection or short-circuit of electrode wiring due to subsequent processes. Additionally, it is possible to prevent an increase in cost caused by adsorption.

[0035] As Figure 14 shown, when the dielectric coating layer 455 is used as a protective layer, even if the transfer substrate 270 is pressed on the self-assembly substrate 401, the pressure generated by the transfer substrate 270 is blocked by the dielectric coating layer 455, and the partition wall 440 can be protected.

[0036] As Figure 15 shown, when the dielectric coating layer 455 is used as an external light scattering layer, external light is scattered or diffused by the dielectric coating layer 455, so that the scattered external light does not face the eyes of the user. Therefore, it is possible to prevent the user from being dazzled.

[0037] On the other hand, in the embodiment, according to the separation distance from the assembly holes, the sizes of the respective plurality of bumps 450a or the intervals between the plurality of bumps 450a are different.

[0038] For example, as Figure 24 shown, the size D21 of the bump 450a located at a position close to the assembly holes 440H1 to 440H3 is larger than the size D21 of the bump 450a located at a position far from the assembly holes 440H1 to 440H3, thereby increasing the number of semiconductor light-emitting elements adsorbed to the position close to the assembly holes 440H1 to 440H3. Thus, due to the collision caused by the movement of the plurality of semiconductor light-emitting elements 150R, 150G, and 150B having a cluster unit in the periphery, at least one or more semiconductor light-emitting elements adsorbed to the position close to the assembly holes 440H1 to 440H3 fall off and are assembled into the adjacent assembly holes 440H1 to 440H3. Therefore, the assembly rate can be improved.

[0039] For example, as Figure 25As shown, the interval L1 between the bumps 450a located near the assembly holes 440H1 to 440H3 is smaller than the interval L1 between the bumps 450a located far from the assembly holes 440H1 to 440H3, so that the number of semiconductor light-emitting elements adsorbed near the assembly holes 440H1 to 440H3 can be increased. Thus, due to the collision caused by the movement of the surrounding multiple semiconductor light-emitting elements 150R, 150G, and 150B having a cluster unit, at least one or more semiconductor light-emitting elements adsorbed near the assembly holes 440H1 to 440H3 fall off and are assembled into the adjacent assembly holes 440H1 to 440H3, so that the assembly rate can be improved.

[0040] On the other hand, as Figure 27 shown, in the embodiment, a second uneven layer 457 having a third uneven structure 458 is disposed on the upper surface of each of the plurality of bumps 450a, so as to further reduce the adsorption possibility on the partition wall 440, thereby being able to prevent the lighting failure caused by the disconnection or short circuit of the electrode wiring due to poor adsorption.

[0041] The additional scope applicable to the embodiment can be clearly understood from the following detailed description. However, those skilled in the art can clearly understand various changes and modifications within the idea and scope of the embodiment. Therefore, the detailed description and specific embodiments such as the preferred embodiments are only illustrative. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 Shows the living room of a house where a display device according to an embodiment is disposed.

[0043] Figure 2 Is a block diagram schematically showing a display device according to an embodiment.

[0044] Figure 3 Is a circuit diagram showing an example of a pixel of Figure 2

[0045] Figure 4 Is Figure 1 An enlarged view of the first panel area in the display device of

[0046] Figure 5 Shows the process of assembling a semiconductor light-emitting element according to an embodiment to a self-assembly substrate by a self-assembly method.

[0047] Figure 6 Is a diagram for explaining a first method of manufacturing a display device according to an embodiment.

[0048] Figure 7 Is a cross-sectional view showing a transfer method using a transfer substrate 270 in the first method of manufacturing a display device according to an embodiment. ​

[0049] Figure 8 This is a diagram for explaining a second method of manufacturing a display device according to a manufacturing example.

[0050] Figure 9 This is a cross-sectional view showing a direct transfer method using a self-assembled substrate in a second method of manufacturing a display device according to a manufacturing example.

[0051] Figure 10 This is a diagram for explaining a third method of manufacturing a display device according to a manufacturing example.

[0052] Figure 11 This is a top view showing a self-assembled substrate of the first embodiment.

[0053] Figure 12 This is a cross-sectional view taken along the line C1-C2 of the self-assembled substrate of the first embodiment.

[0054] Figure 13 This shows a state where a semiconductor light-emitting element is not adsorbed onto the self-assembled substrate during self-assembly.

[0055] Figure 14 This shows a state where the partition walls of the backplane substrate are protected even when pressure is applied to the transfer substrate 270 through a transfer process.

[0056] Figure 15 This shows a state where external light is scattered during display.

[0057] Figure 16 This shows the sizes of the bumps of the first uneven layer and the size of the semiconductor light-emitting element in the embodiment.

[0058] Figure 17 This shows the interval between the bumps of the first uneven layer and the size of the semiconductor light-emitting element in the embodiment.

[0059] Figures 18 to 20 This shows a first method of manufacturing a self-assembled substrate of the first embodiment.

[0060] Figures 21 to 23 This shows a second method of manufacturing a self-assembled substrate of the first embodiment.

[0061] Figure 24 This is a top view showing a self-assembled substrate of the second embodiment.

[0062] Figure 25 This is a top view showing a self-assembled substrate of the third embodiment.

[0063] Figure 26 This is a cross-sectional view showing a self-assembled substrate of the fourth embodiment.

[0064] Figure 27It is a cross-sectional view showing the self-assembled substrate of the fifth embodiment.

[0065] Figure 28 Shows the adsorption rates in the comparative examples and the embodiments.

[0066] The sizes, shapes, numerical values, etc. of the components illustrated in the drawings may be different from the actual situation. Additionally, even if the same components are illustrated as having different sizes, shapes, numerical values, etc. between the drawings, this is only an illustration on the drawings, and the same components may have the same sizes, shapes, numerical values, etc. between the drawings. Detailed implementation manners

[0067] Hereinafter, with reference to the drawings, the embodiments disclosed in this specification will be described in detail. Irrespective of the drawing numbers, the same or similar components are given the same reference numerals, and repeated descriptions thereof are omitted. The ending words'module' and 'part' regarding the components used in the following description are given or mixed for the convenience of writing the specification, and they do not have a meaning or function of distinguishing from each other. Additionally, the drawings are used to assist in understanding the embodiments disclosed in this specification, and the technical ideas disclosed in this specification are not limited to the content in the drawings. Additionally, when referring to an element such as a layer, a region, or a substrate being 'on' another component, this means that it directly exists on the other component or there are other intermediate components in between.

[0068] The display devices described in this specification include TVs, in-vehicle display screens, mobile terminals such as mobile phones or smart phones, computer monitors such as laptop computers or desktop computers, automotive HUDs (head-Up Displays), backlight units for displays, XR (Extend Reality) displays such as AR, VR, MR (mixed Reality), light sources, etc. However, even for newly developed product forms in the future, the structures of the embodiments described in this specification can also be similarly applied to displayable devices.

[0069] Figure 1 Shows the living room of a house equipped with the display device of the embodiment.

[0070] Refer to Figure 1 , the display device 100 of the embodiment can display the states of various electronic products such as a washing machine 101, a robot vacuum cleaner 102, an air purifier 103, etc., can communicate with each electronic product based on the IOT substrate, and can also control each electronic product based on the set data of the user.

[0071] The display device 100 of the embodiment includes a flexible display manufactured on a thin and flexible substrate. While maintaining the characteristics of a conventional flat panel display, the flexible display can be bent or rolled up like paper.

[0072] In the flexible display, time information can be implemented by independently controlling the light emission of unit pixels arranged in a matrix form. A unit pixel refers to the smallest unit for representing one color. The unit pixels of the flexible display can be implemented by light-emitting elements. In the embodiment, the light-emitting element may be a micro LED or a nano LED, but is not limited thereto.

[0073] Figure 2 It is a block diagram schematically showing the display device of the embodiment, Figure 3 It shows Figure 2 An example circuit diagram of the pixel.

[0074] Referring to Figure 2 And Figure 3 The display device of the embodiment includes a display panel 10, a driving circuit 20, a scan driving unit 30, and a power supply circuit 50.

[0075] The display device 100 of the embodiment drives the light-emitting elements by an active matrix (AM) method or a passive matrix (PM) method.

[0076] The driving circuit 20 includes a data driving unit 21 and a timing control unit 22.

[0077] The display panel 10 may be configured as a right-angled quadrilateral, but is not limited thereto. That is, the display panel 10 may be formed into a circular or elliptical shape. At least one side of the display panel 10 is bent with a specified curvature.

[0078] The display panel may include a display area DA. The display area DA is an area where pixels PX are formed and an image is displayed. The display panel may include a non-display area NDA. The non-display area DNA may be an area other than the display area DA.

[0079] As an example, the display area DA and the non-display area NDA are defined on the same plane. For example, the non-display area DNA may be located on the same plane as the display area DA and surround the display area DA, but is not limited thereto.

[0080] As another example, although not illustrated in the drawings, the display area DA and the non-display area NDA may be defined on different surfaces. For example, the display area DA is defined on the upper surface of the substrate, and the non-display area NDA is defined on the lower surface of the substrate. For example, the non-display area NDA may also be defined on the entire area or a part of the area of the lower surface of the substrate.

[0081] On the other hand, although illustrated in the drawings as being divided into the display area DA and the non-display area NDA, it may not be divided into the display area DA and the non-display area NDA. That is, only the display area DA may be formed on the upper surface of the substrate without forming the non-display area NDA. That is, the entire area of the upper surface of the substrate is the display area DA for displaying an image, and there may be no border area as the non-display area NDA.

[0082] The display panel 10 may include data lines D1 to Dm (m is an integer of 2 or more), scan lines S1 to Sn (n is an integer of 2 or more) intersecting the data lines D1 to Dm, a high potential voltage line VDDL for supplying a high potential voltage VDD, a low potential voltage line VSSL for supplying a low potential voltage VSS, and pixels PX connected to the data lines D1 to Dm and the scan lines S1 to Sn.

[0083] Each of the pixels PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 emits first color light having a first main wavelength, the second sub-pixel PX2 emits second color light having a second main wavelength, and the third sub-pixel PX3 emits third color light having a third main wavelength. The first color light may be red light, the second color light may be green light, and the third color light may be blue light, but is not limited thereto. In addition, Figure 2 The case where each of the pixels PX includes 3 sub-pixels is illustrated, but is not limited thereto. That is, each of the pixels PX may include 4 or more sub-pixels.

[0084] Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may be connected to at least one of the data lines D1 to Dm, at least one of the scan lines S1 to Sn, and the high potential voltage line VDDL. As Figure 3 shown, the first sub-pixel PX1 may include a light-emitting element LD, a plurality of transistors for supplying current to the light-emitting element LD, and at least one capacitor Cst.

[0085] Although not illustrated, each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include only one light-emitting element LD and at least one capacitor Cst.

[0086] Each of the light-emitting elements LD may be a semiconductor light-emitting diode including a first electrode 154, a plurality of conductive-type semiconductor layers, and a second electrode 155. Here, the first electrode 154 may be an anode electrode, and the second electrode 155 may be a cathode electrode, but is not limited thereto.

[0087] The light-emitting element LD may be one of a horizontal-type light-emitting element, a flip-chip type light-emitting element, and a vertical-type light-emitting element.

[0088] As Figure 3 shown, the plurality of transistors include a driving transistor DT that supplies current to the light-emitting element LD, and a scanning transistor ST that supplies a data voltage to the gate electrode of the driving transistor DT. The driving transistor DT includes a gate electrode connected to the source electrode of the scanning transistor ST, a source electrode connected to a high potential voltage line VDDL to which a high potential voltage VDD is applied, and a drain electrode connected to the first electrode 154 of the light-emitting element LD. The scanning transistor ST includes a gate electrode connected to a scanning line Sk (k is an integer satisfying 1 ≤ k ≤ n), a source electrode connected to the gate electrode of the driving transistor DT, and a drain electrode connected to a data line Dj (j is an integer satisfying 1 ≤ j ≤ m).

[0089] A capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst is charged with the difference between the gate voltage and the source voltage of the driving transistor DT.

[0090] The driving transistor DT and the scanning transistor ST may be formed of thin film transistors. Additionally, Figure 3 the case where the driving transistor DT and the scanning transistor ST are formed of P-type MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) is mainly described in, but the present invention is not limited thereto. The driving transistor DT and the scanning transistor ST may also be formed of N-type MOSFETs. In this case, the positions of the source electrodes and the drain electrodes of the driving transistor DT and the scanning transistor ST may be changed.

[0091] Additionally, Figure 3 the case where each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 includes a 2T1C (2 transistors - 1 capacitor) having one driving transistor DT, one scanning transistor ST, and one capacitor Cst is illustrated in, but the present invention is not limited thereto. Each of the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 may include a plurality of scanning transistors ST and a plurality of capacitors Cst.

[0092] The second sub-pixel PX2 and the third sub-pixel PX3 can be represented by substantially the same circuit diagram as the first sub-pixel PX1, and thus a detailed description thereof is omitted.

[0093] The driving circuit 20 outputs signals and voltages for driving the display panel 10. To this end, the driving circuit 20 includes a data driving unit 21 and a timing control unit 22.

[0094] The data driving unit 21 receives digital video data DATA and a source control signal DCS from the timing control unit 22. The data driving unit 21 converts the digital video data DATA into an analog data voltage according to the source control signal DCS and supplies it to the data lines D1 to Dm of the display panel 10.

[0095] The timing control unit 22 receives digital video data DATA and timing signals from the host system. The host system may be an application processor of a smart phone or a tablet PC, a monitor, a system-on-chip of a TV, etc.

[0096] The timing control unit 22 generates control signals for controlling the operation timings of the data driving unit 21 and the scan driving unit 30. The control signals include a source control signal DCS for controlling the operation timing of the data driving unit 21 and a scan control signal SCS for controlling the operation timing of the scan driving unit 30.

[0097] The driving circuit 20 may be disposed in a non-display area NDA provided on one side of the display panel 10. The driving circuit 20 is formed of an integrated circuit (IC) and is mounted on the display panel 10 by a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but the present invention is not limited thereto. For example, the driving circuit 20 may be mounted on a circuit board (not shown) instead of on the display panel 10.

[0098] The data driving unit 21 is mounted on the display panel 10 by a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, and the timing control unit 22 is mounted on a circuit board.

[0099] The scan driving unit 30 receives a scan control signal SCS from the timing control unit 22. The scan driving unit 30 generates scan signals according to the scan control signal SCS and supplies them to the scan lines S1 to Sn of the display panel 10. The scan driving unit 30 includes a plurality of transistors and may be formed in the non-display area NDA of the display panel 10. Alternatively, the scan driving unit 30 may be formed of an integrated circuit, and in this case, it may be mounted on a gate flexible film attached to the other side of the display panel 10.

[0100] The power supply circuit 50 generates the voltages required for driving the display panel 10 from the main power supply applied by the system board and supplies them to the display panel 10. For example, the power supply circuit 50 generates the high-potential voltage VDD and the low-potential voltage VSS for driving the light-emitting elements LD of the display panel 10 from the main power supply and supplies them to the high-potential voltage line VDDL and the low-potential voltage line VSSL of the display panel 10. In addition, the power supply circuit 50 generates a driving voltage for driving the driving circuit 20 and the scan driving unit 30 from the main power supply and supplies it.

[0101] Figure 4 is Figure 3 An enlarged view of the first panel area in the display device.

[0102] Refer to Figure 4 , the display device 100 of the embodiment is manufactured by mechanically connecting and electrically connecting a plurality of panel areas such as the first panel area A1 in a tiling manner.

[0103] The first panel area A1 includes a plurality of semiconductor light-emitting elements 150 arranged according to each unit pixel ( Figure 2 PX).

[0104] Next, with reference to Figures 5 to 28 , various embodiments for solving the above problems will be described. Regarding the descriptions omitted below, they can be easily understood from Figures 1 to 4 and the above descriptions related to these drawings.

[0105] In the embodiment, the self-assembly substrates 401 to 405 are substrates for assembling semiconductor light-emitting elements using the self-assembly method developed by the applicant. The self-assembly substrates 401 to 405 can be used as the interposer substrate 200 or the backplane substrates 300A to 300C.

[0106] The interposer substrate 200 can be a substrate on which semiconductor light-emitting elements corresponding to a plurality of sub-pixels of each of a plurality of pixels are assembled using the self-assembly method. Thereafter, the semiconductor light-emitting elements assembled on the interposer substrate 200 are transferred onto the backplane substrates 300A to 300C.

[0107] The backplane substrates 300A to 300C can be substrates on which semiconductor light-emitting elements corresponding to a plurality of sub-pixels of each of a plurality of pixels are assembled using the self-assembly method. Thereafter, the display device can be manufactured through a post-process for forming electrical connections of the semiconductor light-emitting elements assembled on the backplane substrates 300A to 300C.

[0108] First, the self-assembly method of the embodiment will be described.

[0109] Figure 5A process of assembling a semiconductor light-emitting element of an embodiment to a self-assembly substrate by a self-assembly method.

[0110] As Figure 5 shown, the semiconductor light-emitting element 150 can be put into the cavity 1300 filled with the fluid 1200. The fluid 1200 can be water such as ultrapure water, but is not limited thereto. The cavity 1300 can be referred to as a water tank, a box, a container, etc. The semiconductor light-emitting element 150 can include a first semiconductor light-emitting element 150R, a second semiconductor light-emitting element 150G, and a third semiconductor light-emitting element 150B. In such a case, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B can be put into the fluid 1200 or only one semiconductor light-emitting element among the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B can be put into the fluid 1200. The semiconductor light-emitting element 150 can include an electrode. The electrode can include a magnetic layer. The magnetic layer can be magnetized by the magnet 1100, so that the semiconductor light-emitting element 150 moves toward the magnet 1100.

[0111] The self-assembly substrate 400 can be fixed to the upper side of the cavity 1300. Although not shown, the self-assembly substrate 400 can also be fixed to the lower side of the cavity 1300.

[0112] The magnet 1100 can move from the rear of the self-assembly substrate 400 toward a predetermined direction. The magnet 1100 can move in the x-axis, Y-axis, and z directions. The magnet 1100 can perform rotational movement or zigzag movement. For example, the magnet 1100 can move parallel to the surface of the self-assembly substrate 400. The magnet 1100 can be in contact with or near the upper surface of the self-assembly substrate 400. In such a case, the magnetic field of the magnet 1100 may have an impact on the inside of the fluid 1200. Thereby, the semiconductor light-emitting element 150 in the fluid 1200 moves toward the magnet 1100 and can move along the inner side surface of the self-assembly substrate 400. In such a case, the semiconductor light-emitting element 150 can pass through the assembly holes 440H1 to 440H3 of the self-assembly substrate 400. At this time, through the dielectrophoretic force (hereinafter, referred to as the DEP force) formed by the assembly wiring of the self-assembly substrate 400, the semiconductor light-emitting element 150 is assembled to the assembly holes 440H1 to 440H3.

[0113] Next, with reference to Figures 6 to 9 , the manufacturing process of a display using the intermediate layer substrate 200 will be described.

[0114] Figure 6 It is a diagram for explaining a first method of manufacturing a display device of an embodiment.

[0115] As Figure 6As shown, a plurality of first semiconductor light-emitting elements 150R (S111) can be manufactured, a plurality of second semiconductor light-emitting elements 150G (S112) can be manufactured, and a plurality of third semiconductor light-emitting elements 150B (S113) can be manufactured.

[0116] Specifically, the plurality of first semiconductor light-emitting elements 150R, the plurality of second semiconductor light-emitting elements 150G, and the plurality of third semiconductor light-emitting elements 150B can be manufactured independently of each other. The first semiconductor light-emitting element 150R, the second semiconductor light-emitting element 150G, and the third semiconductor light-emitting element 150B can each emit light of different colors from each other. For example, the first semiconductor light-emitting element 150R includes a red semiconductor light-emitting element, the second semiconductor light-emitting element 150G includes a green semiconductor light-emitting element, and the third semiconductor light-emitting element 150B includes a blue semiconductor light-emitting element.

[0117] In an embodiment, the first semiconductor light-emitting element 150R, the second semiconductor light-emitting element 150G, and the third semiconductor light-emitting element 150B can each be a vertical-type semiconductor light-emitting element, but this is not limited thereto. In the vertical-type semiconductor light-emitting element, electrodes can be provided on the upper side and / or the lower side of the light-emitting layer 150a.

[0118] For example, a series of semiconductor processes are performed on a first wafer, thereby manufacturing a plurality of first semiconductor light-emitting elements 150R. For example, a series of semiconductor processes are performed on a second wafer, thereby manufacturing a plurality of second semiconductor light-emitting elements 150G. For example, a series of semiconductor processes are performed on a third wafer, thereby manufacturing a plurality of third semiconductor light-emitting elements 150B.

[0119] On the other hand, the plurality of first semiconductor light-emitting elements 150R, the plurality of second semiconductor light-emitting elements 150G, and the plurality of third semiconductor light-emitting elements 150B can be assembled onto the interposer substrate 200 by a self-assembly method (S120).

[0120] That is, the plurality of first semiconductor light-emitting elements 150R, the plurality of second semiconductor light-emitting elements 150G, and the plurality of third semiconductor light-emitting elements 150B are put into the fluid 1200, and after the interposer substrate 200 is located behind the fluid 1200, the plurality of first semiconductor light-emitting elements 150R, the plurality of second semiconductor light-emitting elements 150G, and the plurality of third semiconductor light-emitting elements 150B are assembled onto the interposer substrate 200 by using a magnetic field and an electric field. The magnet 1100 generates a magnetic field, which is located outside the interposer substrate 200 and can be moved parallel to the interposer substrate 200. The electric field can be formed by applying an alternating voltage to a pair of assembly wirings provided on the interposer substrate 200. The DEP force can be formed by such an electric field. The first assembly wiring 221 and the second assembly wiring 222 are provided on the interposer substrate 200 in order to apply the alternating voltage.

[0121] For example, through a magnetic field, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B can move to desired positions on the interposer substrate 200. Through DEP force, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B can be assembled to desired positions on the interposer substrate 200.

[0122] On the other hand, by using a stamp 271 transfer method, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B on the interposer substrate 200 can be transferred onto the backplane substrate 300A (S130).

[0123] As Figure 7 shown in a of, after the transfer substrate 270 having a plurality of stamps 271 is placed on the interposer substrate 200, it is aligned with the interposer substrate 200. Then, the interposer substrate 200 descends and is pressed and then rises, so that a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B on the interposer substrate 200 can be transferred onto the transfer substrate 270. For example, one semiconductor light-emitting element or a plurality of semiconductor light-emitting elements 150R, 150G, 150B are adhered to each of the plurality of stamps 271.

[0124] As Figure 7 shown in b of, the transfer substrate 270 can move onto the backplane substrate 300A and be aligned with the backplane substrate 300A.

[0125] As Figure 7 shown in c of, the transfer substrate 270 descends and is pressed and then rises, so that a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B on the transfer substrate 270 are transferred onto the backplane substrate 300A.

[0126] An adhesive layer 350 is disposed on the backplane substrate 300A, and the adhesive force of the adhesive layer 350 is greater than the adhesive force of the stamp 271 of the transfer substrate 270. Thus, when the transfer substrate 270 is pressed onto the backplane substrate 300A and then separated, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B are transferred onto the adhesive layer 350 of the backplane substrate 300A with a greater adhesive force.

[0127] As described above, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B that emit different color lights are aligned and arranged at once in such a manner as to form pixels on the interposer substrate 200, and then the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B aligned and arranged on the interposer substrate 200 are transferred to the corresponding pixels of the backplane substrate 300A by using the transfer substrate 270.

[0128] According to the size of the transfer substrate 270, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B corresponding to a number of pixels are simultaneously transferred to the backplane substrate 300A at once. For example, when 1000 pixels are defined on the backplane substrate 300A and the transfer substrate 270 has a size corresponding to 500 pixels, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B can be transferred to each of all the pixels of the backplane substrate 300A through two transfer processes. That is, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B included in 500 pixels are transferred to the backplane substrate 300A through the first transfer process, and then the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B included in the remaining 500 pixels are transferred to the backplane substrate 300A through the second transfer process. After that, the upper sides of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are connected to the electrode wirings, thereby enabling the manufacture of a display device.

[0129] Figure 8 It is a diagram for explaining a second method of manufacturing the display device of the manufacturing example.

[0130] Figure 8 Among them, S141 to S143 are the same as Figure 7 S111 to S113 of, and thus detailed descriptions thereof are omitted.

[0131] Through a self-assembly process, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B can be assembled onto the interposer substrate 200 (S150).

[0132] After that, differently from Figure 7 As Figure 8As shown, it is directly transferred onto the backplane substrate 300B by using the interposer substrate 200. That is, after the interposer substrate 200 is flipped, it is moved onto the backplane substrate 300B. Then, the interposer substrate 200 descends and is pressed onto the backplane substrate 300B and heated, so that the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B on the interposer substrate 200 are transferred onto the backplane substrate 300B. At the same time, by being heated, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are respectively bonded to the electrode wirings 311 of the backplane substrate 300B. The electrode wirings 311 are, for example, cathode electrodes, but are not limited thereto. In such a case, an anode electrode (not shown) is commonly connected to the upper sides of the semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B as a common electrode.

[0133] As Figure 9 shown in a of, after the interposer substrate 200 is flipped, it is moved onto the backplane substrate 300B.

[0134] Then, the interposer substrate 200 descends, is pressed, and then rises, so that the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B on the interposer substrate 200 can be transferred onto the backplane substrate 300B.

[0135] The electrode wirings 311, that is, cathode electrodes, may be provided on the backplane substrate 300B. In such a case, the interposer substrate 200 presses the backplane substrate 300B and can be heated. Through such heat, the electrodes provided on the lower sides of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B can be electrically connected to the electrode wirings 311. This electrode is melted by heat as solder, and this electrode can be bonded to the electrode wirings 311 as solder. Then, another electrode wiring, that is, an anode electrode, is commonly connected to the upper sides of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B, so that a display device can be manufactured.

[0136] As described above, the interposer substrate 200 functions as the transfer substrate 270, so Figure 7 the transfer substrate 270 shown can be omitted. At the same time, since the transfer process and the bonding process are performed simultaneously, the process is simple and the process time can be significantly shortened.

[0137] Then, with reference to Figure 10 the manufacturing process of the display using the backplane substrate 300C will be described.

[0138] Figure 10 is a diagram for explaining the third method of manufacturing the display device of the manufacturing example.

[0139] Figure 10S171 to S173 in are the same as S111 to S113 of Figure 7 , and thus detailed descriptions thereof are omitted.

[0140] Through the self-assembly process, a plurality of first semiconductor light-emitting elements 150R, a plurality of second semiconductor light-emitting elements 150G, and a plurality of third semiconductor light-emitting elements 150B can be assembled onto the backplane substrate 300C (S180). Thereafter, through a post-process, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B assembled onto the backplane substrate are electrically connected respectively, thereby enabling the manufacture of a display device.

[0141] Next, with reference to Figures 11 to 28 various embodiments of the self-assembly substrate will be described.

[0142] In the following description, the self-assembly substrate may be an interposer substrate ( Figures 6 to 9 200) or a backplane substrate ( Figure 10 300C).

[0143] [First Embodiment]

[0144] Figure 11 is a top view showing the self-assembly substrate of the first embodiment. Figure 12 is a cross-sectional view taken along the line C1-C2 of the self-assembly substrate of the first embodiment.

[0145] With reference to Figure 11 and Figure 12 , the self-assembly substrate 401 of the first embodiment includes a substrate 410, a first assembly wiring 421, a second assembly wiring 422, a partition wall 440, a first uneven layer 450, and a dielectric covering layer 455.

[0146] The substrate 410 may be a support substrate for supporting components of the self-assembly substrate 401 of the first embodiment, such as a plurality of first assembly wirings 421, a plurality of second assembly wirings 422, the partition wall 440, etc. The substrate 410 may be made of a plastic material, a ceramic material, glass, etc., but is not limited thereto.

[0147] A plurality of pixels PX may be defined on the substrate 410. Each of the plurality of pixels PX includes a plurality of sub-pixels PX1 to PX3. For example, when the substrate 410 is a base substrate for an interposer substrate, the size of the pixels on the substrate 410 may be the same as the size of the pixels defined on the backplane substrate. At this time, the pixels defined on the backplane substrate may be unit pixels for a display. For example, when the substrate 410 is a base substrate for a backplane substrate, the pixels on the substrate 410 themselves may be unit pixels for a display.

[0148] The first assembly wiring 421 is disposed on the substrate 410. The second assembly wiring 422 is disposed on the substrate 410. The first assembly wiring 421 and the second assembly wiring 422 are disposed on the same layer, i.e., the substrate 410. Although not shown, the first assembly wiring 421 and the second assembly wiring 422 may be disposed on different layers, and the first assembly wiring 421 and the second assembly wiring 422 are insulated by the insulating layer 430. When the first assembly wiring 421 and the second assembly wiring 422 are disposed on different layers, the interval between the first assembly wiring 421 and the second assembly wiring 422 is minimized, thereby enabling the arrangement of semiconductor light-emitting elements with ultra-high resolution.

[0149] The first assembly wiring 421 and the second assembly wiring 422 are disposed in the sub-pixels PX1 to PX3 of the respective pixels. For example, the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3 each include the first assembly wiring 421 and the second assembly wiring 422. The first assembly wiring 421 and the second assembly wiring 422 generate a DEP force to assemble the corresponding semiconductor light-emitting element into the corresponding sub-pixels PX1 to PX3.

[0150] For example, the first semiconductor light-emitting element 150R is assembled on the first sub-pixel PX1 by the DEP force generated by the first assembly wiring 421 and the second assembly wiring 422 on the first sub-pixel PX1. For example, the second semiconductor light-emitting element 150G is assembled on the second sub-pixel PX2 by the DEP force generated by the first assembly wiring 421 and the second assembly wiring 422 on the second sub-pixel PX2. For example, the third semiconductor light-emitting element 150B is assembled on the third sub-pixel PX3 by the DEP force generated by the first assembly wiring 421 and the second assembly wiring 422 on the third sub-pixel PX3.

[0151] The partition wall 440 is disposed on the first assembly wiring 421 and the second assembly wiring 422. The partition wall 440 has a plurality of assembly holes 440H1 to 440H3. The plurality of assembly holes 440H1 to 440H3 respectively facilitate the assembly of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B and prevent them from easily detaching. The assembly holes 440H1 to 440H3 are formed to penetrate the upper surface and the lower surface of the partition wall 440.

[0152] The multiple assembly holes 440H1 to 440H3 have different shapes and / or sizes from each other. For example, the first assembly hole 340H1 is circular, and the second assembly hole 340H2 and the third assembly hole 340H3 are elliptical respectively. The major axis size of the ellipse of the third assembly hole 340H3 is larger than the major axis size of the ellipse of the second assembly hole 340H2, and the minor axis size of the ellipse of the third assembly hole 340H3 is smaller than the minor axis size of the ellipse of the second assembly hole 340H2. For example, the diameter of the circle of the first assembly hole 340H1 is D11, the length of the major axis of the second assembly hole 340H2 is D12, and the length of the major axis of the third assembly hole 340H3 is D13. In such a case, the length D13 of the major axis of the third assembly hole 340H3 is longer than the length D12 of the major axis of the second assembly hole 340H2, and the length D12 of the major axis of the second assembly hole 340H2 is larger than the diameter D11 of the first assembly hole 340H1.

[0153] In this way, the difference among the first assembly hole 340H1 to the third assembly hole 340H3 means the exclusive difference among the first assembly hole 340H1 to the third assembly hole 340H3. Through such exclusive differences, misassembly of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B is prevented. That is, misassembly that the first semiconductor light-emitting element 150R is assembled into the second assembly hole 340H2 or the third assembly hole 340H3 does not occur, but it is correctly assembled into the first assembly hole 340H1. Similarly, misassembly that the second semiconductor light-emitting element 150G is assembled into the first assembly hole 340H1 or the third assembly hole 340H3 does not occur, but it is correctly assembled into the second assembly hole 340H2.

[0154] The first uneven layer 450 is disposed on the partition wall 440. The first uneven layer 450 has a first uneven structure 451. The first uneven layer 450 has a plurality of bumps 450a. The plurality of bumps 450a are disposed on the partition wall 440. The bumps 450a may also be referred to as patterns. In the drawings, the bumps 450a are illustrated as circular, but they may also be other shapes. The plurality of bumps 450a are spaced apart from each other. The bumps may be referred to as uneven portions, patterns, protrusions, protruding portions, protruding regions, etc.

[0155] On the partition wall 440, a first uneven structure is formed by the spaced-apart spaces between the plurality of bumps 450a and the plurality of bumps 450a. The upper surface of the partition wall 440 is exposed through this spaced-apart space.

[0156] As Figure 16 shown, the size D21 of the bump 450a is smaller than the size D22 of the semiconductor light-emitting element, thereby reducing the overlapping area between the semiconductor light-emitting element and the bump 450a and preventing the semiconductor light-emitting element from being adsorbed to the self-assembly substrate 401.

[0157] AsFigure 17 As shown, the interval L1 between the bumps 450a is smaller than the size D22 of the semiconductor light-emitting element, thereby preventing the semiconductor light-emitting element from being caught between the bumps 450a and unable to disengage, which is an undesirable situation.

[0158] The dielectric coating layer 455 is disposed on the partition wall 440. The dielectric coating layer 455 is made of a material having a dielectric constant. For example, the dielectric coating layer 455 includes inorganic substances such as SiOx and SiNx.

[0159] The dielectric coating layer 455 has a second uneven structure 456. At this time, the second uneven structure 456 has a shape corresponding to the shape of the first uneven structure 451.

[0160] In the embodiment, the thickness t2 of the dielectric coating layer 455 can be very thin. For example, the thickness t2 of the dielectric coating layer 455 is thinner than the thickness t1 of the insulating layer 430 described later. For example, the thickness t2 of the dielectric coating layer 455 is several nanometers to several tens of nanometers.

[0161] For example, the thickness t2 of the dielectric coating layer 455 is thinner than the thickness t3 of the bump 450a. The dielectric coating layer 455 is disposed on the upper surface of the partition wall 440. The dielectric coating layer 455 is disposed on each of the plurality of bumps 450a of the first non-uniform layer. In such a case, the dielectric coating layer 455 is disposed on the upper surface of the partition wall 440 and the upper surface of the bump 450a with a thickness t2 thinner than the thickness t3 of the bump 450a, so that the dielectric coating layer 455 can have a shape corresponding to the shape of the first uneven structure 451 of the first non-uniform layer.

[0162] In the embodiment, the dielectric coating layer 455 can have various composite functions.

[0163] First, the dielectric coating layer 455 can be a super-hydrophilic surface modification layer. Therefore, when the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are assembled on the self-assembly substrate 401 of the first embodiment through a self-assembly process, as Figure 13 shown, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are not adsorbed through the dielectric coating layer 455.

[0164] For self-assembly, when the self-assembly substrate 401 of the first embodiment contacts the fluid 1200 and performs self-assembly, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B move through the magnet 1100. At this time, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B attempt to be adsorbed to the partition wall 440 through van der Waals force or surface tension.

[0165] The dielectric coating layer 455 covering the partition wall 440 is a super-hydrophilic surface modification layer. Therefore, the adsorption of the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B is prevented by the dielectric coating layer 455. As a result, the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are not adsorbed onto the partition wall 440, thereby preventing defects caused by adsorption, such as disconnection or short-circuit of electrode wirings due to subsequent processes. In addition, an increase in cost caused by adsorption can be prevented. Here, the increase in cost can refer to an increase in cost due to an increase in the number of semiconductor light-emitting elements wasted by adsorption. That is, the semiconductor light-emitting elements wasted by adsorption are not collected and thus cannot be reused and are discarded, thereby causing an increase in cost due to the waste of semiconductor light-emitting elements. Therefore, as the adsorption on the partition wall 440 is reduced, the increase in cost can be reduced.

[0166] As Figure 28 shown, compared with the comparative example without the dielectric coating layer 455, the chip adsorption rate can be significantly reduced in the embodiment with the dielectric coating layer 455. That is, in the comparative example, as the self-assembly substrate 401 is reused, the chip adsorption rate increases according to the number of times of reuse. On the contrary, in the embodiment, it is known that the chip adsorption rate is constant and very low regardless of the number of times of reuse of the self-assembly substrate 401.

[0167] Second, the dielectric coating layer 455 can be a protective layer. When the self-assembly substrate 401 of the first embodiment is used as the intermediate layer substrate 200, as Figure 6 and Figure 7 shown, for the transfer process, the transfer substrate 270 presses on the intermediate layer substrate 200. In such a case, due to the pressure generated by the pressing of the transfer substrate 270, the partition wall 440 may be damaged. However, in the embodiment, the dielectric coating layer 455 covers the partition wall 440 and functions as a protective layer. Therefore, as Figure 14 shown, even when the transfer substrate 270 is pressed on the self-assembly substrate 401 of the first embodiment, the pressure applied by the transfer substrate 270 can be blocked by the dielectric coating layer 455, and the partition wall 440 can be protected.

[0168] Third, the dielectric coating layer 455 can be an external light scattering layer. Here, the external light includes natural light such as sunlight and artificial light such as illumination. When the self-assembly substrate 401 of the first embodiment is used as the backplane substrate, after the first semiconductor light-emitting element 150R to the third semiconductor light-emitting element 150B are assembled on the backplane substrate, electrical connection is performed through subsequent processes, thereby enabling the manufacture of a display device.

[0169] The display device is commercialized and available for users. When a user views an image through the display device in the wild with strong sunlight or under illumination, external light such as such sunlight or light generated by the illumination may be reflected, which may cause problems such as glare. However, in the embodiment, the dielectric coating layer 455 has a second concavo-convex structure 456 as an external light scattering layer. Therefore, as Figure 15 shown, the external light is scattered or diffused by the dielectric coating layer 455, so that the scattered external light does not shoot into the user's eyes, and thus it is possible to prevent the user from being dazzled.

[0170] On the other hand, the self-assembled substrate 401 of the first embodiment includes an insulating layer 430. The insulating layer 430 is disposed on the first assembly wiring 421 and the second assembly wiring 422, thereby being able to protect the first assembly wiring 421 and the second assembly wiring 422. When self-assembling, the fluid 1200 is filled into the assembly holes 440H1 to 440H3. Therefore, when the insulating layer 430 is omitted, the first assembly wiring 421 and the second assembly wiring 422 are corroded by the fluid 1200. In addition, pressure is generated by the pressing in the transfer process, and through this pressure, the first assembly wiring 421 and the second assembly wiring 422 may be distorted or broken. Thus, the insulating layer 430 is disposed on the first assembly wiring 421 and the second assembly wiring 422, thereby being able to solve the above problems. In addition, the insulating layer 430 has a dielectric constant, which helps to generate the DEP force.

[0171] On the other hand, in the first embodiment, the dielectric coating layer 455 is disposed not only on the partition wall 440 but also in the assembly holes.

[0172] The dielectric coating layer 455 is a super-hydrophilic surface modification layer. Therefore, when self-assembling, it may be difficult to fix the semiconductor light-emitting element into the assembly holes 440H1 to 440H3. That is, the semiconductor light-emitting element assembled into the assembly holes 440H1 to 440H3 is prevented from being adsorbed due to the dielectric coating layer 455 in the assembly holes 440H1 to 440H3, and thus may come off outside the assembly holes 440H1 to 440H3. To solve such a problem, the dielectric coating layer may not be disposed in the assembly holes. That is, the dielectric coating layer 455 may be disposed on the upper surface of the partition wall 440 except for the assembly holes 440H1 to 440H3.

[0173] On the other hand, when the semiconductor light-emitting element assembled in the assembly holes 440H1 to 440H3 is sufficiently fixed by the DEP force, the dielectric coating layer 455 may also be disposed in the assembly holes 440H1 to 440H3.

[0174] Next, a method for manufacturing the self-assembled substrate will be described with reference to Figures 18 to 20 .

[0175] Figures 18 to 20 Shows a first method of manufacturing a self-assembled substrate of the first embodiment. Figures 18 to 20 Shows a method of manufacturing a self-assembled substrate corresponding to the first sub-pixel PX1. However, the manufacturing methods of the self-assembled substrates corresponding to the second sub-pixel PX2 and the third sub-pixel PX3 are also the same as Figures 18 to 20 the method of manufacturing the self-assembled substrate corresponding to the first sub-pixel PX1 illustrated in

[0176] As Figure 18 shown, a series of processes are sequentially performed to form a partition wall 440 having an assembly hole 440H1. Here, the assembly hole 440H1 may be a first assembly hole 340H1.

[0177] Specifically, first, there is a substrate 410. First assembly wirings 421 and second assembly wirings 422 spaced apart from each other are formed on the substrate 410. An insulating layer 430 is formed on the first assembly wirings 421 and the second assembly wirings 422, and a partition wall 440 is formed on the insulating layer 430. After that, a part of the area corresponding to the first sub-pixel PX1 in the partition wall 440 is removed to form an assembly hole 440H1. That is, a part of the partition wall 440 is removed to expose the insulating layer 430, thereby forming an assembly hole 440H1. In such a case, the bottom surface of the assembly hole 440H1 may be the upper surface of the insulating layer 430.

[0178] As Figure 19 illustrated, a first uneven layer 450 is formed on the partition wall 440.

[0179] Specifically, first, a photosensitive film including a photosensitive polymer is coated on the partition wall 440. After that, the photosensitive film is patterned through an exposure process and a development process to form a first uneven layer 450. The first uneven layer 450 has a first uneven structure 451 including a plurality of bumps 450a. The first uneven layer 450 is formed on the partition wall 440. That is, the exposure process and the development process are performed to remove the photosensitive film formed in the assembly hole 440H1. As Figure 16 and Figure 17 shown, the size D21 of the bump 450a is smaller than the size D22 of the semiconductor light-emitting element, and the interval L1 between the bumps 450a is smaller than the size D22 of the semiconductor light-emitting element, so as to prevent the semiconductor light-emitting element from being clamped between these bumps 450a during subsequent self-assembly.

[0180] The first uneven layer 450 may be made of the same material as the partition wall 440. For example, the first uneven layer 450 and the partition wall 440 include a photosensitive polymer. However, the first uneven layer 450 and the partition wall 440 may be different layers. That is, the partition wall 440 is formed, and the first uneven layer 450 can be independently formed on the partition wall 440.

[0181] As shown Figure 20 in the figure, a dielectric covering layer 455 is formed on a substrate 410. The dielectric covering layer 455 is formed on a first uneven layer 450.

[0182] An inorganic film having a dielectric constant is deposited on the substrate 410, thereby forming the dielectric covering layer 455. The dielectric covering layer 455 is formed on a partition wall 440. The dielectric covering layer 455 is formed in an assembly hole 440H1.

[0183] The thickness t2 of the dielectric covering layer 455 is thinner than the thickness t1 of the insulating layer 430. For example, the thickness t2 of the dielectric covering layer 455 can be several nanometers to several tens of nanometers.

[0184] The thickness t2 of the dielectric covering layer 455 is thinner than the thickness t3 of the bump 450a, so that the dielectric covering layer 455 formed on the partition wall 440 has a second uneven structure 456. The second uneven structure 456 has a shape corresponding to the shape of the first uneven structure 451 of the first uneven layer 450.

[0185] The dielectric covering layer 455 is made of an inorganic substance having a dielectric constant and has a second uneven structure 456. Thus, as described above, it can have functions such as a super-hydrophilic surface modification layer, a protective layer, an external light scattering layer, etc.

[0186] On the other hand, a self-assembled substrate can be manufactured differently from Figures 18 to 20 the manufacturing method shown in the figure. Referring to Figures 21 to 23 , a second method for manufacturing the self-assembled substrate of the first embodiment will be described.

[0187] Figures 21 to 23 A second method for manufacturing the self-assembled substrate of the first embodiment is shown. Figures 21 to 23 The manufacturing method of the self-assembled substrate corresponding to the first sub-pixel PX1 is illustrated, but the manufacturing methods of the self-assembled substrates corresponding to the second sub-pixel PX2 and the third sub-pixel PX3 are also the same as Figures 21 to 23 the manufacturing method of the self-assembled substrate corresponding to the first sub-pixel PX1 shown in the figure.

[0188] As Figure 21 shown, a series of processes are sequentially performed to form a first assembly wiring 421, a second assembly wiring 422, an insulating layer 430, and a partition wall 440 on the substrate 410. At the same time, an assembly hole 440H1 is formed in the partition wall 440. Here, the assembly hole 440H1 is the first assembly hole 440H1.

[0189] On the other hand, the thickness of the partition wall 440 can be compared with Figure 18The thickness of the illustrated partition wall 440 is large. Since a first uneven layer 450 is formed on the upper surface of the partition wall 440 as a part of the partition wall 440, this will be described later.

[0190] As Figure 22 shown, a PR pattern 500 can be formed on the partition wall 440.

[0191] Specifically, a photosensitive film is coated on the substrate 410. After that, the photosensitive film is patterned through exposure and development processes to form the PR pattern 500. The PR pattern 500 is not formed in the assembly holes 440H1 but is formed on the partition wall 440.

[0192] An etching process is performed using the PR pattern 500 as a mask, thereby removing a part of the upper surface of the partition wall 440 exposed between the PR patterns 500, and thus forming the first uneven layer 450. Here, the etching process may be a dry etching process, but is not limited thereto. That is, the first uneven layer 450 is formed as a part of the partition wall 440 on the upper surface of the partition wall 440. That is, the upper surface of the partition wall 440 corresponding to the PR pattern 500 in the upper surface of the partition wall 440 is not etched and remains, thereby forming the first uneven layer 450. In such a case, the upper surface of the partition wall 440 that is not etched by the PR pattern 500 becomes bumps 450a. The first uneven structure 451 is formed by these multiple bumps 450a.

[0193] By performing a dry etching process, the side surfaces of the bumps 450a are formed as surfaces perpendicular to the ground, but are not limited thereto.

[0194] As Figure 23 shown, a dielectric covering layer 455 is formed on the substrate 410. The dielectric covering layer 455 is formed on the first uneven layer 450. The dielectric covering layer 455 is not only formed on the partition wall 440, but may also be formed in the assembly holes, but is not limited thereto.

[0195] The dielectric covering layer 455 is composed of an inorganic substance having a dielectric constant and has a second uneven structure 456. Thus, as described above, it can have functions such as a super-hydrophilic surface modification layer, a protective layer, an external light scattering layer, etc.

[0196] On the other hand, in the first embodiment ( Figures 11 to 23 ), the sizes D21 of the multiple bumps 450a of the first uneven layer 450 on the partition wall 440 or the intervals L1 between the bumps 450a are the same. However, according to the separation distances from the assembly holes 440H1 to 440H3, the sizes D21 of the multiple bumps 450a or the intervals L1 between the bumps 450a are formed to be different, so that the adsorption force with the semiconductor light-emitting element can be changed (refer to Figure 24 and Figure 5)。

[0197] [Second Embodiment]

[0198] Figure 24 is a top view showing the self-assembly substrate of the second embodiment.

[0199] As Figure 24 shown, the size D21 of the bump 450a located near the assembly holes 440H1 to 440H3 is larger than the size D21 of the bump 450a located away from the assembly holes 440H1 to 440H3.

[0200] The size D21 of the bump 450a located near the assembly holes 440H1 to 440H3 is relatively large. In such a case, when the semiconductor light-emitting element is located near the assembly holes 440H1 to 440H3 during self-assembly, the contact area between the semiconductor light-emitting element and the bump 450a is large, so the possibility that the semiconductor light-emitting element is adsorbed to the partition wall 440 near the assembly holes 440H1 to 440H3 is high.

[0201] Differently, the size D21 of the bump 450a located away from the assembly holes 440H1 to 440H3 is relatively small. In such a case, when the semiconductor light-emitting element is located away from the assembly holes 440H1 to 440H3 during self-assembly, the contact area between the semiconductor light-emitting element and the bump 450a is small, so the possibility that the semiconductor light-emitting element is adsorbed to the partition wall 440 away from the assembly holes 440H1 to 440H3 is small.

[0202] Generally, a plurality of semiconductor light-emitting elements 150R, 150G, and 150B formed into a cluster by the magnet 1100 move in a specific direction. Even if the DEP force for forming the assembly holes 440H1 to 440H3 is applied, it is very difficult to assemble only one of the plurality of semiconductor light-emitting elements 150R, 150G, and 150B in the above movement to the assembly holes 440H1 to 440H3 by such a DEP force.

[0203] However, as shown in the second embodiment, the size D21 of the bump 450a located near the assembly holes 440H1 to 440H3 is larger than the size D21 of the bump 450a located away from the assembly holes 440H1 to 440H3, so that one semiconductor light-emitting element can be easily assembled into the corresponding assembly holes 440H1 to 440H3, and the assembly rate can be improved.

[0204] That is, in the vicinity of the assembly holes 440H1 to 440H3, the possibility that the semiconductor light-emitting elements are adsorbed onto the partition wall 440 is high, so that they are easily adsorbed onto the partition wall 440. Therefore, at least one or more semiconductor light-emitting elements can be adsorbed near the assembly holes 440H1 to 440H3. Accordingly, the number of candidate semiconductor light-emitting elements to be assembled into the assembly holes 440H1 to 440H3 is increased as much as possible, whereby the assembly rate can be improved. Thus, when at least one or more semiconductor light-emitting elements are adsorbed around the assembly holes 440H1 to 440H3, due to the collision caused by the movement of the plurality of semiconductor light-emitting elements 150R, 150G, 150B having a cluster unit in the vicinity, the at least one or more adsorbed semiconductor light-emitting elements fall off and are assembled into the adjacent assembly holes 440H1 to 440H3, so that the assembly rate can be improved. That is, the time for the semiconductor light-emitting elements to stay around the assembly holes 440H1 to 440H3 is increased, thereby increasing the probability that the semiconductor light-emitting elements are assembled into the assembly holes, and thus the assembly rate can be improved. In addition, at least one or more semiconductor light-emitting elements adsorbed around the assembly holes 440H1 to 440H3 can easily fall off due to the collision caused by the movement of the plurality of semiconductor light-emitting elements 150R, 150G, 150B having a cluster unit during the above movement. When one of the at least one or more semiconductor light-emitting elements that have fallen off in this way is assembled into the assembly holes 440H1 to 440H3, the remaining semiconductor light-emitting elements cannot be assembled into the assembly holes 440H1 to 440H3 any more, but are included in the above cluster and move by the magnet.

[0205] On the other hand, the semiconductor light-emitting elements are not adsorbed onto the partition wall 440 at positions far from the assembly holes 440H1 to 440H3, thereby preventing poor adsorption.

[0206] [Third Embodiment]

[0207] Figure 25 It is a top view showing the self-assembly substrate of the third embodiment.

[0208] As Figure 25 shown, the interval L1 between the bumps 450a located near the assembly holes 440H1 to 440H3 is smaller than the interval L1 between the bumps 450a located far from the assembly holes 440H1 to 440H3.

[0209] The interval L1 between the bumps 450a located at positions close to the assembly holes 440H1 to 440H3 is relatively small. In such a case, when the semiconductor light-emitting element is located at a position close to the assembly holes 440H1 to 440H3 during self-assembly, the contact area between the semiconductor light-emitting element and the bumps 450a is large, so the possibility that the semiconductor light-emitting element is adsorbed to the partition wall 440 at a position close to the assembly holes 440H1 to 440H3 is high.

[0210] Differently, the interval L1 between the bumps 450a located at positions far from the assembly holes 440H1 to 440H3 is relatively large. In such a case, when the semiconductor light-emitting element is located at a position far from the assembly holes 440H1 to 440H3 during self-assembly, the contact area between the semiconductor light-emitting element and the bumps 450a is small, so the possibility that the semiconductor light-emitting element is adsorbed to the partition wall 440 at a position far from the assembly holes 440H1 to 440H3 is low.

[0211] As shown in the third embodiment, the interval L1 between the bumps 450a located at positions close to the assembly holes 440H1 to 440H3 is smaller than the interval L1 between the bumps 450a located at positions far from the assembly holes 440H1 to 440H3, so that a semiconductor light-emitting element can be easily assembled into the assembly holes 440H1 to 440H3, and the assembly rate can be improved.

[0212] That is, at positions close to the assembly holes 440H1 to 440H3, the possibility that the semiconductor light-emitting element is adsorbed to the partition wall 440 is high and it is easily adsorbed to the partition wall 440. Therefore, at least one or more semiconductor light-emitting elements can be adsorbed near the assembly holes 440H1 to 440H3. Therefore, the number of candidate semiconductor light-emitting elements to be assembled into the assembly holes 440H1 to 440H3 is increased as much as possible, so that the assembly rate can be improved. In this way, when at least one or more semiconductor light-emitting elements are adsorbed around the assembly holes 440H1 to 440H3, due to the collision caused by the movement of the plurality of semiconductor light-emitting elements 150R, 150G, 150B having cluster units in the periphery, the above-mentioned at least one or more adsorbed semiconductor light-emitting elements fall off and are assembled into the adjacent assembly holes 440H1 to 440H3, so that the assembly rate can be improved.

[0213] On the other hand, at positions far from the assembly holes 440H1 to 440H3, the semiconductor light-emitting element is not adsorbed to the partition wall 440, so that adsorption failure can be prevented.

[0214] [Fourth Embodiment]

[0215] Figure 26 It is a cross-sectional view of the self-assembly substrate showing the fourth embodiment.

[0216] The fourth embodiment is the same as the first embodiment except for the dielectric coating layer 455. In the fourth embodiment, components having the same shape, structure, and / or function as those in the first embodiment are given the same reference numerals and detailed descriptions thereof are omitted.

[0217] Refer to Figure 26 , the self-assembly substrate 404 of the fourth embodiment includes a substrate 410, a first assembly wiring 421, a second assembly wiring 422, a partition wall 440, a first uneven layer 450, and a dielectric coating layer 455.

[0218] The dielectric coating layer 455 can be disposed on the partition wall 440. The dielectric coating layer 455 may not be disposed in the assembly hole 440H1.

[0219] The dielectric coating layer 455 may not be disposed on the bottom surface of the assembly hole 440H1. Since the dielectric coating layer 455 functions as a super-hydrophilic surface modification layer, it will hinder the adsorption of the semiconductor light-emitting element during self-assembly. The bottom surface of the assembly hole 440H1 is a portion for placing the semiconductor light-emitting element and fixing it by DEP force. Only when the semiconductor light-emitting element assembled into the assembly hole 440H1 does not come off outside the assembly hole 440H1 can the assembly rate be improved and lighting failure be prevented. Therefore, the dielectric coating layer 455 is not disposed on the bottom surface of the assembly hole 440H1, so that the fixing property with the semiconductor light-emitting element at the bottom surface of the assembly hole 440H1 can be strengthened, thereby improving the assembly rate and preventing lighting failure.

[0220] On the other hand, when the semiconductor light-emitting element is adsorbed to the inner side surface of the assembly hole 440H1, the semiconductor light-emitting element cannot be accurately positioned on the bottom surface of the assembly hole 440H1 but is inclined or skewed, resulting in a disconnection during the subsequent electrical connection process and causing lighting failure. Therefore, the inner side surface of the assembly hole 440H1 should be formed to prevent adsorption. Thus, as shown in the fourth embodiment, the dielectric coating layer 455 can be disposed on the inner side surface of the assembly hole 440H1. Thereby, on the inner side surface of the assembly hole 440H1, the semiconductor light-emitting element assembled into the assembly hole 440H1 is not adsorbed to the inner side surface of the assembly hole 440H1 by the dielectric coating layer 455, but is adsorbed or fixed to the bottom surface of the assembly hole 440H1, thereby improving the assembly rate and preventing lighting failure.

[0221] [Fifth Embodiment]

[0222] Figure 27 is a cross-sectional view showing the self-assembly substrate of the fifth embodiment.

[0223] The fifth embodiment is the same as the first to fourth embodiments except for the second uneven layer 457. In the fifth embodiment, for the components having the same shape, structure, and / or function as those in the first to fourth embodiments, the same reference numerals are given, and detailed descriptions thereof are omitted.

[0224] Referring Figure 27 , the self-assembly substrate 405 of the fifth embodiment includes a substrate 410, a first assembly wiring 421, a second assembly wiring 422, a partition wall 440, a first uneven layer 450, a second uneven layer 457, and a dielectric covering layer 455.

[0225] The second uneven layer 457 is disposed on the first uneven layer 450. The second uneven layer 457 is disposed between the first uneven layer 450 and the dielectric covering layer 455.

[0226] The second uneven layer 457 has a third uneven structure 458. At this time, the third uneven structure 458 may be a nano-texture. The width of the pattern of the nano-texture or the interval between the patterns is several nanometers, for example, 3 nm or less.

[0227] The second uneven layer 457 is disposed on the upper surfaces of the plurality of bumps 450a of the first uneven layer 450. The second uneven layer 457 is disposed on the partition wall 440 between the plurality of bumps 450a of the first uneven layer 450.

[0228] The first uneven layer 450 including the plurality of bumps 450a is disposed on the partition wall 440, and then an ashing process using O2 plasma is performed, thereby forming the second uneven layer 457 having the third uneven structure 458 as a nano-texture. That is, the ion particles of the O2 plasma collide with the upper surface of the partition wall 440 and the upper surface of the bump 450a to form surface roughness on the upper surface of the partition wall 440 and the upper surface of the bump 450a, and such surface roughness can be formed as a nano-texture.

[0229] Even if the ashing process using O2 plasma is performed on the entire area of the substrate 410, the insulating layer 430 in the assembly hole 440H1 does not react with the O2 plasma as an inorganic substance, so the second uneven layer 457 is not formed on the insulating layer 430. In the case where the insulating layer 430 is an organic substance, the second uneven layer 457 having a nano-texture can also be formed on the upper surface of the insulating layer 430 in the assembly hole 440H1.

[0230] In the fifth embodiment, a first uneven layer 450 is disposed and a second uneven layer 457 is disposed on the first uneven layer 450. Thereby, when self-assembly is performed, the adsorption possibility of the semiconductor light-emitting element can be further reduced, and the function as an external light-scattering layer can be further enhanced together with the dielectric covering layer 455.

[0231] On the other hand, the above-described display device may be a display panel. That is, in the embodiment, the display device and the display panel can be understood to have the same meaning. In the embodiment, the actual display device may include a display panel and a controller (or processor) that controls the display panel for displaying an image.

[0232] The above detailed description is illustrative only in all aspects and should not be construed in a limiting sense. The scope of the embodiment should be determined based on a reasonable interpretation of the appended claims, and all changes within the equivalent scope of the embodiment are included in the scope of the embodiment.

[0233] Industrial Applicability

[0234] The embodiment can be applied to the field of displays for displaying images or information. The embodiment can be applied to the field of displays that use semiconductor light-emitting elements to display images or information. The semiconductor light-emitting element can be a micron-scale semiconductor light-emitting element or a nano-scale semiconductor light-emitting element.

[0235] For example, the embodiment can be applied to TVs, in-vehicle display screens, mobile terminals such as mobile phones or smart phones, computer monitors such as laptop computers or desktop computers, automotive HUDs (head-Up Displays), backlight units for displays, XR (Extend Reality) displays such as AR, VR, MR (Mixed Reality), light sources, and the like.

Claims

1. A self-assembling substrate, comprising: a substrate; a first assembly wiring located on the substrate; a second assembly wiring located on the substrate; a partition wall located on the first assembly wiring and the second assembly wiring and having an assembly hole; a first uneven layer located on the partition wall and having a first concavo-convex structure; and a dielectric covering layer located on the partition wall and having a second concavo-convex structure, wherein the second concavo-convex structure has a shape corresponding to the shape of the first concavo-convex structure.

2. The self-assembling substrate according to claim 1, wherein the dielectric covering layer is a super-hydrophilic surface modification layer.

3. The self-assembling substrate according to claim 1, wherein the dielectric covering layer is a protective layer.

4. The self-assembling substrate according to claim 1, wherein the dielectric covering layer is an external light scattering layer.

5. The self-assembling substrate according to claim 1, wherein the first uneven layer includes a plurality of bumps, and the plurality of bumps are arranged on the upper surface of the partition wall.

6. The self-assembling substrate according to claim 5, wherein the size of the bumps is smaller than the size of a semiconductor light-emitting element.

7. The self-assembling substrate according to claim 5, wherein the interval between the bumps is smaller than the size of a semiconductor light-emitting element.

8. The self-assembling substrate according to claim 5, wherein according to the separation distance from the assembly hole, the size of each of the plurality of bumps or the interval between the plurality of bumps is different.

9. The self-assembling substrate according to claim 8, wherein the size of the bumps located at a position closer to the assembly hole is larger than the size of the bumps located at a position farther from the assembly hole.

10. The self-assembling substrate according to claim 8, wherein the interval between the bumps located at a position closer to the assembly hole is smaller than the interval between the bumps located at a position farther from the assembly hole.

11. The self-assembling substrate according to claim 5, wherein the dielectric covering layer is arranged on the upper surface of the partition wall except for the assembly hole.

12. The self-assembling substrate according to claim 11, wherein the dielectric covering layer is arranged on the inner side surface of the assembly hole.

13. The self-assembled substrate according to claim 5, wherein, The self-assembling substrate further includes: a second uneven layer located on the upper surface of each of the plurality of bumps and having a third concavo-convex structure.

14. The self-assembling substrate according to claim 13, wherein the second uneven layer is arranged on the upper surface of the partition wall between the plurality of bumps.

15. The self-assembling substrate according to claim 13, wherein the third concavo-convex structure is a nano-texture.

16. The self-assembling substrate according to claim 1, wherein the self-assembling substrate is an interposer substrate or a backplane substrate.

17. A display device manufactured using the self-assembling substrate according to claim 1.

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