ESD protection diode and structure thereof

Abstract

This ESD protection diode is provided with two pairs of PN diodes comprising P-type diffusion layers (23, 24) and N-type diffusion layers (31, 32) in a semiconductor substrate (10). The ESD protection diode is provided with a lateral bipolar transistor, which includes an N-type diffusion layer (25), P-type diffusion layers (23, 24), and N-type diffusion layers (31, 41) that are connected to an anode terminal (1) and have polarities different from those of the terminal, at a position of a semiconductor substrate sandwiched between two pairs of PN diodes. For example, a lateral bipolar transistor includes first and second P-type diffusion layers (23, 24) connected to an anode terminal (1), a third P-type diffusion layer (25) formed between the first and second P-type diffusion layers (23, 24) and connected to a cathode terminal (2), and first and second N-type diffusion layers (31, 32) formed in an N-type well (11) in a semiconductor substrate (10).

Description

Technical Field

[0001] The present invention relates to an ESD (ElectroStatic Discharge) protection diode and its structure. Background Art

[0002] For example, Patent Document 1 discloses a diode having the following structure, including: at least one gate diode and a shallow trench isolation (STI) diode, without halo implant or pocket implant, thereby reducing the capacitance of the diode. According to the diode of this prior example, although it is used in a circuit and other devices having performance characteristics that are easily affected by load capacitance, the performance characteristics of the diode can still be obtained. Such characteristics of the gate diode include a fast turn-on time and high conductance. As an example, the gate diode is made into a diode suitable for an ESD protection circuit. The diode includes a semiconductor substrate, on which a well region and an insulating layer are provided. A gate electrode is formed on the insulating layer. An anode region and a cathode region are provided in the well region.

[0003] That is, in the diode of the prior example, for the purpose of protecting the gate oxide film from overvoltage caused by an ESD surge (especially CDM (Charged Device Model)), it has a structure using a gate diode with superior conductance per unit length and turn-on speed and low capacitance that does not have a bad influence on the performance of the protected circuit. In addition, a method for reducing the junction capacitance, which is a problem specific to the gate diode, is disclosed.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2016-129267 Summary of the Invention

[0007] Problems to be Solved by the Invention

[0008] However, in the diodes of the existing examples, in order to reduce the junction capacitance in the diodes, countermeasures are taken to block the pocket implantation through a pocket implant mask, and it is considered that the existing process flow needs to be changed in technical applications. In addition, since gate diodes are used, there is a problem of load capacitance.

[0009] It is required that ESD protection components such as ESD protection diodes be appropriately configured according to the specifications and breakdown voltages of each terminal. In addition, the protection component itself discharges at a voltage higher than the operating voltage of the internal circuit and lower than the breakdown voltage of the internal circuit. When a surge invades, the ESD protection diode, after reaching the forward voltage Vf, plays a role in discharging the protection component itself and performing clamping. However, there is a concern about the breakdown of the gate oxide film due to each of the ESD protection diodes for low breakdown voltage and for high breakdown voltage. In the ESD protection diode for low breakdown voltage, since the gate oxide film of the protected component is very thin, the overshoot voltage generated before the protection diode reaches the forward voltage Vf becomes a problem.

[0010] On the other hand, in the ESD protection diode for high breakdown voltage, although the gate oxide film is thick, in order to ensure the breakdown voltage of the device, the well concentration becomes low. Therefore, there is a problem of high resistance component and poor responsiveness of the protection diode.

[0011] An object of the present invention is to provide an ESD protection diode and its structure that have improved responsiveness of the protection diode compared with the prior art ( ).

[0012] Means for solving the problem

[0013] The ESD protection diode according to one aspect of the present invention includes two pairs of PN diodes respectively formed by a P-type diffusion layer and an N-type diffusion layer in a semiconductor substrate. In the ESD protection diode,

[0014] At the position of the semiconductor substrate sandwiched by the two pairs of PN diodes, a lateral bipolar transistor is provided. The lateral bipolar transistor includes: a diffusion layer, a diffusion layer of a polarity different from that of the terminal connected to the cathode terminal or the anode terminal; the P-type diffusion layer; and the N-type diffusion layer.

[0015] Here, for example, in the ESD protection diode, the two pairs of PN diodes include:

[0016] A first PN diode formed by a first P-type diffusion layer and a first N-type diffusion layer; and

[0017] The second PN diode is composed of a second P-type diffusion layer and a second N-type diffusion layer.

[0018] The lateral bipolar transistor includes:

[0019] A first P-type diffusion layer and a second P-type diffusion layer, which are connected to the anode terminal;

[0020] A third P-type diffusion layer, which is formed at a position between the first P-type diffusion layer and the second P-type diffusion layer and is connected to the cathode terminal; and

[0021] The first and second N-type diffusion layers are formed in an N-type well within the semiconductor substrate.

[0022] Alternatively, for example, in the ESD protection diode, the two pairs of PN diodes include:

[0023] A first PN diode, which is composed of a first P-type diffusion layer and a first N-type diffusion layer; and

[0024] A second PN diode, which is composed of a second P-type diffusion layer and a second N-type diffusion layer,

[0025] The lateral bipolar transistor includes:

[0026] A first N-type diffusion layer and a second N-type diffusion layer, which are connected to the cathode terminal;

[0027] A third N-type diffusion layer, which is formed at a position between the first N-type diffusion layer and the second N-type diffusion layer and is connected to the anode terminal; and

[0028] The first and second P-type diffusion layers are formed in a P-type well within the semiconductor substrate.

[0029] Advantages of the Invention

[0030] Thus, the ESD protection diode according to one aspect of the present invention can provide an ESD protection diode, etc., which has improved responsiveness of the protection diode compared with the prior art. Brief Description of the Drawings

[0031] Figure 1 It is a longitudinal sectional view showing a structural example of the ESD protection diode 101A according to Embodiment 1.

[0032] Figure 2 It is a longitudinal sectional view showing a structural example of the high-voltage-resistant ESD protection diode 102A according to Embodiment 2.

[0033] Figure 3 It is a longitudinal sectional view showing a structural example of the ESD protection diode 103A according to Embodiment 3.

[0034] Figure 4 is a longitudinal sectional view showing a structural example of the high breakdown voltage ESD protection diode 104A according to Embodiment 4.

[0035] Figure 5 is a graph showing the existing example installed by the QFN0808 type package (Package) manufactured by the applicant according to Embodiment 1 and the JEITA standard DI-CDM test result of the ESD protection diode 101A according to Embodiment 1, that is, the voltage ratio for CDM. ), and the graph (Graph) of the voltage ratio for CDM which is the JEITA standard DI-CDM test result of the ESD protection diode 101A according to Embodiment 1.

[0036] Figure 6 is a graph showing the existing example installed by the QFN0808 type package manufactured by the applicant according to Embodiment 2 and the JEDEC standard FI (Field-Induced) - CDM test result of the ESD protection diode 101A according to Embodiment 1, that is, the voltage ratio for CDM.

[0037] Figure 7 is a graph showing the existing example installed by the HSOP18 type package manufactured by the applicant according to Embodiment 3 and the JEDEC standard FI (Field-Induced) - CDM test result of the ESD protection diode 101A according to Embodiment 1, that is, the voltage ratio for CDM.

[0038] Figure 8 is a circuit diagram showing the structure of a protection circuit using the ESD protection diodes D1 and D2 according to the prior art.

[0039] Figure 9 is a longitudinal sectional view showing the structure of the ESD protection diode 101 according to the existing example 1.

[0040] Figure 10 is a longitudinal sectional view showing the structure of the high breakdown voltage ESD protection diode 102 according to the existing example 2.

[0041] Figure 11 is a longitudinal sectional view showing the structure of the ESD protection diode 103 according to the existing example 3.

[0042] Figure 12 is a longitudinal sectional view showing the structure of the high breakdown voltage ESD protection diode 104 according to the existing example 4. Detailed Embodiments

[0043] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the same or similar structural elements are denoted by the same reference numerals.

[0044] (Insights of the inventors related to the existing examples)

[0045] Figure 8 This is a circuit diagram showing the structure of a protection circuit using the ESD protection diodes D1 and D2 related to the prior art. As Figure 8 shown, the ESD protection diodes D1 and D2 are inserted in two directions between the input pin terminal T1 and the VDD terminal T2, and between the input pin terminal T1 and the GND terminal T3. Here, when a prescribed ESD surge voltage is applied between the terminals T1 and T2 or between the terminals T1 and T3, if a voltage equal to or higher than the forward voltage Vf is applied to the terminals between the anodes and cathodes of the ESD protection diodes D1 and D2, the PN junction diodes of the ESD protection diodes D1 and D2 turn on in the forward direction. The ESD surge current passes through the ESD protection diodes D1 and D2, thereby protecting the internal circuit 100. Here, the ESD protection diode D2 operates when a negative ESD surge voltage lower than the power supply voltage VDD is applied, and the ESD protection diode D1 operates when a positive ESD surge voltage higher than the power supply voltage VDD is applied.

[0046] Next, referring to Figures 9 - 12 , the structures of the ESD protection diodes 101 to 104 related to the existing examples 1 to 4 will be described below.

[0047] Figure 9 This is a longitudinal sectional view showing the structure of the ESD protection diode 101 related to the existing example 1.

[0048] In Figure 9 , by implanting N-type impurity ions (such as P or As, with a dose of, for example, 2×10 12 ~1×10 13 ions / cm 2 ) into the central portion of the P-type semiconductor substrate 10, an N-type well 11 is formed. Next, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 ) into the P-type semiconductor substrate 10 on both outer sides of the N-type well 11, P-type diffusion layers 21 and 22 are respectively formed. In addition, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) into the N-type well 11 near the P-type diffusion layers 21 and 22, N-type diffusion layers 31 and 32 are respectively formed. And, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×1015 ions / cm 2 ), a P-type diffusion layer 23 is formed. Thus, near the substrate surface of the P-type semiconductor substrate 10 and the N-type well 11, starting from the left side in the figure, the P-type diffusion layer 21, the N-type diffusion layer 31, the P-type diffusion layer 23, the N-type diffusion layer 32, and the P-type diffusion layer 22 are arranged in parallel.

[0049] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the P-type diffusion layer 21 and the N-type diffusion layer 31, between the N-type diffusion layer 31 and the P-type diffusion layer 23, between the P-type diffusion layer 23 and the N-type diffusion layer 32, and between the N-type diffusion layer 32 and the P-type diffusion layer 22. Further, the P-type diffusion layer 23 is connected to the anode terminal 1 together via an electrode 23m by a bonding wire. In addition, the N-type diffusion layers 31 and 32 are connected to the cathode terminal 2 together via electrodes 31m and 32m by a bonding wire. Through the above processes, the ESD protection diode 101 is formed.

[0050] Figure 10 is a longitudinal sectional view showing the structure of the high-voltage ESD protection diode 102 according to the prior art example 2.

[0051] In Figure 10 , by implanting N-type impurity ions (such as P or As, with a dose of, for example, 5×10 12 ~1×10 13 ions / cm 2 ) into the central portion of the P-type semiconductor substrate 10, a high-voltage N-type well 11A is formed. Next, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 ) into the P-type semiconductor substrate 10 on both outer sides of the high-voltage N-type well 11A, P-type diffusion layers 21 and 22 are respectively formed. In addition, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) into the N-type well 11 near the P-type diffusion layers 21 and 22, N-type diffusion layers 31 and 32 are respectively formed. And, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) into the high-voltage N-type well 11A between the N-type diffusion layers 31 and 32 to form a P-type well 12, and then by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15ions / cm 2 ), a P-type diffusion layer 23 is formed. Thus, near the substrate surfaces of the P-type semiconductor substrate 10, the high-voltage N-type well 11A, and the P-type well 12, from the left side in the figure, the P-type diffusion layer 21, the N-type diffusion layer 31, the P-type diffusion layer 23, the N-type diffusion layer 32, and the P-type diffusion layer 22 are arranged in parallel.

[0052] Next, near the substrate surfaces between the P-type diffusion layer 21 and the N-type diffusion layer 31, between the N-type diffusion layer 31 and the P-type diffusion layer 23, between the P-type diffusion layer 23 and the N-type diffusion layer 32, and between the N-type diffusion layer 32 and the P-type diffusion layer 22, an insulating film 40 made of, for example, SiO2 is formed. Further, the P-type diffusion layer 23 is connected to the anode terminal 1 together via an electrode 23m by a bonding wire. In addition, the N-type diffusion layers 31 and 32 are respectively connected to the cathode terminal 2 together via electrodes 31m and 32m by bonding wires. Through the above processes, a high-voltage ESD protection diode 102 with a higher breakdown voltage than Figure 8 the ESD protection diode 101 is formed.

[0053] Figure 11 is a longitudinal sectional view showing the structure of the ESD protection diode 103 according to the prior art example 3.

[0054] In Figure 11 , by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) into the central part of the N-type semiconductor substrate 15, a P-type well 16 is formed. Next, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) into the N-type semiconductor substrate 15 on both outer sides of the P-type well 16, N-type diffusion layers 61 and 62 are respectively formed. In addition, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) into the P-type well 16 near the N-type diffusion layers 61 and 62, P-type diffusion layers 51 and 52 are respectively formed. And, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2), an N-type diffusion layer 63 is formed. Thus, near the substrate surface of the N-type semiconductor substrate 15 and the P-type well 16, starting from the right side in the figure, the N-type diffusion layer 61, the P-type diffusion layer 51, the N-type diffusion layer 63, the P-type diffusion layer 52, and the N-type diffusion layer 62 are arranged in parallel.

[0055] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the N-type diffusion layer 61 and the P-type diffusion layer 51, between the P-type diffusion layer 51 and the N-type diffusion layer 63, between the N-type diffusion layer 63 and the P-type diffusion layer 52, and between the P-type diffusion layer 52 and the N-type diffusion layer 62. Further, the P-type diffusion layers 51 and 52 are respectively connected to the anode terminal 1 together through bonding wires via the electrodes 51m and 52m. In addition, the N-type diffusion layer 63 is connected to the cathode terminal 2 together through a bonding wire via the electrode 63m. Through the above processes, the ESD protection diode 103 is formed.

[0056] Figure 12 is a longitudinal sectional view showing the structure of the high-voltage ESD protection diode 104 according to the conventional example 4.

[0057] In Figure 12 , by implanting P-type impurity ions (such as B, with a dose of, for example, 2×10 13 ~1×10 14 ions / cm 2 ) into the central part of the N-type semiconductor substrate 15, a high-voltage P-type well 16A is formed. Next, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 ) into the N-type semiconductor substrate 15 on both outer sides of the high-voltage P-type well 16A, the N-type diffusion layers 61 and 62 are respectively formed. In addition, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) into the high-voltage P-type well 16A near the N-type diffusion layers 61 and 62, the P-type diffusion layers 51 and 52 are respectively formed. And, after forming an N-type well 17 by implanting N-type impurity ions (such as P or As, with a dose of, for example, 2×10 12 ~1×10 13 ions / cm 2 ) into the N-type well 17, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2), an N-type diffusion layer 63 is formed. Thus, near the substrate surface of the N-type semiconductor substrate 15, the high-voltage withstand P-type well 16, and the N-type well 17, starting from the right side in the figure, the N-type diffusion layer 61, the P-type diffusion layer 51, the N-type diffusion layer 63, the P-type diffusion layer 52, and the N-type diffusion layer 62 are arranged in parallel.

[0058] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the N-type diffusion layer 61 and the P-type diffusion layer 51, between the P-type diffusion layer 51 and the N-type diffusion layer 63, between the N-type diffusion layer 63 and the P-type diffusion layer 52, and between the P-type diffusion layer 52 and the N-type diffusion layer 62. Further, the P-type diffusion layers 51, 52 are respectively connected to the anode terminal 1 together through bonding wires via the electrodes 51m, 52m. In addition, the N-type diffusion layer 63 is respectively connected to the cathode terminal 2 together through a bonding wire via the electrode 63m. Through the above processes, the high-voltage withstand ESD protection diode 104 is formed.

[0059] In the ESD protection diodes 101 to 104 configured as described above, if the potential difference between the P-type diffusion layers 21 to 23, 51 to 52 connected to the anode terminal 1 and the N-type diffusion layers 31 to 32, 63 connected to the cathode terminal 2 becomes a forward voltage Vf or more, the PN junction diode turns on in the forward direction, and the ESD surge can be discharged. In addition, in the high-voltage withstand ESD protection diodes 102, 104, in order to ensure the reverse breakdown voltage, the PN junctions become low-concentration wells (11A, 12) (16A, 17). In these low-concentration wells (11A, 12) (16A, 17), even when a voltage of more than the forward voltage Vf is applied, the problem is that the responsiveness deteriorates due to the resistance component of the PN junction.

[0060] In an application model such as CDM (Charged Device Model) that discharges in an extremely short time, the responsiveness of the protection element is very important. For an applied pulse such as CDM, the responsiveness of the parasitic bipolar junction transistor is higher than that of the PN diode. This is because while the P-type diffusion layer and the N-type well are forward-biased, the parasitic bipolar junction transistor also turns on, but the on-resistance Ron is much smaller and better than that of the diode.

[0061] In addition, compared with the bipolar junction transistor having the characteristic of being able to turn on by injecting a small amount of charge, for the PN diode, a voltage of the amount of (V - Vf) simply contributes to the discharge. Therefore, especially in the voltage near the forward voltage Vf, the discharge current of the bipolar junction transistor becomes larger than the discharge current of the diode.

[0062] Thus, it is considered that by introducing a highly responsive parasitic bipolar transistor, the overshoot voltage can be reduced and the CDM withstand voltage can be increased. In the embodiment according to the present invention, in order to improve the responsiveness of a protection element such as an ESD protection diode, a structure is adopted in which a diffusion layer having a conductivity type different from that of the well is added and this diffusion layer is connected to the anode terminal or the cathode terminal, thereby introducing a parasitic bipolar transistor into the PN diode.

[0063] Reference Figures 1 - 4 , a structural example of the ESD protection diodes 101 to 104 according to the embodiment of the present invention will be described below.

[0064] (Embodiment 1)

[0065] Figure 1 FIG. is a longitudinal sectional view showing a structural example of the ESD protection diode 101A according to Embodiment 1. Figure 1 The ESD protection diode 101A of Figure 9 differs from the ESD protection diode 101 of

[0066] in the following points.

[0067] (1) While maintaining the structure of the PN diodes (23, 31; 24, 32) at both ends as it is, a P-type diffusion layer 25 connected to the cathode terminal 2 is provided to form a lateral PNP parasitic bipolar transistor having higher responsiveness than the prior art.

[0068] First, the formation method and structure of the ESD protection diode 101A of Figure 1 will be described below.

[0069] In Figure 1 , by implanting N-type impurity ions (such as P or As, with a dose of, for example, 2×10 12 ~1×10 13 ions / cm 2), an N-type well 11 is formed. Next, P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 are implanted into the P-type semiconductor substrate 10 on both outer sides of the N-type well 11 to form P-type diffusion layers 21 and 22, respectively. In addition, N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 are implanted into the N-type well 11 near the P-type diffusion layers 21 and 22 to form N-type diffusion layers 31 and 32, respectively. Further, P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 are implanted into three positions at a specified interval in the N-type well 11 between the N-type diffusion layers 31 and 32 to form P-type diffusion layers 23, 25, and 24. Thus, near the substrate surface of the P-type semiconductor substrate 10 and the N-type well 11, in the lateral direction actually parallel to the surface of the semiconductor substrate 10 from the left side in the figure, the P-type diffusion layer 21, the N-type diffusion layer 31, the P-type diffusion layers 23, 25, 24, the N-type diffusion layer 32, and the P-type diffusion layer 22 are arranged in parallel.

[0070] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the P-type diffusion layer 21 and the N-type diffusion layer 31, between the N-type diffusion layer 31 and the P-type diffusion layer 23, between the P-type diffusion layer 23 and the P-type diffusion layer 25, between the P-type diffusion layer 25 and the P-type diffusion layer 24, between the P-type diffusion layer 24 and the N-type diffusion layer 32, and between the N-type diffusion layer 32 and the P-type diffusion layer 22. Further, the P-type diffusion layers 23 and 24 are respectively connected to the positive terminal 1 together through bonding wires via the electrodes 23m and 24m. In addition, the N-type diffusion layers 31 and 32 and the P-type diffusion layer 25 are respectively connected to the negative terminal 2 together through bonding wires via the electrodes 31m, 32m, and 25m. Through the above processes, the ESD protection diode 101 is formed.

[0071] Regarding the ESD protection diode 101A configured as above, in order to improve its responsiveness, a new structure introducing a lateral PNP-type parasitic bipolar transistor into the diode structure is proposed, which has the following two characteristics A and B.

[0072] (Feature A) By maintaining the pair (23, 31) (24, 32) of a P-type diffusion layer and an N-type diffusion layer connected to the anode 1, the original state of the PN diode is maintained. A highly responsive lateral PNP parasitic bipolar transistor is formed by connecting the P-type diffusion layer 25 to the cathode terminal 2. Here, the lateral PNP parasitic bipolar transistor has the base of the N-type well 11, the emitters of the P-type diffusion layers 23 and 24 connected to the anode terminal 1, and the collector of the P-type diffusion layer 25 connected to the cathode terminal 2.

[0073] (Feature B) Two PN diodes are formed at both ends of the N-type well 11, and a lateral PNP parasitic bipolar transistor is formed in the central portion of the N-type well 11 sandwiched between the two PN diodes.

[0074] With the structures of Feature A and Feature B above, it is possible to make the distances L11 and L12 between the two pairs of P-type diffusion layers (23, 25) (24, 25) the minimum distances, and it is possible to make the distances L13 and L14 between the two pairs of P-type diffusion layer / N-type diffusion layer (31, 23) (32, 22) the minimum distances. The purpose of making the distances L11 and L12 the minimum distances is that, because of the lateral PNP parasitic bipolar transistor, the base becomes the shortest, so the current amplification factor hfe of the bipolar transistor can be increased and the breakdown voltage can be increased. In addition, the purpose of making the distances L13 and L14 the minimum distances is for the PN diode to operate normally and increase the breakdown voltage. According to the evaluation results of the embodiments described later, it is obvious that if the distances of the respective PN diodes are not the minimum distances and the path length is long, the CDM breakdown voltage will decrease. In addition, according to the prototypes of the inventors of the present invention, the distances L11 to L14 are preferably the minimum distances set based on the specified device breakdown voltage, for example, 1 to 5 μm.

[0075] As described above, according to the ESD protection diode 101 according to Embodiment 1, in order to improve the responsiveness of protection elements such as the ESD protection diode, it has a structure in which a P-type diffusion layer 25 having a conductivity type different from that of the N-type well 11 is added and the P-type diffusion layer 25 is connected to the cathode terminal 2, thereby introducing a parasitic bipolar transistor structure into the PN diode. That is, by improving the responsiveness of the ESD protection diode, the CDM breakdown voltage can be particularly increased. In this way, by introducing a PNP parasitic bipolar transistor having higher responsiveness than the prior art, the overshoot voltage can be reduced and the CDM breakdown voltage can be increased.

[0076] (Embodiment 2)

[0077] Figure 2 It is a longitudinal sectional view showing a structural example of the high-voltage ESD protection diode 102A according to Embodiment 2. Figure 2 The ESD protection diode 102A ofFigure 10 Compared with the ESD protection diode 102, it has the following differences.

[0078] (1) While maintaining the structure of the PN diodes (23, 31; 24, 32) at both ends as it is, by providing a P-type diffusion layer 25 connected to the cathode terminal 2, a lateral (horizontal direction) PNP parasitic bipolar transistor with higher responsiveness than the prior art is formed.

[0079] (2) For the balanced structure of the semiconductor element, a P-type diffusion layer 24 connected to the anode terminal 1 is provided. Thus, the PN diodes are formed at both ends of the high-voltage withstand N-type well 11A by pairs of a P-type diffusion layer 23 and an N-type diffusion layer 31 and pairs of a P-type diffusion layer 24 and an N-type diffusion layer 32. In addition, the lateral PNP parasitic bipolar transistor is constituted by using the P-type diffusion layers 23 and 24 connected to the anode terminal 1 as the emitter, the high-voltage withstand N-type well 11A as the base, and the P-type diffusion layer 25 connected to the cathode terminal 2 as the collector.

[0080] First, the formation method and structure of the ESD protection diode 102A will be described below. Figure 2 of the ESD protection diode 102A.

[0081] In Figure 1 , by implanting N-type impurity ions (such as P or As, with a dose of, for example, 5×12 12 ~1×10 13 ions / cm 2 ) into the central part of the P-type semiconductor substrate 10, a high-voltage withstand N-type well 11A is formed. Next, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 ) into the P-type semiconductor substrate 10 on both outer sides of the N-type well 11A, P-type diffusion layers 21 and 22 are respectively formed. In addition, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) into the N-type well 11A near the P-type diffusion layers 21 and 22, N-type diffusion layers 31 and 32 are respectively formed. And, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2After forming the P-type wells 12 and 13, P-type impurity ions (such as B, with a dose of, for example, 1×10 15 ~5×10 15 ions / cm 2 are implanted at three specified positions in the N-type well 11A at a specified interval between the N-type diffusion layers 31 and 32 (the two outer positions are the formation positions of the P-type wells 12 and 13), forming P-type diffusion layers 23, 25, and 24. Thus, near the substrate surface of the P-type semiconductor substrate 10 and the N-type well 11A, starting from the left side in the figure, in the lateral direction actually parallel to the surface of the semiconductor substrate 10, P-type diffusion layer 21, N-type diffusion layer 31, P-type diffusion layers 23, 25, 24, N-type diffusion layer 32, and P-type diffusion layer 22 are arranged in parallel.

[0082] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the P-type diffusion layer 21 and the N-type diffusion layer 31, between the N-type diffusion layer 31 and the P-type diffusion layer 23, between the P-type diffusion layer 23 and the P-type diffusion layer 25, between the P-type diffusion layer 25 and the P-type diffusion layer 24, between the P-type diffusion layer 24 and the N-type diffusion layer 32, and between the N-type diffusion layer 32 and the P-type diffusion layer 22. Further, the P-type diffusion layers 23 and 24 are respectively connected to the positive terminal 1 together through bonding wires via electrodes 23m and 24m. In addition, the N-type diffusion layers 31 and 32 and the P-type diffusion layer 25 are respectively connected to the negative terminal 2 together through bonding wires via electrodes 31m, 32m, and 25m. Through the above processes, the ESD protection diode 102A is formed.

[0083] For the ESD protection diode 102A configured as above, in order to improve its responsiveness, in addition to having a new structure that introduces a lateral PNP parasitic bipolar transistor into the diode structure and having the same two features A and B as in the first embodiment, high-voltage-resistant N-type well 11A, P-type wells 12 and 13 are formed, so that the breakdown voltage of the entire device of the ESD protection diode 102A can be made higher than that of the ESD protection diode 101A in the first embodiment.

[0084] With the structures of the described Feature A and B, it is possible to form a structure in which the distances L21 and L22 between the two pairs of P-type diffusion layers (23, 25) and (24, 25) become the minimum distances, and it is possible to form a structure in which the distances L23 and L24 between the two pairs of P-type diffusion layer / N-type diffusion layers (31, 23) and (32, 22) become the minimum distances. The purpose of setting the distances L21 and L22 to the minimum distances is that, due to the lateral PNP parasitic bipolar transistor, the base becomes the shortest, so that the current amplification factor hfe of the bipolar transistor can be increased and the breakdown voltage can be improved. In addition, the purpose of setting the distances L23 and L24 to the minimum distances is for the PN diode to operate normally and to improve the breakdown voltage. According to the evaluation results of the embodiments described later, it is obvious that if the PN diodes are not at the minimum distances and the path lengths are long, the CDM breakdown voltage will decrease. In addition, according to the prototypes of the present inventors, the distances L21 to L24 are preferably the minimum distances set based on the specified device breakdown voltage, for example, 10 to 15 μm.

[0085] As described above, according to the ESD protection diode 102A according to Embodiment 2, in order to improve the responsiveness of protection elements such as the ESD protection diode, by adding a P-type diffusion layer 25 having a conductivity type different from that of the N-type well 11A and connecting the P-type diffusion layer 25 to the cathode terminal 2, a structure in which a PNP parasitic bipolar transistor is introduced into the PN diode is provided. That is, by improving the responsiveness of the ESD protection diode, in particular, the CDM breakdown voltage can be improved. In this way, by introducing a PNP parasitic bipolar transistor having higher responsiveness than the prior art, the overshoot voltage can be reduced and the CDM breakdown voltage can be improved.

[0086] (Embodiment 3)

[0087] Figure 3 It is a longitudinal sectional view showing a structural example of the ESD protection diode 103A according to Embodiment 3. Figure 3 The ESD protection diode 103A of Figure 11 Compared with the ESD protection diode 103 of

[0088] (1) While maintaining the structure of the PN diodes (52, 65; 51, 63) at both ends as it is, by providing an N-type diffusion layer 64 connected to the anode terminal 1, a lateral (horizontal direction) NPN parasitic bipolar transistor with higher responsiveness than the prior art is formed.

[0089] (2) For the balanced structure of the semiconductor element, an N-type diffusion layer 65 connected to the cathode terminal 2 is provided. Thus, the PN diode is formed at both ends of the P-type well 16 by pairs of the P-type diffusion layer 51 and the N-type diffusion layer 63 and pairs of the P-type diffusion layer 52 and the N-type diffusion layer 65. In addition, the lateral NPN parasitic bipolar transistor is configured with the N-type diffusion layer 64 connected to the anode terminal 1 as the collector, the P-type well 16 as the base, and the N-type diffusion layers 63 and 65 connected to the cathode terminal 2 as the emitter.

[0090] First, the formation method and structure of the ESD protection diode 103A described below Figure 3 will be described.

[0091] In Figure 3 , a P-type well 16 is formed by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) into the central portion of the N-type semiconductor substrate 15. Next, N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) are implanted into the N-type semiconductor substrate 15 on both outer sides of the P-type well 16 to form N-type diffusion layers 61 and 62, respectively. In addition, P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~5×10 13 ions / cm 2 ) are implanted into the P-type well 16 near the N-type diffusion layers 61 and 62 to form P-type diffusion layers 51 and 52, respectively. And N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~7×10 15 ions / cm 2 ) are implanted into the P-type well 16 at three positions with a specified interval between the P-type diffusion layers 51 and 52 to form N-type diffusion layers 63, 64, and 65, respectively. Thus, near the substrate surface of the N-type semiconductor substrate 15 and the P-type well 16, the N-type diffusion layer 61, the P-type diffusion layer 51, the N-type diffusion layers 63, 64, 65, the P-type diffusion layer 52, and the N-type diffusion layer 62 are arranged side by side in a lateral direction substantially parallel to the surface of the semiconductor substrate 10, starting from the right side in the figure.

[0092] Next, an insulating film 40 made of, for example, SiO2 is formed near the substrate surface between the N-type diffusion layer 61 and the P-type diffusion layer 51, between the P-type diffusion layer 51 and the N-type diffusion layer 63, between the N-type diffusion layer 63 and the N-type diffusion layer 64, between the N-type diffusion layer 64 and the N-type diffusion layer 65, between the N-type diffusion layer 65 and the P-type diffusion layer 52, and between the P-type diffusion layer 52 and the N-type diffusion layer 62. Further, the P-type diffusion layers 51 and 52 and the N-type diffusion layer 64 are respectively connected to the anode terminal 1 together through bonding wires via the electrodes 51m, 52m, and 64m. In addition, the N-type diffusion layers 63 and 65 are respectively connected to the cathode terminal 2 together through bonding wires via the electrodes 63m and 65m. Through the above processes, the ESD protection diode 103A is formed.

[0093] Regarding the ESD protection diode 103A configured as described above, in order to improve its responsiveness, a new structure that introduces a lateral NPN parasitic bipolar transistor into the diode structure is proposed, which has the following two features C and D.

[0094] (Feature C) The PN diode is maintained as it is by the pair (51, 63) (52, 65) of the P-type diffusion layer and the N-type diffusion layer connected to the anode 1, and a highly responsive lateral NPN parasitic bipolar transistor is formed by connecting the N-type diffusion layer 64 to the anode terminal 1. Here, the lateral NPN parasitic bipolar transistor has the base of the P-type well 16, the collector of the N-type diffusion layer 64 connected to the anode terminal 1, and the emitters of the P-type diffusion layers 63 and 65 connected to the cathode terminal 2.

[0095] (Feature D) Two PN diodes are formed at both ends of the P-type well 16, and a lateral NPN parasitic bipolar transistor is formed at the central portion of the P-type well 16 sandwiched between the two PN diodes.

[0096] With the structures of features C and D described above, it is possible to form a structure in which the distances L31 and L32 between the two pairs of N-type diffusion layers (64, 65) (63, 64) are minimized, and it is also possible to form a structure in which the distances L34 and L33 between the two pairs of P-type diffusion layer / N-type diffusion layer (51, 63) (52, 65) are minimized. The purpose of setting the distances L31 and L32 to the minimum distance is to make the base the shortest due to the lateral NPN parasitic bipolar transistor, so that the current amplification factor hfe of the bipolar transistor can be increased and the breakdown voltage can be improved. In addition, the purpose of setting the distances L33 and L34 to the minimum distance is to enable the PN diode to operate normally and improve the breakdown voltage. According to the evaluation results of the embodiments described later, it is obvious that if the PN diodes are not at the minimum distance and the path length is long, the CDM breakdown voltage will decrease. In addition, according to the prototypes of the inventors of the present invention, the distances L31 to L34 are preferably the minimum distances set based on a specified device breakdown voltage, for example, 1 to 5 μm.

[0097] As described above, according to the ESD protection diode 103A according to Embodiment 3, in order to improve the responsiveness of protection elements such as ESD protection diodes, it has a structure in which an N-type diffusion layer 64 having a conductivity type different from that of the P-type well 16 is added and the N-type diffusion layer 64 is connected to the anode terminal 1, thereby introducing a parasitic bipolar transistor into the PN diode. That is, by improving the responsiveness of the ESD protection diode, particularly the CDM breakdown voltage can be improved. In this way, by introducing an NPN parasitic bipolar transistor with higher responsiveness compared to the prior art, the overshoot voltage can be reduced and the CDM breakdown voltage can be improved.

[0098] (Embodiment 4)

[0099] Figure 4 FIG. is a longitudinal sectional view showing a structural example of a high breakdown voltage ESD protection diode 104A according to Embodiment 4. Figure 4 The ESD protection diode 104A of Figure 12 differs from the ESD protection diode 104 in the following points.

[0100] (1) While maintaining the structure of the PN diodes (51, 63; 52, 65) at both ends as it is, by providing an N-type diffusion layer 64 connected to the anode terminal 1, a lateral (horizontal direction) NPN parasitic bipolar transistor with higher responsiveness than the prior art is formed.

[0101] (2) For the balanced structure of the semiconductor element, an N-type diffusion layer 65 connected to the anode terminal 1 is provided. As a result, the PN diode is formed at both ends of the high-voltage-resistant P-type well 16A by the pairs of the P-type diffusion layer 51 and the N-type diffusion layer 63 and the P-type diffusion layer 52 and the N-type diffusion layer 65. In addition, the lateral NPN parasitic bipolar transistor is constituted by using the N-type diffusion layer 64 connected to the anode terminal 1 as the emitter, the high-voltage-resistant P-type well 16A as the base, and the N-type diffusion layers 63 and 65 connected to the cathode terminal 2 as the collector.

[0102] First, the formation method and structure of the ESD protection diode 104A described below Figure 4 will be described.

[0103] In Figure 4 , by implanting P-type impurity ions (such as B, with a dose of, for example, 2×10 13 ~ 1×10 14 ions / cm 2 ) into the central portion of the N-type semiconductor substrate 15, a high-voltage-resistant P-type well 16A is formed. Next, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~ 7×10 15 ions / cm 2 ) into the N-type semiconductor substrate 15 on both outer sides of the high-voltage-resistant P-type well 16A, N-type diffusion layers 61 and 62 are respectively formed. In addition, by implanting P-type impurity ions (such as B, with a dose of, for example, 1×10 13 ~ 5×10 13 ions / cm 2 ) into the high-voltage-resistant P-type well 16A near the N-type diffusion layers 61 and 62, P-type diffusion layers 51 and 52 are respectively formed. And, after forming N-type wells 17 and 18 by implanting N-type impurity ions (such as P or As, with a dose of, for example, 2×10 12 ~ 1×10 13 ions / cm 2 ) into the high-voltage-resistant P-type well 16A at two outer positions among three positions at a prescribed interval between the P-type diffusion layers 51 and 52, by implanting N-type impurity ions (such as P or As, with a dose of, for example, 1×10 15 ~ 7×10 15 ions / cm 2), N-type diffusion layers 63, 64, and 65 are respectively formed. Thus, near the substrate surface of the N-type semiconductor substrate 15 and the high-voltage-resistant P-type well 16A, in the lateral direction actually parallel to the surface of the semiconductor substrate 10 from the right side in the figure, N-type diffusion layers 61, P-type diffusion layer 51, N-type diffusion layers 63, 64, 65, P-type diffusion layer 52, and N-type diffusion layer 62 are arranged in parallel.

[0104] Next, near the substrate surface between the N-type diffusion layer 61 and the P-type diffusion layer 51, between the P-type diffusion layer 51 and the N-type diffusion layer 63, between the N-type diffusion layer 63 and the N-type diffusion layer 64, between the N-type diffusion layer 64 and the N-type diffusion layer 65, between the N-type diffusion layer 65 and the P-type diffusion layer 52, and between the P-type diffusion layer 52 and the N-type diffusion layer 62, an insulating film 40 made of, for example, SiO2 is formed. Further, the P-type diffusion layers 51, 52 and the N-type diffusion layer 64 are respectively connected to the anode terminal 1 together through bonding wires via electrodes 51m, 52m, 64m. In addition, the N-type diffusion layers 63, 65 are respectively connected to the cathode terminal 2 together through bonding wires via electrodes 63m, 65m. Through the above processes, the ESD protection diode 104A is formed.

[0105] According to the ESD protection diode 104A configured as above, in order to improve its responsiveness, in addition to having a new structure that introduces a lateral NPN-type parasitic bipolar transistor into the diode structure and having the same two characteristics C and D as in Embodiment 3, high-voltage-resistant P-type wells 16A, N-type wells 17, 18 are also formed, so that the breakdown voltage of the entire device of the ESD protection diode 104B can be made higher than that of the ESD protection diode 103A in Embodiment 3.

[0106] Through the structures of the characteristics C and D, it is possible to make the distances L41 and L42 between the two pairs of N-type diffusion layers (64, 65) (63, 64) the minimum distances, and it is possible to make the distances L44 and L43 between the two pairs of P-type diffusion layer / N-type diffusion layers (51, 63) (52, 62) the minimum distances. The purpose of setting the distances L41 and L42 as the minimum distances is that, because of the lateral NPN-type parasitic bipolar transistor, the base becomes the shortest, so the current amplification factor hfe of the bipolar transistor can be increased and the breakdown voltage can be increased. In addition, the purpose of setting the distances L43 and L44 as the minimum distances is for the PN diode to operate normally and increase the breakdown voltage. According to the evaluation results of the embodiments described later, it is obvious that if the PN diodes are not at the minimum distances and the path lengths are long, the CDM breakdown voltage will decrease. In addition, according to the prototypes of the inventors of the present invention, the distances L41 to L44 are preferably the minimum distances set based on the specified device breakdown voltage, for example, 10 to 15 μm.

[0107] According to the ESD protection diode 104A configured as described above, in order to improve the responsiveness of protection components such as ESD protection diodes, it has a structure in which an N-type diffusion layer 64 of a conductivity type different from that of the P-type well 16A is added and the N-type diffusion layer 64 is connected to the anode terminal 1, thereby introducing a parasitic bipolar transistor structure into the PN diode. That is, by improving the responsiveness of the ESD protection diode, in particular, the CDM withstand voltage can be improved. In this way, by introducing an NPN parasitic bipolar transistor with higher responsiveness compared to the prior art, the overshoot voltage can be reduced and the CDM withstand voltage can be increased.

[0108] Embodiment

[0109] Figure 5 It is a graph showing the voltage ratio with respect to CDM, which is the JEITA standard D (Direct)-CDM test result of the existing example mounted through the QFN0808 package manufactured by the applicant and the ESD protection diode 101A according to Embodiment 1. In addition, Figure 6 It is a graph showing the voltage ratio with respect to CDM, which is the JEDEC standard FI (Field-Induced)-CDM test result of the existing example mounted through the QFN0808 package manufactured by the applicant and the ESD protection diode 101A according to Embodiment 2. Further, Figure 7 It is a graph showing the voltage ratio with respect to CDM, which is the JEDEC standard FI (Field-Induced)-CDM test result of the existing example mounted through the HSOP18 package manufactured by the applicant and the ESD protection diode 101A according to Embodiment 3. Here, the reference value is set to the voltage value of the ESD protection diode related to the existing example.

[0110] According to Figures 5 - 7 , regarding the device structure according to the embodiment, it shows to what extent the CDM withstand voltage is improved, and represents the voltage ratio of the CDM withstand voltage with respect to the reference value related to the existing example. From Figures 5 - 7 , it can be seen that in all embodiments, the CDM withstand voltage is improved.

[0111] (Other modified examples)

[0112] In the above embodiment, for Figures 1 - 4The embodiments have been described, but the present invention is not limited thereto and may also be configured as follows: In a semiconductor substrate, in an ESD protection diode having two pairs of PN diodes formed of a P-type diffusion layer and an N-type diffusion layer respectively, a lateral bipolar transistor is provided at a position of the semiconductor substrate sandwiched by the two pairs of PN diodes, and the lateral bipolar transistor includes: a diffusion layer having a polarity different from that of the terminal connected to the cathode terminal or the anode terminal, the P-type diffusion layer, and the N-type diffusion layer.

[0113] (Differences from Patent Document 1)

[0114] The differences from Patent Document 1 will be described below.

[0115] In Patent Document 1, the following structure is disclosed: For the purpose of protecting the gate oxide film from overvoltage caused by an ESD surge (especially CDM), a structure having a gate diode with superior conductance per unit length and turn-on speed and low capacitance that does not adversely affect the performance of the protected circuit is provided. In addition, a method for reducing the junction capacitance, which is a problem specific to gate diodes, is proposed. It is indeed similar to the present invention in that both are protection elements for CDM.

[0116] However, in the invention described in Patent Document 1, in order to reduce the junction capacitance in the diode, a countermeasure of blocking pocket implantation through a pocket implantation mask is taken, which is considered to require changing the existing process flow in technical applications. In addition, since a gate diode is used, there is a problem of load capacitance. That is, if the gate diode is not used, the load capacitance will not be a particular problem. In contrast, in the embodiment of the present invention, a highly responsive ESD protection diode is fabricated without changing the process flow and without using a gate diode.

[0117] Industrial Applicability

[0118] As described in detail above, according to the ESD protection diode of the present invention, in order to improve the responsiveness of protection elements such as the ESD protection diode, a structure is provided in which a diffusion layer having a conductivity type different from that of the well is added and the diffusion layer is connected to the anode terminal or the cathode terminal, thereby introducing a parasitic bipolar transistor into the PN diode. That is, by improving the responsiveness of the ESD protection diode, especially the CDM withstand voltage can be improved. In this way, by introducing a PNP parasitic bipolar transistor with higher responsiveness compared to the prior art, the overshoot voltage can be reduced and the CDM withstand voltage can be improved.

[0119] Explanation of Reference Numerals

[0120] 1 Anode terminal

[0121] 2 Cathode terminal

[0122] 10 P-type semiconductor substrate

[0123] 11 N-type well

[0124] 11A High-voltage-resistant N-type well

[0125] 12, 13 P-type well

[0126] 15 N-type semiconductor substrate

[0127] 16 P-type well

[0128] 16A High-voltage-resistant P-type well

[0129] 17, 18 N-type well

[0130] 21~25 P-type diffusion layer

[0131] 23m~25m Electrode

[0132] 31~32 N-type diffusion layer

[0133] 31m~32m Electrode

[0134] 40 Insulating film

[0135] 51~52 P-type diffusion layer

[0136] 51m~52m Electrode

[0137] 61~65 N-type diffusion layer

[0138] 63m~65m Electrode

[0139] 100 Internal circuit

[0140] 101~104, 101A~104A ESD protection diode

[0141] T1~T3 Terminals.

Claims

1. An ESD protection diode, which is an ESD protection diode having two pairs of PN diodes respectively formed by a P-type diffusion layer and an N-type diffusion layer in a semiconductor substrate, wherein, at the position of the semiconductor substrate sandwiched by the two pairs of PN diodes, a lateral bipolar transistor is provided, and the lateral bipolar transistor includes: a diffusion layer of a polarity different from the terminal connected to the cathode terminal or the anode terminal, the P-type diffusion layer, and the N-type diffusion layer.

2. The ESD protection diode according to claim 1, wherein, the two pairs of PN diodes include: a first PN diode formed by a first P-type diffusion layer and a first N-type diffusion layer; and a second PN diode formed by a second P-type diffusion layer and a second N-type diffusion layer, the lateral bipolar transistor includes: the first P-type diffusion layer and the second P-type diffusion layer, which are connected to the anode terminal; a third P-type diffusion layer formed at a position between the first P-type diffusion layer and the second P-type diffusion layer and connected to the cathode terminal; and the first N-type diffusion layer and the second N-type diffusion layer, which are formed in an N-type well in the semiconductor substrate.

3. The ESD protection diode according to claim 2, wherein, the first P-type diffusion layer, the second P-type diffusion layer, and the third P-type diffusion layer are formed in an N-type well in the semiconductor substrate, the first P-type diffusion layer and the second P-type diffusion layer are the emitters of the lateral bipolar transistor, the N-type well is the base of the lateral bipolar transistor, the third P-type diffusion layer is the collector of the lateral bipolar transistor.

4. The ESD protection diode according to claim 3, wherein, the ESD protection diode further includes: a fourth P-type diffusion layer formed on the semiconductor substrate on the outer side of the first N-type diffusion layer opposite to the first P-type diffusion layer and connected to the anode terminal; and a fifth P-type diffusion layer formed on the semiconductor substrate on the outer side of the second N-type diffusion layer opposite to the second P-type diffusion layer and connected to the anode terminal.

5. The ESD protection diode according to claim 2, wherein, the first P-type diffusion layer and the second P-type diffusion layer are formed in a P-type well in the semiconductor substrate, the third P-type diffusion layer is formed in an N-type well in the semiconductor substrate, the first P-type diffusion layer and the second P-type diffusion layer are the emitters of the lateral bipolar transistor, the N-type well is the base of the lateral bipolar transistor, the third P-type diffusion layer is the collector of the lateral bipolar transistor.

6. The ESD protection diode according to any one of claims 3 to 5, wherein, the distance between the emitter and the collector of the lateral bipolar transistor is set to the minimum distance set according to a specified device breakdown voltage.

7. The ESD protection diode according to any one of claims 3 to 5, wherein, the distances between the first P-type diffusion layer and the first N-type diffusion layer and between the second P-type diffusion layer and the second N-type diffusion layer are set to the minimum distances set according to a specified device breakdown voltage.

8. The ESD protection diode according to claim 1, wherein the two pairs of PN diodes include: a first PN diode formed by a first P-type diffusion layer and a first N-type diffusion layer; and a second PN diode formed by a second P-type diffusion layer and a second N-type diffusion layer, the lateral bipolar transistor includes: a first N-type diffusion layer and a second N-type diffusion layer connected to the cathode terminal; a third N-type diffusion layer formed at a position between the first N-type diffusion layer and the second N-type diffusion layer and connected to the anode terminal; and the first P-type diffusion layer and the second P-type diffusion layer formed in a P-type well within the semiconductor substrate.

9. The ESD protection diode according to claim 8, wherein the first N-type diffusion layer, the second N-type diffusion layer, and the third N-type diffusion layer are formed in a P-type well within the semiconductor substrate, the first N-type diffusion layer and the second N-type diffusion layer are the emitters of the lateral bipolar transistor, the P-type well is the base of the lateral bipolar transistor, the third N-type diffusion layer is the collector of the lateral bipolar transistor.

10. The ESD protection diode according to claim 9, wherein the ESD protection diode further includes: a fourth N-type diffusion layer formed in the semiconductor substrate on the outer side of the first P-type diffusion layer opposite to the first N-type diffusion layer and connected to the cathode terminal; and a fifth N-type diffusion layer formed in the semiconductor substrate on the outer side of the second P-type diffusion layer opposite to the second N-type diffusion layer and connected to the cathode terminal.

11. The ESD protection diode according to claim 8, wherein the first N-type diffusion layer and the second N-type diffusion layer are formed in an N-type well within the semiconductor substrate, the third N-type diffusion layer is formed in a P-type well within the semiconductor substrate, the first N-type diffusion layer and the second N-type diffusion layer are the emitters of the lateral bipolar transistor, the P-type well is the base of the lateral bipolar transistor, the third N-type diffusion layer is the collector of the lateral bipolar transistor.

12. The ESD protection diode according to any one of claims 9 to 11, wherein the distance between the emitter and the collector of the lateral bipolar transistor is set to the minimum distance set according to a specified device breakdown voltage.

13. The ESD protection diode according to any one of claims 9 to 11, wherein the distance between the first P-type diffusion layer and the first N-type diffusion layer and the distance between the second P-type diffusion layer and the second N-type diffusion layer are set to the minimum distance set according to a specified device breakdown voltage.

14. A structure of an ESD protection diode, comprising two pairs of PN diodes respectively formed by P-type diffusion layers and N-type diffusion layers in a semiconductor substrate, wherein at a position of the semiconductor substrate sandwiched by the two pairs of PN diodes, a lateral bipolar transistor is provided, and the lateral bipolar transistor includes: diffusion layers of polarities different from the terminals connected to the cathode terminal or the anode terminal, the P-type diffusion layer, and the N-type diffusion layer.

15. The structure of the ESD protection diode as described in claim 14, wherein, the 2 pairs of PN diodes include: a first PN diode formed by a first P-type diffusion layer and a first N-type diffusion layer; and a second PN diode formed by a second P-type diffusion layer and a second N-type diffusion layer, the lateral bipolar transistor includes: a first P-type diffusion layer and a second P-type diffusion layer connected to the anode terminal; a third P-type diffusion layer formed at a position between the first P-type diffusion layer and the second P-type diffusion layer and connected to the cathode terminal; and the first N-type diffusion layer and the second N-type diffusion layer formed in an N-type well within the semiconductor substrate.

16. The structure of the ESD protection diode as described in claim 14, wherein, the 2 pairs of PN diodes include: a first PN diode formed by a first P-type diffusion layer and a first N-type diffusion layer; and a second PN diode formed by a second P-type diffusion layer and a second N-type diffusion layer, the lateral bipolar transistor includes: a first N-type diffusion layer and a second N-type diffusion layer connected to the cathode terminal; a third N-type diffusion layer formed at a position between the first N-type diffusion layer and the second N-type diffusion layer and connected to the anode terminal; and the first P-type diffusion layer and the second P-type diffusion layer formed in a P-type well within the semiconductor substrate.

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