Dichotomy-based data quantification method, apparatus and device, and storage medium
The binary search-based data quantization method addresses resource and time inefficiencies in phase calculation by iteratively assigning phase values and compensating residuals, enhancing precision and efficiency in large-scale phased array antennas.
Patent Information
- Application Number
- CN202510435403.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-08
- Publication Date
- 2025-07-15
AI Technical Summary
The phase calculation methods of existing phased array antennas have problems such as large resource consumption and long time consumption, especially in large-scale phased array antennas, it is difficult to meet the computing needs.
The data quantization method based on dichotomy is used to determine whether the current phase is greater than or equal to the phase corresponding to the current phase shifter's current bit, and initial quantization is performed through dichotomy, and then error compensation is performed on the residual phase to obtain the phase shifter data quantization result.
It improves the accuracy and efficiency of data quantization, reduces resource usage, and is especially suitable for large-scale phased array antennas, reducing computing complexity and cost.
Smart Images
Figure CN120314647A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of phased array antennas, and particularly to a data quantization method, device, equipment, and storage medium based on the dichotomy method. Background Art
[0002] A phased array antenna is an antenna system that realizes beamforming and pointing by controlling the phase and amplitude of multiple antenna elements. Phase calculation is one of the core technologies in the design of phased array antennas. In the implementation process of phased array antennas, for large-scale phased array antennas based on the analog phase shifter architecture, after calculating the channel phase, it is necessary to convert the phase into a low-precision analog phase shifter CODE. A typical implementation method is to divide the phase by the precision of the analog phase shifter and round it to reduce the phase error. In large-scale phased array antennas, the number of array elements is more than 1000, and for phased array antennas supporting multiple beams, each beam needs to be calculated separately. The current phase calculation is implemented in the following ways:
[0003] 1. Implement using an FPGA divider. Using multiple dividers in parallel can reduce the time consumption, but it will occupy a large amount of logic resources and requires a high-performance FPGA to meet the requirements, resulting in a large overhead in resource consumption and power consumption.
[0004] 2. Implement using an FPGA look-up table. Using multiple data in parallel can reduce the time consumption, but it will occupy a large amount of logic resources, and as the number of bits of the phase shifter increases, the size of the table will increase exponentially.
[0005] 3. Implement using a DSP. Dependent on the hardware divider, in order to achieve a faster speed, a higher-specification DSP chip is usually required, resulting in an increase in hardware costs, and communication is required between the DSP and the FPGA, increasing the system complexity.
[0006] 4. Implement using an MCU. Usually, it can only perform serial calculations. Even if parallel calculations are performed, the number of parallel paths is small and it is difficult to meet the time requirements.
[0007] Therefore, there are problems of large resource consumption and long time consumption in current phase data quantization. Summary of the Invention
[0008] Based on this, it is necessary to provide a data quantization method, device, equipment, and storage medium based on the dichotomy method for the above technical problems.
[0009] A data quantization method based on the dichotomy method, the method includes:
[0010] Starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter;
[0011] If so, assign 1 to the current bit and subtract the phase corresponding to the current bit of the phase shifter from the current phase; otherwise, assign 0.
[0012] After completing the assignment of all bits of the phase shifter, an initial quantization code is obtained.
[0013] Calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the phase shifter data quantization result.
[0014] In one embodiment, it further includes: calculating the residual phase after assignment includes:
[0015]
[0016] where ΔPHASE is the residual phase, bit(n - 1) is the quantization bit of the (n - 1)th bit, n is the quantization bit width, and PHASE is the phase corresponding to all bits of the phase shifter.
[0017] In one embodiment, it further includes: according to whether the residual phase is greater than or equal to If so, increment the phase quantization by 1.
[0018] In one embodiment, it further includes: adopting a pipeline mechanism to sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter starting from the highest bit of the phase shifter.
[0019] A data quantization device based on the dichotomy method, the device includes:
[0020] A judgment module, configured to sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter starting from the highest bit of the phase shifter;
[0021] An assignment module, configured to if so, assign 1 to the current bit, and subtract the phase corresponding to the current bit of the phase shifter from the current phase; otherwise, assign 0;
[0022] An initial quantization code calculation module, configured to obtain an initial quantization code after completing the assignment of all bits of the phase shifter;
[0023] A compensation module, configured to calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the phase shifter data quantization result.
[0024] A computer device includes a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:
[0025] Starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter;
[0026] If so, assign 1 to the current bit, and subtract the phase corresponding to the current bit of the phase shifter from the current phase, otherwise assign 0;
[0027] After completing the assignment of all bits of the phase shifter, obtain the initial quantization code;
[0028] Calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the quantization result of the phase shifter data.
[0029] A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:
[0030] Starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter;
[0031] If so, assign 1 to the current bit, and subtract the phase corresponding to the current bit of the phase shifter from the current phase, otherwise assign 0;
[0032] After completing the assignment of all bits of the phase shifter, obtain the initial quantization code;
[0033] Calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the quantization result of the phase shifter data.
[0034] The above data quantization method, device, equipment and storage medium based on the dichotomy method, by adopting the dichotomy method, starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter, perform initial quantization on the phase shifter, and then perform error compensation based on the residual phase after dichotomy quantization, further improving the accuracy of data quantization, and the dichotomy method does not rely on division operations, can improve the data quantization efficiency, and is particularly suitable for large-scale phased array antennas. Description of the Drawings
[0035] Figure 1 Is a schematic flowchart of a data quantization method based on the dichotomy method in an embodiment;
[0036] Figure 2 Is a structural block diagram of a data quantization device based on the dichotomy method in an embodiment;
[0037] Figure 3 Is an internal structure diagram of a computer device in an embodiment. Detailed Embodiment
[0038] To make the objectives, technical solutions and advantages of this application more clear and understandable, the following further elaborates on this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.
[0039] In one embodiment, as Figure 1 shown, a data quantization method based on the dichotomy is provided, including the following steps:
[0040] Step 102: Starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter.
[0041] Taking a 6-bit phase shifter as an example, the highest bit is Bit5. Sequentially judge, the last bit is Bit0. The phases that the phase shifter can take effect are 2 6 ^6 = 64 kinds. The phases corresponding to each bit are shown in Table 1:
[0042] Table 1 Phase table corresponding to bits
[0043] Bit Phase Bit 5 180° Bit 4 90° Bit 3 45° Bit 2 22.5° Bit 1 11.25° Bit 0 5.625°
[0044] Step 104: If so, assign 1 to the current bit and subtract the phase corresponding to the current bit of the phase shifter from the current phase; otherwise, assign 0.
[0045] Through the dichotomy, only the magnitudes of the phase and the phase represented by the corresponding bit need to be judged for each clock.
[0046] Compared with the look-up table method, the resource occupancy is
[0047] Quantization bit width Resource occupancy saving 5 15.625％ 6 9.375％ 7 5.469％ 8 3.125％
[0048] Step 106: After completing the assignment of all bits of the phase shifter, obtain the initial quantization code.
[0049] Step 108: Calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the data quantization result of the phase shifter.
[0050] Due to the phase discretization problem caused by phase quantization, it has a great impact on the sidelobe level after phased array beamforming. Therefore, when using a divider for phase quantization, rounding is usually used to reduce the discretization problem caused by phase quantization. In this embodiment, after calculating Bit0, a residual phase will be obtained, and this residual phase is the quantization error of phase quantization by the dichotomy.
[0051] In the above data quantization method based on the dichotomy method, by adopting the dichotomy method, starting from the highest bit of the phase shifter, it is successively determined whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter, and the phase shifter is initially quantized. Then, based on the residual phase after dichotomy quantization, error compensation is performed, further improving the accuracy of data quantization. Moreover, the dichotomy method does not rely on division operations, can improve data quantization efficiency, and is particularly suitable for large-scale phased array antennas.
[0052] In one embodiment, calculating the residual phase after assignment includes:
[0053]
[0054] Where, ΔPHASE is the residual phase, bit(n - 1) is the quantization bit of the (n - 1)th bit, n is the quantization bit width, and PHASE is the phase corresponding to all bits of the phase shifter.
[0055] In this embodiment, in order to reduce the influence of quantization error, the residual phase needs to be further quantized to reduce the quantization error. When the phase quantization of Bit0 is completed, quantization compensation needs to be performed on the residual phase to As the quantization compensation reference phase, when the residual phase is greater than or equal to the quantization compensation reference phase, the obtained phase quantization CODE + 1, otherwise no processing is performed. By doing so, the quantization error of the phase is reduced to half of the accuracy of the phase shifter.
[0056] Performing phase quantization by the dichotomy method requires (N + 1)T clocks to complete quantization, which is N + 1 times that of the look-up table method. In order to improve the time overhead of the dichotomy method, it is designed with a pipeline structure. As the number of required quantization calculations increases, the additional time overhead brought by the dichotomy method can be ignored. The time required for the dichotomy method is N + NUM, where N is the quantization bit width and NUM is the number of calculations required.
[0057]
[0058] The additional time overhead shown in the above table refers to the calculation speed compared with the look-up table method under the single-channel pipeline structure.
[0059] In one embodiment, adopting a pipeline mechanism, starting from the highest bit of the phase shifter, it is successively determined whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter. Due to the reduction in resource consumption brought by the dichotomy method, in practical applications, if there are sufficient resources, multi-channel parallel calculations can be realized, and the calculation speed of the dichotomy method will be faster than that of the look-up table method. Taking the dichotomy method and the look-up table method using the same resources as an example, the following table shows the processing speed of the dichotomy method relative to the look-up table method under the same resource consumption.
[0060]
[0061] It should be understood that although Figure 1 the steps in the flowchart are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 at least a part of the steps in
[0062] In one embodiment, as Figure 2 shown, a data quantization device based on the dichotomy method is provided, including: a judgment module 202, an assignment module 204, an initial quantization code calculation module 206, and a compensation module 208, where:
[0063] The judgment module 202 is configured to sequentially judge whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter starting from the highest bit of the phase shifter;
[0064] The assignment module 204 is configured to, if so, assign 1 to the current bit and subtract the phase corresponding to the current bit of the phase shifter from the current phase, otherwise assign 0;
[0065] The initial quantization code calculation module 206 is configured to obtain an initial quantization code after the assignment of all bits of the phase shifter is completed;
[0066] The compensation module 208 is configured to calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to a compensation threshold to obtain the phase shifter data quantization result.
[0067] In one of the embodiments, the compensation module 208 is further configured to calculate the residual phase after assignment, including:
[0068]
[0069] where ΔPHASE is the residual phase, bit(n - 1) is the quantization bit of the (n - 1)th bit, n is the quantization bit width, and PHASE is the phase corresponding to all bits of the phase shifter.
[0070] In one of the embodiments, the compensation module 208 is further configured to, according to whether the residual phase is greater than or equal to If so, increment the phase quantization by 1.
[0071] In one embodiment, the determination module is further configured to adopt a pipeline mechanism to sequentially determine, starting from the highest bit of the phase shifter, whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter.
[0072] For the specific limitations on the data quantization device based on the dichotomy method, reference can be made to the limitations on the data quantization method based on the dichotomy method in the foregoing text, which will not be elaborated herein. Each module in the above-mentioned data quantization device based on the dichotomy method can be implemented in whole or in part by software, hardware, and their combination. The above-mentioned modules can be embedded in the processor in the computer device in hardware form or independent of the processor, or stored in the memory in the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to each of the above modules.
[0073] In one embodiment, a computer device is provided. The computer device can be a terminal, and its internal structure diagram can be as Figure 3 shown. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a data quantization method based on the dichotomy method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.
[0074] Those skilled in the art can understand that Figure 3 the structure shown in
[0075] is only a block diagram of some structures related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine some components, or have different component arrangements.
[0076] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the steps of the method in the above embodiment.
[0077] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.
[0078] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.
[0079] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.
Claims
1. A data quantization method based on the dichotomy, characterized in that The method includes: Starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter; If so, assign 1 to the current bit, and subtract the phase corresponding to the current bit of the phase shifter from the current phase, otherwise assign 0; After completing the assignment of all bits of the phase shifter, obtain the initial quantization code; Calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the quantization result of the phase shifter data.
2. The method according to claim 1, wherein The calculation of the residual phase after assignment includes: The calculation of the residual phase after assignment includes: Where, ΔPHASE is the residual phase, bit(n - 1) is the quantization bit of the (n - 1)th bit, n is the quantization bit width, and PHASE is the phase corresponding to all bits of the phase shifter.
3. The method according to claim 1, characterized in that, Compensating the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold includes: According to whether the residual phase is greater than or equal to If so, increment the phase quantization by 1.
4. The method according to any one of claims 1 to 3, characterized in that The method further includes: Adopting a pipeline mechanism, starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter.
5. A data quantization device based on the dichotomy method, characterized in that The device includes: A judgment module, configured to start from the highest bit of the phase shifter and sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter; An assignment module, configured to, if so, assign 1 to the current bit, and subtract the phase corresponding to the current bit of the phase shifter from the current phase, otherwise assign 0; An initial quantization code calculation module, configured to obtain the initial quantization code after completing the assignment of all bits of the phase shifter; A compensation module, configured to calculate the residual phase after assignment, and compensate the initial quantization code according to whether the residual phase is greater than or equal to the compensation threshold to obtain the quantization result of the phase shifter data.
6. The device according to claim 5, characterized in that, The compensation module is further configured to calculate the residual phase after assignment, including: Where, ΔPHASE is the residual phase, bit(n - 1) is the quantization bit of the (n - 1)th bit, n is the quantization bit width, and PHASH is the phase corresponding to all bits of the phase shifter.
7. The device according to claim 5, characterized in that, The compensation module is further configured to determine whether the residual phase is greater than or equal to If so, increment the phase quantization by 1.
8. The device according to any one of claims 5 to 7, characterized in that, The judgment module is further configured to adopt a pipeline mechanism, starting from the highest bit of the phase shifter, sequentially determine whether the current phase is greater than or equal to the phase corresponding to the current bit of the phase shifter.
9. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 7.
10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the method according to any one of claims 1 to 7.