Band-gap reference circuit and method applied to wide power supply voltage input range
The bandgap reference circuit addresses the instability of traditional designs by using transistor and resistor configurations with feedback loops to maintain stable operation across varying voltages, preventing transistor breakdown and ensuring reliable chip performance.
Patent Information
- Application Number
- CN202510582887.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-07
- Publication Date
- 2025-07-15
AI Technical Summary
Traditional bandgap reference circuits cannot operate stably under high power supply voltage and low power supply voltage, affecting chip performance.
The circuit structure consisting of transistors, low-voltage and high-voltage NMOS/PMOS tubes, operational amplifiers and zener diodes is adopted. Through the combination of positive feedback loops and negative feedback loops, the circuit can be ensured to operate stably within a wide power supply voltage range, and the tube breakdown is avoided through Zener diode clamps.
The bandgap reference circuit is realized stably working within a wide power supply voltage range, avoiding circuit damage caused by voltage fluctuations, and ensuring that the chip starts and works normally under low voltage and high voltage.
Smart Images
Figure CN120315528A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a bandgap reference circuit and method, in particular to a bandgap reference circuit and method applicable to a wide power supply voltage input range, belonging to the technical field of semiconductor integrated circuits. Background Art
[0002] As an important part of many analog circuits and mixed-signal circuits, the bandgap reference circuit provides the required reference voltage and bias current for the normal operation of the circuit. In some applications with a relatively wide power supply voltage input range, the externally input power supply voltage fluctuates greatly, and the bandgap reference circuit is required to work normally and stably under both high and low power supply voltages. Therefore, expanding the operating voltage range of the bandgap reference circuit is crucial for chip performance.
[0003] The structural block diagram of a traditional bandgap reference circuit applied to a high power supply voltage is as Figure 3 shown. Its basic principle is to first step down the high power supply voltage input by the external power supply module through a pre-regulator circuit to obtain an internal low-voltage power supply. This power supply provides a low-voltage power supply for the bandgap reference circuit to ensure that the core bandgap reference circuit is not damaged by the high power supply voltage breakdown. The common structure of the pre-regulator circuit is as Figure 4 shown. When the power supply voltage VBAT input by the external power supply module is relatively low, the Zener diode Z1 will not undergo Zener breakdown and conduct. Therefore, the gate voltage of the high-voltage NMOS transistor NDM1 is equal to the power supply voltage VBAT input by the external power supply module, and the internal power supply voltage VDD output by the pre-regulator circuit is equal to VBAT - VGSN1. When the power supply voltage VBAT input by the external power supply module is greater than the clamping voltage Vclamp1 of the Zener diode, the Zener diode Z1 will undergo Zener breakdown and conduct. At this time, the gate voltage of the high-voltage NMOS transistor NDM1 is equal to the clamping voltage Vclamp1 of the Zener diode Z1, and the internal power supply voltage VDD output by the pre-regulator circuit is equal to Vclamp1 - VGSN1. Through the above analysis, it can be seen that the internal power supply voltage VDD output by the pre-regulator circuit is at least one VGSN1 smaller than the power supply voltage VBAT input by the external power supply module. When the power supply voltage VBAT input by the external power supply module is small, the output VDD of the pre-regulator circuit is even smaller, which does not meet the minimum operating voltage of the bandgap reference circuit, thus affecting the normal operation of the system. In addition, generally, the output reference voltage of the bandgap reference circuit is used as a reference voltage for the undervoltage lockout module of the chip. During the power-on process, since the internal power supply voltage VDD output by the pre-regulator circuit is smaller than the power supply voltage VBAT input by the external power supply module, the reference voltage cannot be established in time, resulting in the failure of the undervoltage lockout module of the chip. Therefore, it cannot be guaranteed that the bandgap reference circuit can work normally and stably under both high and low power supply voltages, greatly affecting chip performance. Summary of the Invention
[0004] The technical problem to be solved by the present invention is to provide a bandgap reference circuit and method applicable to a wide power supply voltage input range, which can work stably under both low voltage and high voltage.
[0005] To solve the above technical problem, the technical solution adopted by the present invention is: A bandgap reference circuit applicable to a wide power supply voltage input range includes a triode Q1, a triode Q2, a low-voltage operational amplifier AMP1, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor NDM3, a low-voltage PMOS transistor PM1, a low-voltage PMOS transistor PM2, a high-voltage PMOS transistor PDM3, a high-voltage PMOS transistor PDM4, and resistors R3 to R6. The source electrodes of the high-voltage PMOS transistor PDM3 and the high-voltage PMOS transistor PDM4 are connected to the power supply VBAT. The gate electrodes of the high-voltage PMOS transistor PDM3 and the high-voltage PMOS transistor PDM4, the drain electrode of the high-voltage PMOS transistor PDM3, and the drain electrode of the high-voltage NMOS transistor NDM3 are connected and connected to the bias voltage VB1. The drain electrode of the high-voltage PMOS transistor PDM4, the source electrode of the low-voltage PMOS transistor PM2, the power supply terminal of the low-voltage operational amplifier AMP1, and the source electrode of the low-voltage PMOS transistor PM1 are connected to the internal power supply VDD. The gate electrodes of the low-voltage PMOS transistor PM2 and the low-voltage PMOS transistor PM1, the drain electrode of the low-voltage PMOS transistor PM1, one end of the resistor R5, and one end of the resistor 6 are connected to the bias voltage VB2. The drain electrode of the low-voltage PMOS transistor PM2 is connected to the gate electrode of the high-voltage NMOS transistor NDM3 and the drain electrode of the low-voltage NMOS transistor NM6. The gate electrode of the low-voltage NMOS transistor NM6 is connected to the output terminal of the low-voltage operational amplifier AMP1. The other end of the resistor R5 is connected to the inverting input terminal of the low-voltage operational amplifier AMP1, the collector of the triode Q1, the base of the triode Q1, and the base of the triode Q2 to generate the voltage VBG. The other end of the resistor R6 is connected to the non-inverting input terminal of the low-voltage operational amplifier AMP1 and the collector of the triode Q2. The emitter of the triode Q2 is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the emitter of the triode Q1 and one end of the resistor R3. The source electrode of the low-voltage NMOS transistor NM6, the source electrode of the high-voltage NMOS transistor NDM3, the ground terminal of the low-voltage operational amplifier AMP1, and the other end of the resistor R3 are grounded.
[0006] Further, the low-voltage NMOS transistor NM6 and the low-voltage PMOS transistor PM2 form a first common-source amplifier, and the high-voltage NMOS transistor NDM3 and the high-voltage PMOS transistor PDM3 form a second common-source amplifier.
[0007] Further, the high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the transistor Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the transistor Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop, and the gain of the negative feedback loop is greater than that of the positive feedback loop.
[0008] Further, it also includes a Zener diode Z2 and a Zener diode Z3. The cathode of the Zener diode Z2 is connected to the power supply VBAT, and the anode of the Zener diode Z2 is connected to the gates of the high-voltage PMOS transistor PDM3 and the high-voltage PMOS transistor PDM4. The cathode of the Zener diode Z3 is connected to the internal power supply VDD, and the other end of the Zener diode Z3 is grounded.
[0009] Further, it also includes a startup circuit. The startup circuit includes a high-voltage Wilson current source, a low-voltage PMOS transistor PM3, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, and a high-voltage NMOS transistor NDM2. The source of the low-voltage PMOS transistor PM3 is connected to the internal power supply VDD, the gate of the low-voltage PMOS transistor PM3 is connected to the bias voltage VB2, and the drain of the low-voltage PMOS transistor PM3 is connected to the drains, gates of the low-voltage NMOS transistor NM2 and the low-voltage NMOS transistor NM3. The drain of the low-voltage NMOS transistor NM3 is connected to the output terminal of the high-voltage Wilson current source, the drains, gates of the low-voltage NMOS transistor NM4, the gate of the high-voltage NMOS transistor NDM2, and the gate of the low-voltage NMOS transistor NM5. The drain of the high-voltage NMOS transistor NDM2 outputs the bias voltage VB1, the drain of the low-voltage NMOS transistor NM5 outputs the bias voltage VB2, and the sources of the low-voltage NMOS transistor NM2, the low-voltage NMOS transistor NM3, the low-voltage NMOS transistor NM4, the high-voltage NMOS transistor NDM2, and the low-voltage NMOS transistor NM5 are grounded.
[0010] Further, the high-voltage Wilson current source includes a resistor R1, a resistor R2, a Zener diode Z1, a low-voltage NMOS transistor NM1, a high-voltage NMOS transistor NDM1, a high-voltage PMOS transistor PDM1, and a high-voltage PMOS transistor PDM2. One end of the resistor R1, the source electrodes of the high-voltage PMOS transistors PDM1 and PDM2 are connected to the power supply VBAT. The other end of the resistor R1 is connected to the drain of the low-voltage NMOS transistor NM1, the cathode of the Zener diode Z1, and the gate of the high-voltage NDM1. The gate of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor NDM1 and one end of the resistor R2. The drain of the high-voltage NMOS transistor NDM1 is connected to the drain of the high-voltage PMOS transistor PDM1, the upper stage of the high-voltage PMOS transistor PDM1, and the gate of the high-voltage PMOS transistor PDM2. The drain of the high-voltage PMOS transistor PDM2 serves as the output terminal of the high-voltage Wilson current source. The source of the low-voltage NMOS transistor NM1, the anode of the Zener diode Z1, and the other end of the resistor R2 are grounded.
[0011] A control method for a bandgap reference circuit applied to a wide power supply voltage input range includes the following steps: The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the transistor Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the transistor Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. Since the gain of the negative feedback loop is greater than the gain of the positive feedback loop, the overall bandgap reference circuit is a negative feedback loop, and thus it operates stably through negative feedback compensation. One end of the resistor R5 and one end of the resistor R6 are connected so that the voltages are equal. The positive input terminal and the negative input terminal of the low-voltage operational amplifier AMP1 clamp the voltages at the other ends of the resistor R5 and the resistor R6 to be equal through negative feedback, making the voltage drops across the resistor R5 and the resistor R6 equal. If the resistances of the resistor R5 and the resistor R6 are the same, the currents flowing through the resistor R5 and the resistor R6 are equal. Without considering the base currents of transistor Q1 and transistor Q2, the currents flowing through transistor Q1 and transistor Q2 are equal. Since the areas of transistor Q1 and transistor Q2 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltage VBE1 of transistor Q1 and the base-emitter voltage VBE2 of transistor Q2. The voltage △VBE with a positive temperature coefficient is divided by the zero-temperature coefficient resistor R4 to generate a current Iptat with a positive temperature coefficient. Since the two currents are equal, the current flowing through the zero-temperature coefficient resistor R3 is 2*Iptat, and the voltage across the zero-temperature coefficient resistor R3 is a voltage 2*Iptat*R3 with a positive temperature coefficient. The voltage 2*Iptat*R3 with a positive temperature coefficient plus the voltage VBE1 with a negative temperature coefficient results in a voltage VBG with a zero temperature coefficient. The voltage of the internal power supply VDD is equal to the voltage VBG with a zero temperature coefficient plus the voltage drop across resistor R5 plus the gate-source voltage |VGSP1| of the low-voltage PMOS transistor PM1, that is, VDD = VBG + Iptat*R5 + |VGSP1|. The internal power supply VDD serves as the power supply voltage of the bandgap reference circuit to ensure the normal operation of the bandgap reference circuit. When the power supply VBAT is powered on, the gate voltage of the high-voltage NMOS transistor NDM1 is pulled up through resistor R1, causing the high-voltage NMOS transistor NDM1 to conduct. The current generated by the conduction of the high-voltage NMOS transistor NDM1 passes through resistor R2 to generate a voltage drop, pulling up the gate voltage of the low-voltage NMOS transistor NM1 and causing the low-voltage NMOS transistor NM1 to conduct. The Zener diode Z1 clamps the gate-source voltage VGSN1 of the high-voltage NMOS transistor NDM1 and the drain-source voltage VDSN1 of the low-voltage NMOS transistor NM1 to be lower than the clamping voltage Vclamp1 of the Zener diode Z1, preventing the gate-source of the high-voltage NMOS transistor NDM1 and the drain-source of the low-voltage NMOS transistor NM1 from being broken down. The output current Istart of the high-voltage Wilson current source is equal to the gate-source voltage VGSN1 of the low-voltage NMOS transistor NM1 divided by resistor R2, that is, Istart = VGSN1 / R2. The current Istart flows into the diode-connected low-voltage NMOS transistor NM4 through the current mirror composed of the high-voltage PMOS transistors PDM1 and PDM2, causing the gate voltages of the low-voltage NMOS transistor NM4, the low-voltage NMOS transistor NM5, and the high-voltage NMOS transistor NDM2 to increase and thus conduct. After conduction, the high-voltage NMOS transistor NDM2 pulls down the gate voltages of the high-voltage PMOS transistors PDM3 and PDM4 through the bias voltage VB1, causing the high-voltage PMOS transistors PDM3 and PDM4 to conduct; after conduction, the low-voltage NMOS transistor NM5 pulls down the gate voltages of the low-voltage PMOS transistors PM1, PM2, and PM3 through the bias voltage VB2, causing the low-voltage PMOS transistors PM1, PM2, and PM3 to conduct; the current of the low-voltage PMOS transistor PM3 flows into the NMOS current mirror composed of the low-voltage NMOS transistors NM2 and NM3, causing the low-voltage NMOS transistors NM2 and NM3 to conduct; the current Istart that previously flowed into the low-voltage NMOS transistor NM4 flows into the low-voltage NMOS transistor NM3, thereby turning off the low-voltage NMOS transistors NM4 and NM5 and the high-voltage NMOS transistor NDM2, ensuring that the startup circuit is turned off after the circuit starts and operates normally.
[0012] Compared with the prior art, the present invention has the following advantages and effects: The present invention discloses a bandgap reference circuit and method applicable to a wide power supply voltage input range, which does not require a pre-regulator circuit and can operate stably under low voltage and high voltage; the startup circuit can operate stably under low voltage and high voltage, and can ensure that the bandgap reference circuit gets rid of the degeneracy point and operates normally. Brief Description of the Drawings
[0013] Figure 1 is a schematic diagram of a bandgap reference circuit of the present invention applicable to a wide power supply voltage input range.
[0014] Figure 2 is a schematic diagram of the startup circuit of the present invention.
[0015] Figure 3 is a schematic diagram of a bandgap reference circuit of the prior art applicable to high voltage.
[0016] Figure 4 is a schematic diagram of a pre-regulator circuit of the prior art under high power supply voltage. Detailed Description of the Embodiment
[0017] In order to elaborate in detail on the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments. And, without creative labor, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.
[0018] Such as Figure 1As shown in the figure, a bandgap reference circuit applied to a wide power supply voltage input range according to the present invention includes a triode Q1, a triode Q2, a low-voltage operational amplifier AMP1, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor NDM3, a low-voltage PMOS transistor PM1, a low-voltage PMOS transistor PM2, a high-voltage PMOS transistor PDM3, a high-voltage PMOS transistor PDM4, and resistors R3 to R6. The source of the high-voltage PMOS transistor PDM3 and the source of the high-voltage PMOS transistor PDM4 are connected to the power supply VBAT. The gate of the high-voltage PMOS transistor PDM3 is connected to the gate of the high-voltage PMOS transistor PDM4, the drain of the high-voltage PMOS transistor PDM3, and the drain of the high-voltage NMOS transistor NDM3 and is connected to the bias voltage VB1. The drain of the high-voltage PMOS transistor PDM4, the source of the low-voltage PMOS transistor PM2, the power supply terminal of the low-voltage operational amplifier AMP1, and the source of the low-voltage PMOS transistor PM1 are connected to the internal power supply VDD. The gate of the low-voltage PMOS transistor PM2 and the gate of the low-voltage PMOS transistor PM1, the drain of the low-voltage PMOS transistor PM1, one end of the resistor R5, and one end of the resistor 6 are connected to the bias voltage VB2. The drain of the low-voltage PMOS transistor PM2 is connected to the gate of the high-voltage NMOS transistor NDM3 and the drain of the low-voltage NMOS transistor NM6. The gate of the low-voltage NMOS transistor NM6 is connected to the output terminal of the low-voltage operational amplifier AMP1. The other end of the resistor R5 is connected to the inverting input terminal of the low-voltage operational amplifier AMP1, the collector of the triode Q1, the base of the triode Q1, and the base of the triode Q2 and generates the voltage VBG. The other end of the resistor R6 is connected to the non-inverting input terminal of the low-voltage operational amplifier AMP1 and the collector of the triode Q2. The emitter of the triode Q2 is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the emitter of the triode Q1 and one end of the resistor R3. The source of the low-voltage NMOS transistor NM6, the source of the high-voltage NMOS transistor NDM3, the ground terminal of the low-voltage operational amplifier AMP1, and the other end of the resistor R3 are grounded.
[0019] Among them, the low-voltage NMOS transistor NM6 and the low-voltage PMOS transistor PM2 form a first common-source amplifier, and the high-voltage NMOS transistor NDM3 and the high-voltage PMOS transistor PDM3 form a second common-source amplifier.
[0020] The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the triode Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the triode Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. The gain of the negative feedback loop is greater than the gain of the positive feedback loop.
[0021] A bandgap reference circuit applied to a wide power supply voltage input range according to the present invention further includes a Zener diode Z2 and a Zener diode Z3. The cathode of the Zener diode Z2 is connected to the power supply VBAT, and the anode of the Zener diode Z2 is connected to the gates of the high-voltage PMOS transistor PDM3 and the high-voltage PMOS transistor PDM4. The cathode of the Zener diode Z3 is connected to the internal power supply VDD, and the other end of the Zener diode Z3 is grounded. To ensure the reliability of the circuit and avoid overvoltage damage to the circuit in extreme cases. The Zener diode Z2 is used to clamp the gate-source voltage VGSP of the high-voltage PMOS transistors PDM3 and PDM4 in the PMOS current mirror to be lower than the clamping voltage Vclamp2 of the Zener diode Z2, avoiding breakdown of the gate-source of the high-voltage PMOS transistor. The Zener diode Z3 is used to clamp the internal power supply VDD voltage to be lower than the clamping voltage Vclamp3 of the Zener diode Z3, avoiding damage to the low-voltage circuit under the internal power supply VDD voltage due to high voltage breakdown.
[0022] A bandgap reference circuit applied to a wide power supply voltage input range according to the present invention further includes a startup circuit, as Figure 2 shown. The startup circuit includes a high-voltage Wilson current source, a low-voltage PMOS transistor PM3, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, and a high-voltage NMOS transistor NDM2. The source of the low-voltage PMOS transistor PM3 is connected to the internal power supply VDD, the gate of the low-voltage PMOS transistor PM3 is connected to the bias voltage VB2, and the drain of the low-voltage PMOS transistor PM3 is connected to the drain, gate of the low-voltage NMOS transistor NM2, and the gate of the low-voltage NMOS transistor NM3. The drain of the low-voltage NMOS transistor NM3 is connected to the output terminal of the high-voltage Wilson current source, the drain of the low-voltage NMOS transistor NM4, the gate of the low-voltage NMOS transistor NM4, the gate of the high-voltage NMOS transistor NDM2, and the gate of the low-voltage NMOS transistor NM5. The drain of the high-voltage NMOS transistor NDM2 outputs the bias voltage VB1, and the drain of the low-voltage NMOS transistor NM5 outputs the bias voltage VB2. The sources of the low-voltage NMOS transistor NM2, the low-voltage NMOS transistor NM3, the low-voltage NMOS transistor NM4, the high-voltage NMOS transistor NDM2, and the low-voltage NMOS transistor NM5 are grounded.
[0023] The high-voltage Wilson current source includes a resistor R1, a resistor R2, a Zener diode Z1, a low-voltage NMOS transistor NM1, a high-voltage NMOS transistor NDM1, a high-voltage PMOS transistor PDM1, and a high-voltage PMOS transistor PDM2. One end of the resistor R1, the source electrodes of the high-voltage PMOS transistors PDM1 and PDM2 are connected to the power supply VBAT. The other end of the resistor R1 is connected to the drain of the low-voltage NMOS transistor NM1, the cathode of the Zener diode Z1, and the gate of the high-voltage NDM1. The gate of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor NDM1 and one end of the resistor R2. The drain of the high-voltage NMOS transistor NDM1 is connected to the drain of the high-voltage PMOS transistor PDM1, the upper stage of the high-voltage PMOS transistor PDM1, and the gate of the high-voltage PMOS transistor PDM2. The drain of the high-voltage PMOS transistor PDM2 serves as the output terminal of the high-voltage Wilson current source. The source of the low-voltage NMOS transistor NM1, the anode of the Zener diode Z1, and the other end of the resistor R2 are grounded.
[0024] A control method for a bandgap reference circuit applied to a wide power supply voltage input range includes the following steps: The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the transistor Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the transistor Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. Since the gain of the negative feedback loop is greater than the gain of the positive feedback loop, the overall bandgap reference circuit is a negative feedback loop, thus stabilizing the operation through negative feedback compensation.
[0025] One end of the resistor R5 and one end of the resistor R6 are connected so that the voltages are equal. The positive input terminal and the negative input terminal of the low-voltage operational amplifier AMP1 clamp the voltages at the other ends of the resistor R5 and the resistor R6 to be equal through negative feedback, making the voltage drops across the resistor R5 and the resistor R6 equal. If the resistances of the resistor R5 and the resistor R6 are the same, the currents flowing through the resistor R5 and the resistor R6 are equal.
[0026] Without considering the base currents of transistor Q1 and transistor Q2, the currents flowing through transistor Q1 and transistor Q2 are equal. Since the areas of transistor Q1 and transistor Q2 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltage VBE1 of transistor Q1 and the base-emitter voltage VBE2 of transistor Q2. The voltage △VBE with a positive temperature coefficient is divided by the zero-temperature coefficient resistor R4 to generate a current Iptat with a positive temperature coefficient. Since the two currents are equal, the current flowing through the zero-temperature coefficient resistor R3 is 2*Iptat, and the voltage across the zero-temperature coefficient resistor R3 is a voltage 2*Iptat*R3 with a positive temperature coefficient. The voltage 2*Iptat*R3 with a positive temperature coefficient plus the voltage VBE1 with a negative temperature coefficient results in a voltage VBG with a zero temperature coefficient.
[0027] The voltage of the internal power supply VDD is equal to the voltage VBG with a zero temperature coefficient plus the voltage drop across resistor R5 plus the gate-source voltage |VGSP1| of the low-voltage PMOS transistor PM1, that is, VDD = VBG + Iptat*R5 + |VGSP1|; the internal power supply VDD, as the power supply voltage of the bandgap reference circuit, ensures the normal operation of the bandgap reference circuit.
[0028] When the power supply VBAT is powered on, the gate voltage of the high-voltage NMOS transistor NDM1 is pulled up through the resistor R1, making the high-voltage NMOS transistor NDM1 conduct. The current generated by the conduction of the high-voltage NMOS transistor NDM1 passes through the resistor R2 to generate a voltage drop to pull up the gate voltage of the low-voltage NMOS transistor NM1, making the low-voltage NMOS transistor NM1 conduct. Therefore, the high-voltage Wilson current source has no degeneracy point and can operate normally after the power supply is powered on.
[0029] The Zener diode Z1 clamps the gate-source voltage VGSN1 of the high-voltage NMOS transistor NDM1 and the drain-source voltage VDSN1 of the low-voltage NMOS transistor NM1 to be lower than the clamping voltage Vclamp1 of the Zener diode Z1, avoiding breakdown of the gate-source of the high-voltage NMOS transistor NDM1 and the drain-source of the low-voltage NMOS transistor NM1.
[0030] The output current Istart of the high-voltage Wilson current source is equal to the gate-source voltage VGSN1 of the low-voltage NMOS transistor NM1 divided by the resistor R2, that is, Istart = VGSN1 / R2; the current Istart flows into the diode-connected low-voltage NMOS transistor NM4 through the current mirror composed of the high-voltage PMOS transistors PDM1 and PDM2, causing the gate voltages of the low-voltage NMOS transistor NM4, the low-voltage NMOS transistor NM5, and the high-voltage NMOS transistor NDM2 to increase and then conduct.
[0031] After conduction, the high-voltage NMOS transistor NDM2 pulls down the gate voltages of the high-voltage PMOS transistors PDM3 and PDM4 through the bias voltage VB1, causing the high-voltage PMOS transistors PDM3 and PDM4 to conduct; after conduction, the low-voltage NMOS transistor NM5 pulls down the gate voltages of the low-voltage PMOS transistors PM1, PM2, and PM3 through the bias voltage VB2, causing the low-voltage PMOS transistors PM1, PM2, and PM3 to conduct; the current of the low-voltage PMOS transistor PM3 flows into the NMOS current mirror composed of the low-voltage NMOS transistors NM2 and NM3, causing the low-voltage NMOS transistors NM2 and NM3 to conduct; the current Istart that previously flowed into the low-voltage NMOS transistor NM4 now flows into the low-voltage NMOS transistor NM3, thereby turning off the low-voltage NMOS transistors NM4 and NM5 and the high-voltage NMOS transistor NDM2, ensuring that the startup circuit is turned off after the circuit starts and the circuit operates normally.
[0032] The present invention discloses a bandgap reference circuit and method applicable to a wide power supply voltage input range, which does not require a pre-regulator circuit and can operate stably under both low voltage and high voltage; the startup circuit can operate stably under both low voltage and high voltage and can ensure that the bandgap reference circuit operates normally away from the degeneracy point.
[0033] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or equivalents by using the disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the technical content of the present invention and is based on the spirit and principle of the present invention, any simple modification, equivalent replacement, and improvement of the above embodiments still fall within the protection scope of the technical solution of the present invention.
Claims
1. A bandgap reference circuit applicable to a wide power supply voltage input range, characterized in that: It includes a triode Q1, a triode Q2, a low-voltage operational amplifier AMP1, a low-voltage NMOS transistor NM6, a high-voltage NMOS transistor NDM3, a low-voltage PMOS transistor PM1, a low-voltage PMOS transistor PM2, a high-voltage PMOS transistor PDM3, a high-voltage PMOS transistor PDM4, and resistors R3 to R6. The source of the high-voltage PMOS transistor PDM3 and the source of the high-voltage PMOS transistor PDM4 are connected to the power supply VBAT. The gate of the high-voltage PMOS transistor PDM3 is connected to the gate of the high-voltage PMOS transistor PDM4, the drain of the high-voltage PMOS transistor PDM3, and the drain of the high-voltage NMOS transistor NDM3 and is connected to the bias voltage VB1. The drain of the high-voltage PMOS transistor PDM4, the source of the low-voltage PMOS transistor PM2, the power supply terminal of the low-voltage operational amplifier AMP1, and the source of the low-voltage PMOS transistor PM1 are connected to the internal power supply VDD. The gate of the low-voltage PMOS transistor PM2 and the gate of the low-voltage PMOS transistor PM1, the drain of the low-voltage PMOS transistor PM1, one end of the resistor R5, and one end of the resistor 6 are connected to the bias voltage VB2. The drain of the low-voltage PMOS transistor PM2 is connected to the gate of the high-voltage NMOS transistor NDM3 and the drain of the low-voltage NMOS transistor NM6. The gate of the low-voltage NMOS transistor NM6 is connected to the output terminal of the low-voltage operational amplifier AMP1. The other end of the resistor R5 is connected to the inverting input terminal of the low-voltage operational amplifier AMP1, the collector of the triode Q1, the base of the triode Q1, and the base of the triode Q2 and generates the voltage VBG. The other end of the resistor R6 is connected to the non-inverting input terminal of the low-voltage operational amplifier AMP1 and the collector of the triode Q2. The emitter of the triode Q2 is connected to one end of the resistor R4. The other end of the resistor R4 is connected to the emitter of the triode Q1 and one end of the resistor R3. The source of the low-voltage NMOS transistor NM6, the source of the high-voltage NMOS transistor NDM3, the ground terminal of the low-voltage operational amplifier AMP1, and the other end of the resistor R3 are grounded.
2. The bandgap reference circuit applied to a wide power supply voltage input range according to claim 1, characterized in that: The low-voltage NMOS transistor NM6 and the low-voltage PMOS transistor PM2 form a first common-source amplifier, and the high-voltage NMOS transistor NDM3 and the high-voltage PMOS transistor PDM3 form a second common-source amplifier.
3. A bandgap reference circuit applied to a wide power supply voltage input range according to claim 2, characterized in that: The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the triode Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the triode Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. The gain of the negative feedback loop is greater than the gain of the positive feedback loop.
4. A bandgap reference circuit applied to a wide power supply voltage input range according to claim 1, characterized in that: It also includes a Zener diode Z2 and a Zener diode Z3. The cathode of the Zener diode Z2 is connected to the power supply VBAT, and the anode of the Zener diode Z2 is connected to the gates of the high-voltage PMOS transistor PDM3 and the high-voltage PMOS transistor PDM4. The cathode of the Zener diode Z3 is connected to the internal power supply VDD, and the other end of the Zener diode Z3 is grounded.
5. The bandgap reference circuit applied to a wide power supply voltage input range according to claim 1, characterized in that: It also includes a startup circuit, which consists of a high-voltage Wilson current source, a low-voltage PMOS transistor PM3, a low-voltage NMOS transistor NM2, a low-voltage NMOS transistor NM3, a low-voltage NMOS transistor NM4, a low-voltage NMOS transistor NM5, and a high-voltage NMOS transistor NDM2. The source of the low-voltage PMOS transistor PM3 is connected to the internal power supply VDD. The gate of the low-voltage PMOS transistor PM3 is connected to the bias voltage VB2. The drain of the low-voltage PMOS transistor PM3 is connected to the drains, gates of the low-voltage NMOS transistor NM2 and the gate of the low-voltage NMOS transistor NM3. The drain of the low-voltage NMOS transistor NM3 is connected to the output terminal of the high-voltage Wilson current source, the drains, gates of the low-voltage NMOS transistor NM4, the gate of the high-voltage NMOS transistor NDM2, and the gate of the low-voltage NMOS transistor NM5. The drain of the high-voltage NMOS transistor NDM2 outputs the bias voltage VB1. The drain of the low-voltage NMOS transistor NM5 outputs the bias voltage VB2. The sources of the low-voltage NMOS transistor NM2, the low-voltage NMOS transistor NM3, the low-voltage NMOS transistor NM4, the high-voltage NMOS transistor NDM2, and the low-voltage NMOS transistor NM5 are grounded.
6. The bandgap reference circuit applied to a wide power supply voltage input range according to claim 5, wherein: The high-voltage Wilson current source includes a resistor R1, a resistor R2, a Zener diode Z1, a low-voltage NMOS transistor NM1, a high-voltage NMOS transistor NDM1, a high-voltage PMOS transistor PDM1, and a high-voltage PMOS transistor PDM2. One end of the resistor R1, the sources of the high-voltage PMOS transistor PDM1 and the high-voltage PMOS transistor PDM2 are connected to the power supply VBAT. The other end of the resistor R1 is connected to the drain of the low-voltage NMOS transistor NM1, the cathode of the Zener diode Z1, and the gate of the high-voltage NDM1. The gate of the low-voltage NMOS transistor NM1 is connected to the source of the high-voltage NMOS transistor NDM1 and one end of the resistor R2. The drain of the high-voltage NMOS transistor NDM1 is connected to the drains, upper stage of the high-voltage PMOS transistor PDM1, and the gate of the high-voltage PMOS transistor PDM2. The drain of the high-voltage PMOS transistor PDM2 serves as the output terminal of the high-voltage Wilson current source. The source of the low-voltage NMOS transistor NM1, the anode of the Zener diode Z1, and the other end of the resistor R2 are grounded.
7. A control method for a bandgap reference circuit applied to a wide power supply voltage input range as described in claim 6, characterized in that It includes the following steps: The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R5, the transistor Q1, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a positive feedback loop. The high-voltage PMOS transistor PDM4, the low-voltage PMOS transistor PM1, the resistor R6, the transistor Q2, the resistor R4, the resistor R3, the low-voltage operational amplifier AMP1, the first common-source amplifier, and the second common-source amplifier form a negative feedback loop. Since the gain of the negative feedback loop is greater than that of the positive feedback loop, the overall bandgap reference circuit is a negative feedback loop, thereby achieving stable operation through negative feedback compensation. One end of resistor R5 is connected to one end of resistor R6 so that the voltages are equal. The positive input terminal and the negative input terminal of the low-voltage operational amplifier AMP1 clamp the voltages at the other ends of resistor R5 and resistor R6 equal through negative feedback, making the voltage drops across resistor R5 and resistor R6 equal. Given that the resistances of resistor R5 and resistor R6 are the same, the currents flowing through resistor R5 and resistor R6 are equal. Without considering the base currents of transistor Q1 and transistor Q2, the currents flowing through transistor Q1 and transistor Q2 are equal. Since the areas of transistor Q1 and transistor Q2 are different, there is a voltage difference △VBE with a positive temperature coefficient between the base-emitter voltage VBE1 of transistor Q1 and the base-emitter voltage VBE2 of transistor Q2. The positive-temperature-coefficient voltage △VBE divided by the zero-temperature-coefficient resistor R4 generates a positive-temperature-coefficient current Iptat. Since the two currents are equal, the current flowing through the zero-temperature-coefficient resistor R3 is 2*Iptat, and the voltage across the zero-temperature-coefficient resistor R3 is a positive-temperature-coefficient voltage 2*Iptat*R3. The positive-temperature-coefficient voltage 2*Iptat*R3 plus the negative-temperature-coefficient voltage VBE1 results in a zero-temperature-coefficient voltage VBG. The voltage of the internal power supply VDD is equal to the zero-temperature-coefficient voltage VBG plus the voltage drop across resistor R5 plus the gate-source voltage |VGSP1| of the low-voltage PMOS transistor PM1, i.e., VDD = VBG + Iptat*R5 + |VGSP1|. The internal power supply VDD, as the power supply voltage of the bandgap reference circuit, ensures the normal operation of the bandgap reference circuit. When the power supply VBAT is powered on, the gate voltage of the high-voltage NMOS transistor NDM1 is pulled up through resistor R1, turning on the high-voltage NMOS transistor NDM1. The current generated by the conduction of the high-voltage NMOS transistor NDM1 creates a voltage drop through resistor R2 to pull up the gate voltage of the low-voltage NMOS transistor NM1, turning on the low-voltage NMOS transistor NM1. The Zener diode Z1 clamps the gate-source voltage VGSN1 of the high-voltage NMOS transistor NDM1 and the drain-source voltage VDSN1 of the low-voltage NMOS transistor NM1 below the clamping voltage Vclamp1 of the Zener diode Z1, preventing the gate-source of the high-voltage NMOS transistor NDM1 and the drain-source of the low-voltage NMOS transistor NM1 from being broken down. The output current Istart of the high-voltage Wilson current source is equal to the gate-source voltage VGSN1 of the low-voltage NMOS transistor NM1 divided by resistor R2, i.e., Istart = VGSN1 / R2. The current Istart flows into the diode-connected low-voltage NMOS transistor NM4 through the current mirror composed of the high-voltage PMOS transistors PDM1 and PDM2, raising the gate voltages of the low-voltage NMOS transistor NM4, the low-voltage NMOS transistor NM5, and the high-voltage NMOS transistor NDM2 and thus turning them on. After conduction, the high-voltage NMOS transistor NDM2 pulls down the gate voltages of the high-voltage PMOS transistors PDM3 and PDM4 through the bias voltage VB1, causing the high-voltage PMOS transistors PDM3 and PDM4 to conduct; after conduction, the low-voltage NMOS transistor NM5 pulls down the gate voltages of the low-voltage PMOS transistors PM1, PM2, and PM3 through the bias voltage VB2, causing the low-voltage PMOS transistors PM1, PM2, and PM3 to conduct; the current of the low-voltage PMOS transistor PM3 flows into the NMOS current mirror composed of the low-voltage NMOS transistors NM2 and NM3, causing the low-voltage NMOS transistors NM2 and NM3 to conduct; the current Istart that previously flowed into the low-voltage NMOS transistor NM4 flows into the low-voltage NMOS transistor NM3, thereby turning off the low-voltage NMOS transistors NM4 and NM5 and the high-voltage NMOS transistor NDM2, ensuring that the startup circuit is turned off after the circuit starts up and operates normally.